MIPS mem_barrier

[rixed at happyleptic.org]

In compiler.h, is defined mem_barrier() which is used if I understand
correctly when accessing the memory mapped IO, to force the CPU to
ensure previous writes/reads are commited to the bus before the
following ones (gcc being independantly informed to keep the source code
reads/writes ordering by the use of volatile).

On MIPS on Linux, I see that the mem_barrier consist of several nops.

I do not understand these nops, since first MIPS ISA there exist
a SYNC instruction that forces the CPU to flush reads/writes for this
very purpose.

Also, this instruction is certainly faster, and more portable than a
sequence of nops.

But I'm certain that the original author knew more about MIPS than I do,
that's why I'm asking here for a clue.