915gm/945gm/XAA lockup with gray blocks when switching video mode

[Peter Clifton]

On Fri, 2007-10-12 at 20:13 +0100, Peter Clifton wrote:

> The following fixes it for me at least:
> 
> --- xserver-xorg-video-intel-2.1.1.orig/src/i830_driver.c	2007-10-12 14:37:57.000000000 +0100
> +++ xserver-xorg-video-intel-2.1.1/src/i830_driver.c	2007-10-12 14:39:08.000000000 +0100
> @@ -1985,11 +1985,12 @@
>     OUTREG(VCLK_DIVISOR_VGA1, pI830->saveVCLK_DIVISOR_VGA1);
>     OUTREG(VCLK_POST_DIV, pI830->saveVCLK_POST_DIV);
>  
> -   for(i = 0; i < 256; i++) {
> -      OUTREG(PALETTE_A + (i << 2), pI830->savePaletteA[i]);
> +   if ((INREG(PIPEACONF) & PIPEACONF_ENABLE)) {
> +      for(i = 0; i < 256; i++) {
> +         OUTREG(PALETTE_A + (i << 2), pI830->savePaletteA[i]);
> +      }
>     }
> -   
> -   if(xf86_config->num_crtc == 2) {
> +   if (xf86_config->num_crtc == 2 && (INREG(PIPEBCONF) & PIPEBCONF_ENABLE)) {
>        for(i= 0; i < 256; i++) {
>           OUTREG(PALETTE_B + (i << 2), pI830->savePaletteB[i]);
>        }


Strictly speaking, we're now not restoring the full set of the video
chips registers, so perhaps if your bios knows how to re-program the
chip and say connect an external monitor to the other pipe, we'll have
left it with a bad palette. IMO, thats better than the crashes, and
perhaps something Intel will sort out "properly". I didn't want to delve
into how complex it might be to deliberately program both pipelines just
for the sake of restoring their palette regs.

The "correct"? fix might be to save the palette regs when the crtc
pipleine is first used by the X11 driver, then re-program it before we
shut it off. That way, only palettes which have been touched are
re-programmed.

This would only manifest if X11 starts with some pipeline(s) disabled,
then X11 enables both over the course of its runtime (and set their
palettes). And.. then the BIOS would need to use both pipelines again.


I noticed a similar register not-cleanly reinit in the probing of the tv
output. A patch to fix this is:

Index: xserver-xorg-video-intel-2.1.1/src/i830_tv.c
===================================================================
--- xserver-xorg-video-intel-2.1.1.orig/src/i830_tv.c	2007-10-12 11:57:15.000000000 +0100
+++ xserver-xorg-video-intel-2.1.1/src/i830_tv.c	2007-10-12 11:57:18.000000000 +0100
@@ -1361,6 +1361,7 @@
     if (crtc)
     {
         i830_tv_detect_type (crtc, output);
+        i830_tv_restore (output);
         i830ReleaseLoadDetectPipe (output, dpms_mode);
     }
 

Best wishes,

-- 
Peter Clifton

Electrical Engineering Division,
Engineering Department,
University of Cambridge,
9, JJ Thomson Avenue,
Cambridge
CB3 0FA

Tel: +44 (0)7729 980173 - (No signal in the lab!)