EXA support for nv driver

Fri Aug 26 08:37:59 PDT 2005

On Fri, 2005-08-26 at 09:43 +0200, Lars Knoll wrote:
> On Friday 26 August 2005 08:58, Benjamin Herrenschmidt wrote:
> > On Fri, 2005-08-26 at 08:41 +0200, Lars Knoll wrote:
> > > Wouldn't mapping the actual RAM page be better anyway, as that one could
> > > be mapped cachable, whereas the GART memory usually is write combining
> > > only?
> >
> > Mapping cacheable ? Hrm... I'm not sure that would work with many
> > chipsets as I'm not sure they would trigger proper coherency protocol
> > when beeing accessed by the card. I currently map them non-cacheable on
> > Macs but it might be worth trying on some chipsets I suppose...
> 
> Hmmm... true. I remember vaguely having read that some newer chipsets support 
> this, but I couldn't find the reference anymore.

You mean PCIe chipsets? ;) AFAIK AGP is explicitly specified not to be
cache coherent.

-- 
Earthling Michel Dänzer      |     Debian (powerpc), X and DRI developer
Libre software enthusiast    |   http://svcs.affero.net/rm.php?r=daenzer