[PATCH] radeon: r200 depth buffers are always tiled

[Dave Airlie]

On Mon, Dec 5, 2011 at 9:13 PM, Roland Scheidegger
<rscheidegger_lists at hispeed.ch> wrote:
> Am 05.12.2011 21:51, schrieb Dave Airlie:
>> On Mon, Dec 5, 2011 at 8:08 PM, Roland Scheidegger
>> <rscheidegger_lists at hispeed.ch> wrote:
>>> IIRC this is not only true for r200. Might be true for r300 too, and
>>> r100 (possibly not rv100) even. Looks good otherwise though.
>>
>> Yeah I've been trying to solve it as I find it, I found it definitely
>> on rv250/rv280, r200 I'm not 100% sure on but will check that.
>>
>> my rv100 definitely doesn't need it, but I don't have simple access to
>> an rv200 or r100 yet, might be able to get an M7 tomorrow.
>>
>> Good point for r300->r500 should probably check that, but we should be
>> enabling tiling on those by default anyways.
>>
>
> I think it might be always tiled for anything below r600 except the
> rv100 (and the igp-based rv100s). Of course, with different tiling patterns.
> I'm not 100% sure though, but I remember some differences there between
> r100 and rv100 (it is possible though just the tiling pattern was
> different).

Okay so I've tested now on an M7 laptop, and it has always tiled depth,
r200, rv250 and rv280 are always tiled, and my rv100 has never tiled.

The code in mesa now passes readPixSanity on all the ancient
crap^Wradeons I can beg or borrow access to.

In theory color tiling should also work fine enabled, and it seems to,
not seeing and piglit regressions apart from noise between
tiled/untiled runs.

Dave.