[PATCH] radeon: r200 depth buffers are always tiled
rscheidegger_lists at hispeed.ch
Mon Dec 5 13:13:11 PST 2011
Am 05.12.2011 21:51, schrieb Dave Airlie:
> On Mon, Dec 5, 2011 at 8:08 PM, Roland Scheidegger
> <rscheidegger_lists at hispeed.ch> wrote:
>> IIRC this is not only true for r200. Might be true for r300 too, and
>> r100 (possibly not rv100) even. Looks good otherwise though.
> Yeah I've been trying to solve it as I find it, I found it definitely
> on rv250/rv280, r200 I'm not 100% sure on but will check that.
> my rv100 definitely doesn't need it, but I don't have simple access to
> an rv200 or r100 yet, might be able to get an M7 tomorrow.
> Good point for r300->r500 should probably check that, but we should be
> enabling tiling on those by default anyways.
I think it might be always tiled for anything below r600 except the
rv100 (and the igp-based rv100s). Of course, with different tiling patterns.
I'm not 100% sure though, but I remember some differences there between
r100 and rv100 (it is possible though just the tiling pattern was
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