xf86-video-intel: 4 commits - src/i965_render.c src/intel_batchbuffer.c src/intel_driver.h src/intel_module.c
Eric Anholt
anholt at kemper.freedesktop.org
Mon May 9 22:57:38 PDT 2011
src/i965_render.c | 4
src/intel_batchbuffer.c | 4
src/intel_driver.h | 9 +
src/intel_module.c | 352 ++++++++++++------------------------------------
4 files changed, 106 insertions(+), 263 deletions(-)
New commits:
commit 79e59fb2a047b1e733a7b0dee608db3311391725
Author: Eric Anholt <eric at anholt.net>
Date: Fri May 6 12:40:12 2011 -0700
Add support for Ivybridge chipset.
This gets display and 2D blit acceleration up and running. No Render
acceleration is provided yet.
diff --git a/src/i965_render.c b/src/i965_render.c
index bfcd3f2..b76107d 100644
--- a/src/i965_render.c
+++ b/src/i965_render.c
@@ -182,6 +182,10 @@ i965_check_composite(int op,
int width, int height)
{
ScrnInfoPtr scrn = xf86Screens[dest_picture->pDrawable->pScreen->myNum];
+ intel_screen_private *intel = intel_get_screen_private(scrn);
+
+ if (IS_GEN7(intel))
+ return FALSE;
/* Check for unsupported compositing operations. */
if (op >= sizeof(i965_blend_op) / sizeof(i965_blend_op[0])) {
diff --git a/src/intel_batchbuffer.c b/src/intel_batchbuffer.c
index 95eca43..d0a41aa 100644
--- a/src/intel_batchbuffer.c
+++ b/src/intel_batchbuffer.c
@@ -211,7 +211,9 @@ void intel_batch_submit(ScrnInfoPtr scrn)
ret = drm_intel_bo_mrb_exec(intel->batch_bo,
intel->batch_used*4,
NULL, 0, 0xffffffff,
- IS_GEN6(intel) ? intel->current_batch: I915_EXEC_DEFAULT);
+ (HAS_BLT(intel) ?
+ intel->current_batch:
+ I915_EXEC_DEFAULT));
}
if (ret != 0) {
diff --git a/src/intel_driver.h b/src/intel_driver.h
index 2e72177..4a584fe 100644
--- a/src/intel_driver.h
+++ b/src/intel_driver.h
@@ -184,6 +184,13 @@
#define PCI_CHIP_SANDYBRIDGE_M_GT2_PLUS 0x0126
#define PCI_CHIP_SANDYBRIDGE_BRIDGE_S 0x0108 /* Server */
#define PCI_CHIP_SANDYBRIDGE_S_GT 0x010A
+
+#define PCI_CHIP_IVYBRIDGE_M_GT1 0x0156
+#define PCI_CHIP_IVYBRIDGE_M_GT2 0x0166
+#define PCI_CHIP_IVYBRIDGE_D_GT1 0x0152
+#define PCI_CHIP_IVYBRIDGE_D_GT2 0x0162
+#define PCI_CHIP_IVYBRIDGE_S_GT1 0x015a
+
#endif
#define I85X_CAPID 0x44
@@ -209,6 +216,7 @@
#define IS_GEN4(intel) IS_GENx(intel, 4)
#define IS_GEN5(intel) IS_GENx(intel, 5)
#define IS_GEN6(intel) IS_GENx(intel, 6)
+#define IS_GEN7(intel) IS_GENx(intel, 7)
/* Some chips have specific errata (or limits) that we need to workaround. */
#define IS_I830(intel) (DEVICE_ID((intel)->PciInfo) == PCI_CHIP_I830_M)
@@ -222,6 +230,7 @@
/* supports Y tiled surfaces (pre-965 Mesa isn't ready yet) */
#define SUPPORTS_YTILING(pI810) (INTEL_INFO(intel)->gen >= 40)
+#define HAS_BLT(pI810) (INTEL_INFO(intel)->gen >= 60)
extern SymTabRec *intel_chipsets;
diff --git a/src/intel_module.c b/src/intel_module.c
index 6cf5951..6aeaeeb 100644
--- a/src/intel_module.c
+++ b/src/intel_module.c
@@ -73,6 +73,10 @@ static const struct intel_device_info intel_sandybridge_info = {
.gen = 60,
};
+static const struct intel_device_info intel_ivybridge_info = {
+ .gen = 70,
+};
+
static const SymTabRec _intel_chipsets[] = {
{PCI_CHIP_I810, "i810"},
{PCI_CHIP_I810_DC100, "i810-dc100"},
@@ -116,6 +120,11 @@ static const SymTabRec _intel_chipsets[] = {
{PCI_CHIP_SANDYBRIDGE_M_GT2, "Sandybridge" },
{PCI_CHIP_SANDYBRIDGE_M_GT2_PLUS, "Sandybridge" },
{PCI_CHIP_SANDYBRIDGE_S_GT, "Sandybridge" },
+ {PCI_CHIP_IVYBRIDGE_M_GT1, "Ivybridge Mobile GT1" },
+ {PCI_CHIP_IVYBRIDGE_M_GT2, "Ivybridge Mobile GT2" },
+ {PCI_CHIP_IVYBRIDGE_D_GT1, "Ivybridge Desktop GT1" },
+ {PCI_CHIP_IVYBRIDGE_D_GT2, "Ivybridge Desktop GT2" },
+ {PCI_CHIP_IVYBRIDGE_S_GT1, "Ivybridge Server GT1" },
{-1, NULL}
};
SymTabRec *intel_chipsets = (SymTabRec *) _intel_chipsets;
@@ -173,6 +182,13 @@ static const struct pci_id_match intel_device_match[] = {
INTEL_DEVICE_MATCH (PCI_CHIP_SANDYBRIDGE_M_GT2_PLUS, &intel_sandybridge_info ),
INTEL_DEVICE_MATCH (PCI_CHIP_SANDYBRIDGE_S_GT, &intel_sandybridge_info ),
+
+ INTEL_DEVICE_MATCH (PCI_CHIP_IVYBRIDGE_M_GT1, &intel_ivybridge_info ),
+ INTEL_DEVICE_MATCH (PCI_CHIP_IVYBRIDGE_M_GT2, &intel_ivybridge_info ),
+ INTEL_DEVICE_MATCH (PCI_CHIP_IVYBRIDGE_D_GT1, &intel_ivybridge_info ),
+ INTEL_DEVICE_MATCH (PCI_CHIP_IVYBRIDGE_D_GT2, &intel_ivybridge_info ),
+ INTEL_DEVICE_MATCH (PCI_CHIP_IVYBRIDGE_S_GT1, &intel_ivybridge_info ),
+
{ 0, 0, 0 },
};
commit 792738adfc5164d30358f045875dfc9b199a46da
Author: Eric Anholt <eric at anholt.net>
Date: Fri May 6 13:14:25 2011 -0700
Remove the static list of PciChipset and construct it from SymTabRec instead.
This is one less place the new hardware enabler has to spam the
chipset in. The PciChipset is just a match structure from PciId to
the SymTabRec entry token, and our SymTabRec entry tokens are just the
PciId, so it's trivial to construct.
Acked-by: Kenneth Graunke <kenneth at whitecape.org>
diff --git a/src/intel_module.c b/src/intel_module.c
index be34e7f..6cf5951 100644
--- a/src/intel_module.c
+++ b/src/intel_module.c
@@ -176,51 +176,6 @@ static const struct pci_id_match intel_device_match[] = {
{ 0, 0, 0 },
};
-static PciChipsets intel_pci_chipsets[] = {
- {PCI_CHIP_I810, PCI_CHIP_I810, NULL},
- {PCI_CHIP_I810_DC100, PCI_CHIP_I810_DC100, NULL},
- {PCI_CHIP_I810_E, PCI_CHIP_I810_E, NULL},
- {PCI_CHIP_I815, PCI_CHIP_I815, NULL},
- {PCI_CHIP_I830_M, PCI_CHIP_I830_M, NULL},
- {PCI_CHIP_845_G, PCI_CHIP_845_G, NULL},
- {PCI_CHIP_I854, PCI_CHIP_I854, NULL},
- {PCI_CHIP_I855_GM, PCI_CHIP_I855_GM, NULL},
- {PCI_CHIP_I865_G, PCI_CHIP_I865_G, NULL},
- {PCI_CHIP_I915_G, PCI_CHIP_I915_G, NULL},
- {PCI_CHIP_E7221_G, PCI_CHIP_E7221_G, NULL},
- {PCI_CHIP_I915_GM, PCI_CHIP_I915_GM, NULL},
- {PCI_CHIP_I945_G, PCI_CHIP_I945_G, NULL},
- {PCI_CHIP_I945_GM, PCI_CHIP_I945_GM, NULL},
- {PCI_CHIP_I945_GME, PCI_CHIP_I945_GME, NULL},
- {PCI_CHIP_PINEVIEW_M, PCI_CHIP_PINEVIEW_M, NULL},
- {PCI_CHIP_PINEVIEW_G, PCI_CHIP_PINEVIEW_G, NULL},
- {PCI_CHIP_I965_G, PCI_CHIP_I965_G, NULL},
- {PCI_CHIP_G35_G, PCI_CHIP_G35_G, NULL},
- {PCI_CHIP_I965_Q, PCI_CHIP_I965_Q, NULL},
- {PCI_CHIP_I946_GZ, PCI_CHIP_I946_GZ, NULL},
- {PCI_CHIP_I965_GM, PCI_CHIP_I965_GM, NULL},
- {PCI_CHIP_I965_GME, PCI_CHIP_I965_GME, NULL},
- {PCI_CHIP_G33_G, PCI_CHIP_G33_G, NULL},
- {PCI_CHIP_Q35_G, PCI_CHIP_Q35_G, NULL},
- {PCI_CHIP_Q33_G, PCI_CHIP_Q33_G, NULL},
- {PCI_CHIP_GM45_GM, PCI_CHIP_GM45_GM, NULL},
- {PCI_CHIP_G45_E_G, PCI_CHIP_G45_E_G, NULL},
- {PCI_CHIP_G45_G, PCI_CHIP_G45_G, NULL},
- {PCI_CHIP_Q45_G, PCI_CHIP_Q45_G, NULL},
- {PCI_CHIP_G41_G, PCI_CHIP_G41_G, NULL},
- {PCI_CHIP_B43_G, PCI_CHIP_B43_G, NULL},
- {PCI_CHIP_IRONLAKE_D_G, PCI_CHIP_IRONLAKE_D_G, NULL},
- {PCI_CHIP_IRONLAKE_M_G, PCI_CHIP_IRONLAKE_M_G, NULL},
- {PCI_CHIP_SANDYBRIDGE_GT1, PCI_CHIP_SANDYBRIDGE_GT1, NULL},
- {PCI_CHIP_SANDYBRIDGE_GT2, PCI_CHIP_SANDYBRIDGE_GT2, NULL},
- {PCI_CHIP_SANDYBRIDGE_GT2_PLUS, PCI_CHIP_SANDYBRIDGE_GT2_PLUS, NULL},
- {PCI_CHIP_SANDYBRIDGE_M_GT1, PCI_CHIP_SANDYBRIDGE_M_GT1, NULL},
- {PCI_CHIP_SANDYBRIDGE_M_GT2, PCI_CHIP_SANDYBRIDGE_M_GT2, NULL},
- {PCI_CHIP_SANDYBRIDGE_M_GT2_PLUS, PCI_CHIP_SANDYBRIDGE_M_GT2_PLUS, NULL},
- {PCI_CHIP_SANDYBRIDGE_S_GT, PCI_CHIP_SANDYBRIDGE_S_GT, NULL},
- {-1, -1, NULL }
-};
-
void intel_detect_chipset(ScrnInfoPtr scrn,
struct pci_device *pci,
struct intel_chipset *chipset)
@@ -311,6 +266,8 @@ static Bool intel_pci_probe (DriverPtr driver,
intptr_t match_data)
{
ScrnInfoPtr scrn;
+ PciChipsets intel_pci_chipsets[ARRAY_SIZE(intel_chipsets)];
+ int i;
chipset_info = (void *)match_data;
@@ -330,6 +287,12 @@ static Bool intel_pci_probe (DriverPtr driver,
#endif
}
+ for (i = 0; i < ARRAY_SIZE(intel_chipsets); i++) {
+ intel_pci_chipsets[i].numChipset = intel_chipsets[i].token;
+ intel_pci_chipsets[i].PCIid = intel_chipsets[i].token;
+ intel_pci_chipsets[i].dummy = NULL;
+ }
+
scrn = xf86ConfigPciEntity(NULL, 0, entity_num, intel_pci_chipsets,
NULL, NULL, NULL, NULL, NULL);
if (scrn != NULL) {
commit 583e80dfa12d6c73fc677c81cb605a07b2768979
Author: Eric Anholt <eric at anholt.net>
Date: Fri May 6 13:00:53 2011 -0700
Use the existing deviceID -> name mapping in SymTabRec instead of duping it.
We need to have this array anyway for the xf86 interfaces, apparently,
so just store the name in one location. This drops the i852/i855
subdevice distinction in the name printed, but I haven't seen us ever
care about that.
Acked-by: Kenneth Graunke <kenneth at whitecape.org>
diff --git a/src/intel_module.c b/src/intel_module.c
index ff26523..be34e7f 100644
--- a/src/intel_module.c
+++ b/src/intel_module.c
@@ -225,148 +225,18 @@ void intel_detect_chipset(ScrnInfoPtr scrn,
struct pci_device *pci,
struct intel_chipset *chipset)
{
- uint32_t capid;
+ int i;
chipset->info = chipset_info;
- switch (DEVICE_ID(pci)) {
- case PCI_CHIP_I810:
- chipset->name = "i810";
- break;
- case PCI_CHIP_I810_DC100:
- chipset->name = "i810-dc100";
- break;
- case PCI_CHIP_I810_E:
- chipset->name = "i810e";
- break;
- case PCI_CHIP_I815:
- chipset->name = "i815";
- break;
- case PCI_CHIP_I830_M:
- chipset->name = "830M";
- break;
- case PCI_CHIP_845_G:
- chipset->name = "845G";
- break;
- case PCI_CHIP_I854:
- chipset->name = "854";
- break;
- case PCI_CHIP_I855_GM:
- /* Check capid register to find the chipset variant */
- pci_device_cfg_read_u32(pci, &capid, I85X_CAPID);
- chipset->variant =
- (capid >> I85X_VARIANT_SHIFT) & I85X_VARIANT_MASK;
- switch (chipset->variant) {
- case I855_GM:
- chipset->name = "855GM";
- break;
- case I855_GME:
- chipset->name = "855GME";
- break;
- case I852_GM:
- chipset->name = "852GM";
- break;
- case I852_GME:
- chipset->name = "852GME";
- break;
- default:
- xf86DrvMsg(scrn->scrnIndex, X_INFO,
- "Unknown 852GM/855GM variant: 0x%x)\n",
- chipset->variant);
- chipset->name = "852GM/855GM (unknown variant)";
- break;
- }
- break;
- case PCI_CHIP_I865_G:
- chipset->name = "865G";
- break;
- case PCI_CHIP_I915_G:
- chipset->name = "915G";
- break;
- case PCI_CHIP_E7221_G:
- chipset->name = "E7221 (i915)";
- break;
- case PCI_CHIP_I915_GM:
- chipset->name = "915GM";
- break;
- case PCI_CHIP_I945_G:
- chipset->name = "945G";
- break;
- case PCI_CHIP_I945_GM:
- chipset->name = "945GM";
- break;
- case PCI_CHIP_I945_GME:
- chipset->name = "945GME";
- break;
- case PCI_CHIP_PINEVIEW_M:
- chipset->name = "Pineview GM";
- break;
- case PCI_CHIP_PINEVIEW_G:
- chipset->name = "Pineview G";
- break;
- case PCI_CHIP_I965_G:
- chipset->name = "965G";
- break;
- case PCI_CHIP_G35_G:
- chipset->name = "G35";
- break;
- case PCI_CHIP_I965_Q:
- chipset->name = "965Q";
- break;
- case PCI_CHIP_I946_GZ:
- chipset->name = "946GZ";
- break;
- case PCI_CHIP_I965_GM:
- chipset->name = "965GM";
- break;
- case PCI_CHIP_I965_GME:
- chipset->name = "965GME/GLE";
- break;
- case PCI_CHIP_G33_G:
- chipset->name = "G33";
- break;
- case PCI_CHIP_Q35_G:
- chipset->name = "Q35";
- break;
- case PCI_CHIP_Q33_G:
- chipset->name = "Q33";
- break;
- case PCI_CHIP_GM45_GM:
- chipset->name = "GM45";
- break;
- case PCI_CHIP_G45_E_G:
- chipset->name = "4 Series";
- break;
- case PCI_CHIP_G45_G:
- chipset->name = "G45/G43";
- break;
- case PCI_CHIP_Q45_G:
- chipset->name = "Q45/Q43";
- break;
- case PCI_CHIP_G41_G:
- chipset->name = "G41";
- break;
- case PCI_CHIP_B43_G:
- chipset->name = "B43";
- break;
- case PCI_CHIP_IRONLAKE_D_G:
- chipset->name = "Clarkdale";
- break;
- case PCI_CHIP_IRONLAKE_M_G:
- chipset->name = "Arrandale";
- break;
- case PCI_CHIP_SANDYBRIDGE_GT1:
- case PCI_CHIP_SANDYBRIDGE_GT2:
- case PCI_CHIP_SANDYBRIDGE_GT2_PLUS:
- case PCI_CHIP_SANDYBRIDGE_M_GT1:
- case PCI_CHIP_SANDYBRIDGE_M_GT2:
- case PCI_CHIP_SANDYBRIDGE_M_GT2_PLUS:
- case PCI_CHIP_SANDYBRIDGE_S_GT:
- chipset->name = "Sandybridge";
- break;
- default:
- chipset->name = "unknown chipset";
- break;
+ for (i = 0; intel_chipsets[i].name != NULL; i++) {
+ if (DEVICE_ID(pci) == intel_chipsets[i].token) {
+ chipset->name = intel_chipsets[i].name;
+ break;
+ }
+ }
+ if (intel_chipsets[i].name == NULL) {
+ chipset->name = "unknown chipset";
}
xf86DrvMsg(scrn->scrnIndex, X_INFO,
commit adf7bbd3a8758de6cdecbace42e399dd27188497
Author: Eric Anholt <eric at anholt.net>
Date: Fri May 6 12:56:53 2011 -0700
Store the chipset info struct in the PCI match struct, instead of a switch().
Acked-by: Kenneth Graunke <kenneth at whitecape.org>
diff --git a/src/intel_module.c b/src/intel_module.c
index 8416544..ff26523 100644
--- a/src/intel_module.c
+++ b/src/intel_module.c
@@ -39,6 +39,8 @@
#include <xf86drmMode.h>
+static struct intel_device_info *chipset_info;
+
static const struct intel_device_info intel_i81x_info = {
.gen = 10,
};
@@ -119,50 +121,58 @@ static const SymTabRec _intel_chipsets[] = {
SymTabRec *intel_chipsets = (SymTabRec *) _intel_chipsets;
#define INTEL_DEVICE_MATCH(d,i) \
-{ 0x8086, (d), PCI_MATCH_ANY, PCI_MATCH_ANY, 0, 0, (i) }
+ { 0x8086, (d), PCI_MATCH_ANY, PCI_MATCH_ANY, 0, 0, (intptr_t)(i) }
static const struct pci_id_match intel_device_match[] = {
- INTEL_DEVICE_MATCH (PCI_CHIP_I810, 0 ),
- INTEL_DEVICE_MATCH (PCI_CHIP_I810_DC100, 0 ),
- INTEL_DEVICE_MATCH (PCI_CHIP_I810_E, 0 ),
- INTEL_DEVICE_MATCH (PCI_CHIP_I815, 0 ),
- INTEL_DEVICE_MATCH (PCI_CHIP_I830_M, 0 ),
- INTEL_DEVICE_MATCH (PCI_CHIP_845_G, 0 ),
- INTEL_DEVICE_MATCH (PCI_CHIP_I854, 0 ),
- INTEL_DEVICE_MATCH (PCI_CHIP_I855_GM, 0 ),
- INTEL_DEVICE_MATCH (PCI_CHIP_I865_G, 0 ),
- INTEL_DEVICE_MATCH (PCI_CHIP_I915_G, 0 ),
- INTEL_DEVICE_MATCH (PCI_CHIP_E7221_G, 0 ),
- INTEL_DEVICE_MATCH (PCI_CHIP_I915_GM, 0 ),
- INTEL_DEVICE_MATCH (PCI_CHIP_I945_G, 0 ),
- INTEL_DEVICE_MATCH (PCI_CHIP_I945_GM, 0 ),
- INTEL_DEVICE_MATCH (PCI_CHIP_I945_GME, 0 ),
- INTEL_DEVICE_MATCH (PCI_CHIP_PINEVIEW_M, 0 ),
- INTEL_DEVICE_MATCH (PCI_CHIP_PINEVIEW_G, 0 ),
- INTEL_DEVICE_MATCH (PCI_CHIP_I965_G, 0 ),
- INTEL_DEVICE_MATCH (PCI_CHIP_G35_G, 0 ),
- INTEL_DEVICE_MATCH (PCI_CHIP_I965_Q, 0 ),
- INTEL_DEVICE_MATCH (PCI_CHIP_I946_GZ, 0 ),
- INTEL_DEVICE_MATCH (PCI_CHIP_I965_GM, 0 ),
- INTEL_DEVICE_MATCH (PCI_CHIP_I965_GME, 0 ),
- INTEL_DEVICE_MATCH (PCI_CHIP_G33_G, 0 ),
- INTEL_DEVICE_MATCH (PCI_CHIP_Q35_G, 0 ),
- INTEL_DEVICE_MATCH (PCI_CHIP_Q33_G, 0 ),
- INTEL_DEVICE_MATCH (PCI_CHIP_GM45_GM, 0 ),
- INTEL_DEVICE_MATCH (PCI_CHIP_G45_E_G, 0 ),
- INTEL_DEVICE_MATCH (PCI_CHIP_G45_G, 0 ),
- INTEL_DEVICE_MATCH (PCI_CHIP_Q45_G, 0 ),
- INTEL_DEVICE_MATCH (PCI_CHIP_G41_G, 0 ),
- INTEL_DEVICE_MATCH (PCI_CHIP_B43_G, 0 ),
- INTEL_DEVICE_MATCH (PCI_CHIP_IRONLAKE_D_G, 0 ),
- INTEL_DEVICE_MATCH (PCI_CHIP_IRONLAKE_M_G, 0 ),
- INTEL_DEVICE_MATCH (PCI_CHIP_SANDYBRIDGE_GT1, 0 ),
- INTEL_DEVICE_MATCH (PCI_CHIP_SANDYBRIDGE_GT2, 0 ),
- INTEL_DEVICE_MATCH (PCI_CHIP_SANDYBRIDGE_GT2_PLUS, 0 ),
- INTEL_DEVICE_MATCH (PCI_CHIP_SANDYBRIDGE_M_GT1, 0 ),
- INTEL_DEVICE_MATCH (PCI_CHIP_SANDYBRIDGE_M_GT2, 0 ),
- INTEL_DEVICE_MATCH (PCI_CHIP_SANDYBRIDGE_M_GT2_PLUS, 0 ),
- INTEL_DEVICE_MATCH (PCI_CHIP_SANDYBRIDGE_S_GT, 0 ),
+ INTEL_DEVICE_MATCH (PCI_CHIP_I810, &intel_i81x_info ),
+ INTEL_DEVICE_MATCH (PCI_CHIP_I810_DC100, &intel_i81x_info ),
+ INTEL_DEVICE_MATCH (PCI_CHIP_I810_E, &intel_i81x_info ),
+ INTEL_DEVICE_MATCH (PCI_CHIP_I815, &intel_i81x_info ),
+
+ INTEL_DEVICE_MATCH (PCI_CHIP_I830_M, &intel_i8xx_info ),
+ INTEL_DEVICE_MATCH (PCI_CHIP_845_G, &intel_i8xx_info ),
+ INTEL_DEVICE_MATCH (PCI_CHIP_I854, &intel_i8xx_info ),
+ INTEL_DEVICE_MATCH (PCI_CHIP_I855_GM, &intel_i8xx_info ),
+ INTEL_DEVICE_MATCH (PCI_CHIP_I865_G, &intel_i8xx_info ),
+
+ INTEL_DEVICE_MATCH (PCI_CHIP_I915_G, &intel_i915_info ),
+ INTEL_DEVICE_MATCH (PCI_CHIP_E7221_G, &intel_i915_info ),
+ INTEL_DEVICE_MATCH (PCI_CHIP_I915_GM, &intel_i915_info ),
+ INTEL_DEVICE_MATCH (PCI_CHIP_I945_G, &intel_i915_info ),
+ INTEL_DEVICE_MATCH (PCI_CHIP_I945_GM, &intel_i915_info ),
+ INTEL_DEVICE_MATCH (PCI_CHIP_I945_GME, &intel_i915_info ),
+
+ INTEL_DEVICE_MATCH (PCI_CHIP_G33_G, &intel_g33_info ),
+ INTEL_DEVICE_MATCH (PCI_CHIP_PINEVIEW_M, &intel_g33_info ),
+ INTEL_DEVICE_MATCH (PCI_CHIP_PINEVIEW_G, &intel_g33_info ),
+
+ INTEL_DEVICE_MATCH (PCI_CHIP_I965_G, &intel_i965_info ),
+ INTEL_DEVICE_MATCH (PCI_CHIP_G35_G, &intel_i965_info ),
+ INTEL_DEVICE_MATCH (PCI_CHIP_I965_Q, &intel_i965_info ),
+ INTEL_DEVICE_MATCH (PCI_CHIP_I946_GZ, &intel_i965_info ),
+ INTEL_DEVICE_MATCH (PCI_CHIP_I965_GM, &intel_i965_info ),
+ INTEL_DEVICE_MATCH (PCI_CHIP_I965_GME, &intel_i965_info ),
+ INTEL_DEVICE_MATCH (PCI_CHIP_Q35_G, &intel_i965_info ),
+ INTEL_DEVICE_MATCH (PCI_CHIP_Q33_G, &intel_i965_info ),
+
+ INTEL_DEVICE_MATCH (PCI_CHIP_GM45_GM, &intel_g4x_info ),
+ INTEL_DEVICE_MATCH (PCI_CHIP_G45_E_G, &intel_g4x_info ),
+ INTEL_DEVICE_MATCH (PCI_CHIP_G45_G, &intel_g4x_info ),
+ INTEL_DEVICE_MATCH (PCI_CHIP_Q45_G, &intel_g4x_info ),
+ INTEL_DEVICE_MATCH (PCI_CHIP_G41_G, &intel_g4x_info ),
+ INTEL_DEVICE_MATCH (PCI_CHIP_B43_G, &intel_g4x_info ),
+
+ INTEL_DEVICE_MATCH (PCI_CHIP_IRONLAKE_D_G, &intel_ironlake_info ),
+ INTEL_DEVICE_MATCH (PCI_CHIP_IRONLAKE_M_G, &intel_ironlake_info ),
+
+ INTEL_DEVICE_MATCH (PCI_CHIP_SANDYBRIDGE_GT1, &intel_sandybridge_info ),
+ INTEL_DEVICE_MATCH (PCI_CHIP_SANDYBRIDGE_GT2, &intel_sandybridge_info ),
+ INTEL_DEVICE_MATCH (PCI_CHIP_SANDYBRIDGE_GT2_PLUS, &intel_sandybridge_info ),
+ INTEL_DEVICE_MATCH (PCI_CHIP_SANDYBRIDGE_M_GT1, &intel_sandybridge_info ),
+ INTEL_DEVICE_MATCH (PCI_CHIP_SANDYBRIDGE_M_GT2, &intel_sandybridge_info ),
+ INTEL_DEVICE_MATCH (PCI_CHIP_SANDYBRIDGE_M_GT2_PLUS, &intel_sandybridge_info ),
+ INTEL_DEVICE_MATCH (PCI_CHIP_SANDYBRIDGE_S_GT, &intel_sandybridge_info ),
+
{ 0, 0, 0 },
};
@@ -217,34 +227,29 @@ void intel_detect_chipset(ScrnInfoPtr scrn,
{
uint32_t capid;
+ chipset->info = chipset_info;
+
switch (DEVICE_ID(pci)) {
case PCI_CHIP_I810:
chipset->name = "i810";
- chipset->info = &intel_i81x_info;
break;
case PCI_CHIP_I810_DC100:
chipset->name = "i810-dc100";
- chipset->info = &intel_i81x_info;
break;
case PCI_CHIP_I810_E:
chipset->name = "i810e";
- chipset->info = &intel_i81x_info;
break;
case PCI_CHIP_I815:
chipset->name = "i815";
- chipset->info = &intel_i81x_info;
break;
case PCI_CHIP_I830_M:
chipset->name = "830M";
- chipset->info = &intel_i8xx_info;
break;
case PCI_CHIP_845_G:
chipset->name = "845G";
- chipset->info = &intel_i8xx_info;
break;
case PCI_CHIP_I854:
chipset->name = "854";
- chipset->info = &intel_i8xx_info;
break;
case PCI_CHIP_I855_GM:
/* Check capid register to find the chipset variant */
@@ -271,111 +276,84 @@ void intel_detect_chipset(ScrnInfoPtr scrn,
chipset->name = "852GM/855GM (unknown variant)";
break;
}
- chipset->info = &intel_i8xx_info;
break;
case PCI_CHIP_I865_G:
chipset->name = "865G";
- chipset->info = &intel_i8xx_info;
break;
case PCI_CHIP_I915_G:
chipset->name = "915G";
- chipset->info = &intel_i915_info;
break;
case PCI_CHIP_E7221_G:
chipset->name = "E7221 (i915)";
- chipset->info = &intel_i915_info;
break;
case PCI_CHIP_I915_GM:
chipset->name = "915GM";
- chipset->info = &intel_i915_info;
break;
case PCI_CHIP_I945_G:
chipset->name = "945G";
- chipset->info = &intel_i915_info;
break;
case PCI_CHIP_I945_GM:
chipset->name = "945GM";
- chipset->info = &intel_i915_info;
break;
case PCI_CHIP_I945_GME:
chipset->name = "945GME";
- chipset->info = &intel_i915_info;
break;
case PCI_CHIP_PINEVIEW_M:
chipset->name = "Pineview GM";
- chipset->info = &intel_g33_info;
break;
case PCI_CHIP_PINEVIEW_G:
chipset->name = "Pineview G";
- chipset->info = &intel_g33_info;
break;
case PCI_CHIP_I965_G:
chipset->name = "965G";
- chipset->info = &intel_i965_info;
break;
case PCI_CHIP_G35_G:
chipset->name = "G35";
- chipset->info = &intel_i965_info;
break;
case PCI_CHIP_I965_Q:
chipset->name = "965Q";
- chipset->info = &intel_i965_info;
break;
case PCI_CHIP_I946_GZ:
chipset->name = "946GZ";
- chipset->info = &intel_i965_info;
break;
case PCI_CHIP_I965_GM:
chipset->name = "965GM";
- chipset->info = &intel_i965_info;
break;
case PCI_CHIP_I965_GME:
chipset->name = "965GME/GLE";
- chipset->info = &intel_i965_info;
break;
case PCI_CHIP_G33_G:
chipset->name = "G33";
- chipset->info = &intel_g33_info;
break;
case PCI_CHIP_Q35_G:
chipset->name = "Q35";
- chipset->info = &intel_g33_info;
break;
case PCI_CHIP_Q33_G:
chipset->name = "Q33";
- chipset->info = &intel_g33_info;
break;
case PCI_CHIP_GM45_GM:
chipset->name = "GM45";
- chipset->info = &intel_g4x_info;
break;
case PCI_CHIP_G45_E_G:
chipset->name = "4 Series";
- chipset->info = &intel_g4x_info;
break;
case PCI_CHIP_G45_G:
chipset->name = "G45/G43";
- chipset->info = &intel_g4x_info;
break;
case PCI_CHIP_Q45_G:
chipset->name = "Q45/Q43";
- chipset->info = &intel_g4x_info;
break;
case PCI_CHIP_G41_G:
chipset->name = "G41";
- chipset->info = &intel_g4x_info;
break;
case PCI_CHIP_B43_G:
chipset->name = "B43";
- chipset->info = &intel_g4x_info;
break;
case PCI_CHIP_IRONLAKE_D_G:
chipset->name = "Clarkdale";
- chipset->info = &intel_ironlake_info;
break;
case PCI_CHIP_IRONLAKE_M_G:
chipset->name = "Arrandale";
- chipset->info = &intel_ironlake_info;
break;
case PCI_CHIP_SANDYBRIDGE_GT1:
case PCI_CHIP_SANDYBRIDGE_GT2:
@@ -385,7 +363,6 @@ void intel_detect_chipset(ScrnInfoPtr scrn,
case PCI_CHIP_SANDYBRIDGE_M_GT2_PLUS:
case PCI_CHIP_SANDYBRIDGE_S_GT:
chipset->name = "Sandybridge";
- chipset->info = &intel_sandybridge_info;
break;
default:
chipset->name = "unknown chipset";
@@ -465,6 +442,8 @@ static Bool intel_pci_probe (DriverPtr driver,
{
ScrnInfoPtr scrn;
+ chipset_info = (void *)match_data;
+
if (!has_kernel_mode_setting(device)) {
#if KMS_ONLY
return FALSE;
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