xf86-video-ati: Branch 'master' - 3 commits

[Alex Deucher]

 src/radeon.h          |    6 ++++--
 src/radeon_atombios.c |    6 ++++--
 src/radeon_crtc.c     |    7 ++++++-
 src/radeon_reg.h      |    3 +++
 4 files changed, 17 insertions(+), 5 deletions(-)

New commits:
commit 95b56275d80dcee48a7927df124602c34cd72235
Author: Alex Deucher <alexdeucher at gmail.com>
Date:   Wed Jan 27 15:48:25 2010 -0500

    avivo: add some hotplug detect regs

diff --git a/src/radeon_reg.h b/src/radeon_reg.h
index e656f5f..5895da5 100644
--- a/src/radeon_reg.h
+++ b/src/radeon_reg.h
@@ -4020,6 +4020,9 @@
 #define AVIVO_GPIO_2                        0x7e50
 #define AVIVO_GPIO_3                        0x7e60
 
+#define AVIVO_DC_GPIO_HPD_MASK              0x7e90
+#define AVIVO_DC_GPIO_HPD_A                 0x7e94
+#define AVIVO_DC_GPIO_HPD_EN                0x7e98
 #define AVIVO_DC_GPIO_HPD_Y                 0x7e9c
 
 #define AVIVO_I2C_STATUS					0x7d30
commit 5a4327f7784361933484895c9af751ccfa242d48
Author: Alex Deucher <alexdeucher at gmail.com>
Date:   Tue Jan 26 16:06:00 2010 -0500

    radeon: minor pll updates
    
    add new fixed post divider option

diff --git a/src/radeon.h b/src/radeon.h
index 10710a8..adc848d 100644
--- a/src/radeon.h
+++ b/src/radeon.h
@@ -277,10 +277,12 @@ typedef struct {
 #define RADEON_PLL_PREFER_HIGH_POST_DIV (1 << 9)
 #define RADEON_PLL_USE_FRAC_FB_DIV      (1 << 10)
 #define RADEON_PLL_PREFER_CLOSEST_LOWER (1 << 11)
+#define RADEON_PLL_USE_POST_DIV    (1 << 12)
 
 typedef struct {
-    uint16_t          reference_freq;
-    uint16_t          reference_div;
+    uint32_t          reference_freq;
+    uint32_t          reference_div;
+    uint32_t          post_div;
     uint32_t          pll_in_min;
     uint32_t          pll_in_max;
     uint32_t          pll_out_min;
diff --git a/src/radeon_crtc.c b/src/radeon_crtc.c
index 4e8b490..fd2c38c 100644
--- a/src/radeon_crtc.c
+++ b/src/radeon_crtc.c
@@ -144,6 +144,8 @@ RADEONComputePLL(RADEONPLLPtr pll,
 {
     uint32_t min_ref_div = pll->min_ref_div;
     uint32_t max_ref_div = pll->max_ref_div;
+    uint32_t min_post_div = pll->min_post_div;
+    uint32_t max_post_div = pll->max_post_div;
     uint32_t min_fractional_feed_div = 0;
     uint32_t max_fractional_feed_div = 0;
     uint32_t best_vco = pll->best_vco;
@@ -174,12 +176,15 @@ RADEONComputePLL(RADEONPLLPtr pll,
 	}
     }
 
+    if (flags & RADEON_PLL_USE_POST_DIV)
+	min_post_div = max_post_div = pll->post_div;
+
     if (flags & RADEON_PLL_USE_FRAC_FB_DIV) {
 	min_fractional_feed_div = pll->min_frac_feedback_div;
 	max_fractional_feed_div = pll->max_frac_feedback_div;
     }
 
-    for (post_div = pll->min_post_div; post_div <= pll->max_post_div; ++post_div) {
+    for (post_div = min_post_div; post_div <= max_post_div; ++post_div) {
 	uint32_t ref_div;
 
 	if ((flags & RADEON_PLL_NO_ODD_POST_DIV) && (post_div & 1))
commit cbd642af7c76469d701471daea0c8d167567ccf8
Author: Alex Deucher <alexdeucher at gmail.com>
Date:   Tue Jan 26 12:03:45 2010 -0500

    radeon: use mmio bar size rather than hardcoded number for register ops
    
    newer asics have larger mmio bars

diff --git a/src/radeon_atombios.c b/src/radeon_atombios.c
index b19e653..d6c58bc 100644
--- a/src/radeon_atombios.c
+++ b/src/radeon_atombios.c
@@ -2691,13 +2691,14 @@ UINT32
 CailReadATIRegister(VOID* CAIL, UINT32 idx)
 {
     ScrnInfoPtr pScrn = xf86Screens[((atomBiosHandlePtr)CAIL)->scrnIndex];
+    RADEONInfoPtr info = RADEONPTR(pScrn);
     RADEONEntPtr pRADEONEnt = RADEONEntPriv(pScrn);
     unsigned char *RADEONMMIO = pRADEONEnt->MMIO;
     UINT32 ret;
     UINT32 mm_reg = idx << 2;
     CAILFUNC(CAIL);
 
-    if (mm_reg < 0x10000)
+    if (mm_reg < info->MMIOSize)
 	ret = INREG(mm_reg);
     else {
 	OUTREG(RADEON_MM_INDEX, mm_reg);
@@ -2712,12 +2713,13 @@ VOID
 CailWriteATIRegister(VOID *CAIL, UINT32 idx, UINT32 data)
 {
     ScrnInfoPtr pScrn = xf86Screens[((atomBiosHandlePtr)CAIL)->scrnIndex];
+    RADEONInfoPtr info = RADEONPTR(pScrn);
     RADEONEntPtr pRADEONEnt = RADEONEntPriv(pScrn);
     unsigned char *RADEONMMIO = pRADEONEnt->MMIO;
     UINT32 mm_reg = idx << 2;
     CAILFUNC(CAIL);
 
-    if (mm_reg < 0x10000)
+    if (mm_reg < info->MMIOSize)
 	OUTREG(mm_reg, data);
     else {
 	OUTREG(RADEON_MM_INDEX, mm_reg);