xf86-video-ati: Branch 'radeon-vbos' - 45 commits
Dave Airlie
airlied at kemper.freedesktop.org
Sun Aug 1 00:04:57 PDT 2010
Rebased ref, commits from common ancestor:
commit 1fcc69b46915e62a8aa36da0a146d88288e18879
Author: Dave Airlie <airlied at redhat.com>
Date: Sun Aug 1 16:59:46 2010 +1000
radeon: add r300/r500 vbo support.
Doesn't work yet on my r5xx card.
Signed-off-by: Dave Airlie <airlied at redhat.com>
diff --git a/src/radeon_exa.c b/src/radeon_exa.c
index 7dd792e..f8e49b1 100644
--- a/src/radeon_exa.c
+++ b/src/radeon_exa.c
@@ -43,6 +43,7 @@
#include "radeon_probe.h"
#include "radeon_version.h"
#include "radeon_exa_shared.h"
+#include "radeon_vbo.h"
#include "xf86.h"
diff --git a/src/radeon_exa_funcs.c b/src/radeon_exa_funcs.c
index 2df6ccb..ca10a70 100644
--- a/src/radeon_exa_funcs.c
+++ b/src/radeon_exa_funcs.c
@@ -847,6 +847,11 @@ Bool FUNC_NAME(RADEONDrawInit)(ScreenPtr pScreen)
FUNC_NAME(R300PrepareComposite);
info->accel_state->exa->Composite = FUNC_NAME(RadeonComposite);
info->accel_state->exa->DoneComposite = FUNC_NAME(RadeonDoneComposite);
+
+#ifdef XF86DRM_MODE
+ if (info->cs)
+ radeon_vbo_init_lists(pScrn);
+#endif
} else
xf86DrvMsg(pScrn->scrnIndex, X_INFO, "EXA Composite requires CP on R5xx/IGP\n");
} else if (IS_R200_3D) {
@@ -895,12 +900,22 @@ Bool FUNC_NAME(RADEONDrawInit)(ScreenPtr pScreen)
#endif
info->accel_state->exa->maxY = 8191;
+ info->accel_state->verts_per_op = 4;
if (xf86ReturnOptValBool(info->Options, OPTION_EXA_VSYNC, FALSE)) {
xf86DrvMsg(pScrn->scrnIndex, X_INFO, "EXA VSync enabled\n");
info->accel_state->vsync = TRUE;
} else
info->accel_state->vsync = FALSE;
+#ifdef ACCEL_CP
+ if (info->accel_state->use_vbos) {
+ info->accel_state->exa->DoneComposite = RadeonDoneComposite_VBO;
+ info->accel_state->finish_op = radeon_finish_composite_op;
+ info->accel_state->vb_start_op = -1;
+ }
+#endif
+
+ RADEONVlineHelperClear(pScrn);
RADEONEngineInit(pScrn);
if (!exaDriverInit(pScreen, info->accel_state->exa)) {
diff --git a/src/radeon_exa_render.c b/src/radeon_exa_render.c
index da72416..72f0b78 100644
--- a/src/radeon_exa_render.c
+++ b/src/radeon_exa_render.c
@@ -54,6 +54,17 @@
#define ONLY_ONCE
#endif
+#ifdef ACCEL_CP
+static void RadeonCompositeTile_VBO(ScrnInfoPtr pScrn,
+ RADEONInfoPtr info,
+ PixmapPtr pDst,
+ int srcX, int srcY,
+ int maskX, int maskY,
+ int dstX, int dstY,
+ int w, int h);
+#endif
+
+
/* Only include the following (generic) bits once. */
#ifdef ONLY_ONCE
@@ -63,6 +74,7 @@ struct blendinfo {
uint32_t blend_cntl;
};
+
static struct blendinfo RadeonBlendOp[] = {
/* Clear */
{0, 0, RADEON_SRC_BLEND_GL_ZERO | RADEON_DST_BLEND_GL_ZERO},
@@ -1482,15 +1494,33 @@ static Bool FUNC_NAME(R300PrepareComposite)(int op, PicturePtr pSrcPicture,
pSrc, pMask, pDst);
/* have to execute switch after doing buffer sizing check as the latter flushes */
+ if (info->accel_state->use_vbos) {
+ if (pMask)
+ radeon_vbo_check(pScrn, 24);
+ else
+ radeon_vbo_check(pScrn, 16);
+ radeon_cp_start(pScrn);
+ }
+
RADEON_SWITCH_TO_3D();
- if (!FUNC_NAME(R300TextureSetup)(pSrcPicture, pSrc, 0))
+ if (!FUNC_NAME(R300TextureSetup)(pSrcPicture, pSrc, 0)) {
+ if (info->accel_state->use_vbos) {
+ radeon_ib_discard(pScrn);
+ radeon_vb_discard(pScrn);
+ }
return FALSE;
+ }
txenable = R300_TEX_0_ENABLE;
if (pMask != NULL) {
- if (!FUNC_NAME(R300TextureSetup)(pMaskPicture, pMask, 1))
+ if (!FUNC_NAME(R300TextureSetup)(pMaskPicture, pMask, 1)) {
+ if (info->accel_state->use_vbos) {
+ radeon_ib_discard(pScrn);
+ radeon_vb_discard(pScrn);
+ }
return FALSE;
+ }
txenable |= R300_TEX_1_ENABLE;
} else {
info->accel_state->is_transform[1] = FALSE;
@@ -2096,6 +2126,8 @@ static Bool FUNC_NAME(R300PrepareComposite)(int op, PicturePtr pSrcPicture,
OUT_ACCEL_REG(R300_VAP_VTX_SIZE, 4);
FINISH_ACCEL();
+ if (info->accel_state->vsync)
+ RADEONVlineHelperClear(pScrn);
return TRUE;
}
@@ -2280,10 +2312,11 @@ static void FUNC_NAME(RadeonCompositeTile)(ScrnInfoPtr pScrn,
} else
vtx_count = 4;
- if (info->accel_state->vsync)
- FUNC_NAME(RADEONWaitForVLine)(pScrn, pDst,
+ if (info->accel_state->vsync) {
+ FUNC_NAME(RADEONWaitForVLine)(pScrn, pDst,
radeon_pick_best_crtc(pScrn, dstX, dstX + w, dstY, dstY + h),
dstY, dstY + h);
+ }
#ifdef ACCEL_CP
if (info->ChipFamily < CHIP_FAMILY_R200) {
@@ -2438,13 +2471,24 @@ static void FUNC_NAME(RadeonComposite)(PixmapPtr pDst,
RINFO_FROM_SCREEN(pDst->drawable.pScreen);
if (!info->accel_state->need_src_tile_x && !info->accel_state->need_src_tile_y) {
- FUNC_NAME(RadeonCompositeTile)(pScrn,
- info,
- pDst,
- srcX, srcY,
- maskX, maskY,
- dstX, dstY,
- width, height);
+#ifdef ACCEL_CP
+ if (info->accel_state->use_vbos)
+ RadeonCompositeTile_VBO(pScrn,
+ info,
+ pDst,
+ srcX, srcY,
+ maskX, maskY,
+ dstX, dstY,
+ width, height);
+ else
+#endif
+ FUNC_NAME(RadeonCompositeTile)(pScrn,
+ info,
+ pDst,
+ srcX, srcY,
+ maskX, maskY,
+ dstX, dstY,
+ width, height);
return;
}
@@ -2474,13 +2518,24 @@ static void FUNC_NAME(RadeonComposite)(PixmapPtr pDst,
w = remainingWidth;
remainingWidth -= w;
- FUNC_NAME(RadeonCompositeTile)(pScrn,
- info,
- pDst,
- tileSrcX, tileSrcY,
- tileMaskX, tileMaskY,
- tileDstX, tileDstY,
- w, h);
+#ifdef ACCEL_CP
+ if (info->accel_state->use_vbos)
+ RadeonCompositeTile_VBO(pScrn,
+ info,
+ pDst,
+ tileSrcX, tileSrcY,
+ tileMaskX, tileMaskY,
+ tileDstX, tileDstY,
+ w, h);
+ else
+#endif
+ FUNC_NAME(RadeonCompositeTile)(pScrn,
+ info,
+ pDst,
+ tileSrcX, tileSrcY,
+ tileMaskX, tileMaskY,
+ tileDstX, tileDstY,
+ w, h);
tileSrcX = 0;
tileMaskX += w;
@@ -2492,5 +2547,197 @@ static void FUNC_NAME(RadeonComposite)(PixmapPtr pDst,
}
}
+
+#ifdef ACCEL_CP
+
+void radeon_finish_composite_op(ScrnInfoPtr pScrn, int vtx_size)
+{
+ RADEONInfoPtr info = RADEONPTR(pScrn);
+ struct radeon_accel_state *accel_state = info->accel_state;
+ ACCEL_PREAMBLE();
+ int vb_size_dw, vtx_size_dw;
+
+ if (accel_state->vb_start_op == -1)
+ return;
+
+ if (accel_state->vb_offset == accel_state->vb_start_op) {
+ /* vb discard */
+ radeon_ib_discard(pScrn);
+ radeon_vb_discard(pScrn);
+ return;
+ }
+
+ accel_state->vb_size = accel_state->vb_offset - accel_state->vb_start_op;
+
+ vb_size_dw = accel_state->vb_size / 4;
+ vtx_size_dw = vtx_size / 4;
+
+ BEGIN_RING(14);
+
+ OUT_RING(CP_PACKET3(RADEON_CP_PACKET3_3D_LOAD_VBPNTR, 2));
+ OUT_RING(1);
+ OUT_RING(vtx_size_dw | (vtx_size_dw << 8));
+ OUT_RING(info->accel_state->vb_start_op);
+ OUT_RELOC(accel_state->vb_bo, RADEON_GEM_DOMAIN_GTT, 0);
+
+ OUT_RING(CP_PACKET3(R200_CP_PACKET3_3D_DRAW_VBUF_2, 0));
+ OUT_RING(RADEON_CP_VC_CNTL_PRIM_TYPE_QUAD_LIST |
+ RADEON_CP_VC_CNTL_PRIM_WALK_LIST |
+ ((vb_size_dw / vtx_size_dw) << RADEON_CP_VC_CNTL_NUM_SHIFT));
+
+ OUT_RING_REG(R300_SC_CLIP_RULE, 0xAAAA);
+ OUT_RING_REG(R300_RB3D_DSTCACHE_CTLSTAT, R300_RB3D_DC_FLUSH_ALL);
+ OUT_RING_REG(RADEON_WAIT_UNTIL, RADEON_WAIT_3D_IDLECLEAN);
+ ADVANCE_RING();
+
+ accel_state->vb_start_op = -1;
+ accel_state->ib_reset_op = 0;
+}
+
+static void RadeonDoneComposite_VBO(PixmapPtr pDst)
+{
+ ScrnInfoPtr pScrn = xf86Screens[pDst->drawable.pScreen->myNum];
+ RADEONInfoPtr info = RADEONPTR(pScrn);
+ struct radeon_accel_state *accel_state = info->accel_state;
+ int vtx_size;
+
+ if (accel_state->vsync)
+ RADEONWaitForVLineCP(pScrn, pDst,
+ accel_state->vline_crtc,
+ accel_state->vline_y1,
+ accel_state->vline_y2);
+
+ vtx_size = accel_state->msk_pic ? 24 : 16;
+
+ radeon_finish_composite_op(pScrn, vtx_size);
+}
+
+static void RadeonCompositeTile_VBO(ScrnInfoPtr pScrn,
+ RADEONInfoPtr info,
+ PixmapPtr pDst,
+ int srcX, int srcY,
+ int maskX, int maskY,
+ int dstX, int dstY,
+ int w, int h)
+{
+ xPointFixed srcTopLeft, srcTopRight, srcBottomLeft, srcBottomRight;
+ static xPointFixed maskTopLeft, maskTopRight, maskBottomLeft, maskBottomRight;
+ float *vb;
+ ACCEL_PREAMBLE();
+
+ ENTER_DRAW(0);
+
+ /* ErrorF("RadeonComposite (%d,%d) (%d,%d) (%d,%d) (%d,%d)\n",
+ srcX, srcY, maskX, maskY,dstX, dstY, w, h); */
+
+ srcTopLeft.x = IntToxFixed(srcX);
+ srcTopLeft.y = IntToxFixed(srcY);
+ srcTopRight.x = IntToxFixed(srcX + w);
+ srcTopRight.y = IntToxFixed(srcY);
+ srcBottomLeft.x = IntToxFixed(srcX);
+ srcBottomLeft.y = IntToxFixed(srcY + h);
+ srcBottomRight.x = IntToxFixed(srcX + w);
+ srcBottomRight.y = IntToxFixed(srcY + h);
+
+ if (info->accel_state->is_transform[0]) {
+ if ((info->ChipFamily < CHIP_FAMILY_R300) || !info->accel_state->has_tcl) {
+ transformPoint(info->accel_state->transform[0], &srcTopLeft);
+ transformPoint(info->accel_state->transform[0], &srcTopRight);
+ transformPoint(info->accel_state->transform[0], &srcBottomLeft);
+ transformPoint(info->accel_state->transform[0], &srcBottomRight);
+ }
+ }
+
+ if (info->accel_state->msk_pic) {
+ maskTopLeft.x = IntToxFixed(maskX);
+ maskTopLeft.y = IntToxFixed(maskY);
+ maskTopRight.x = IntToxFixed(maskX + w);
+ maskTopRight.y = IntToxFixed(maskY);
+ maskBottomLeft.x = IntToxFixed(maskX);
+ maskBottomLeft.y = IntToxFixed(maskY + h);
+ maskBottomRight.x = IntToxFixed(maskX + w);
+ maskBottomRight.y = IntToxFixed(maskY + h);
+
+ if (info->accel_state->is_transform[1]) {
+ if ((info->ChipFamily < CHIP_FAMILY_R300) || !info->accel_state->has_tcl) {
+ transformPoint(info->accel_state->transform[1], &maskTopLeft);
+ transformPoint(info->accel_state->transform[1], &maskTopRight);
+ transformPoint(info->accel_state->transform[1], &maskBottomLeft);
+ transformPoint(info->accel_state->transform[1], &maskBottomRight);
+ }
+ }
+ }
+
+ if (info->accel_state->vsync) {
+ RADEONVlineHelperSet(pScrn, dstX, dstY, dstX + w, dstY + h);
+ }
+
+ if (info->accel_state->msk_pic) {
+ vb = radeon_vbo_space(pScrn, 24);
+
+ vb[0] = (float)dstX;
+ vb[1] = (float)dstY;
+ vb[2] = xFixedToFloat(srcTopLeft.x) / info->accel_state->texW[0];
+ vb[3] = xFixedToFloat(srcTopLeft.y) / info->accel_state->texH[0];
+ vb[4] = xFixedToFloat(maskTopLeft.x) / info->accel_state->texW[1];
+ vb[5] = xFixedToFloat(maskTopLeft.y) / info->accel_state->texH[1];
+
+ vb[6] = (float)dstX;
+ vb[7] = (float)(dstY + h);
+ vb[8] = xFixedToFloat(srcBottomLeft.x) / info->accel_state->texW[0];
+ vb[9] = xFixedToFloat(srcBottomLeft.y) / info->accel_state->texH[0];
+ vb[10] = xFixedToFloat(maskBottomLeft.x) / info->accel_state->texW[1];
+ vb[11] = xFixedToFloat(maskBottomLeft.y) / info->accel_state->texH[1];
+
+ vb[12] = (float)(dstX + w);
+ vb[13] = (float)(dstY + h);
+ vb[14] = xFixedToFloat(srcBottomRight.x) / info->accel_state->texW[0];
+ vb[15] = xFixedToFloat(srcBottomRight.y) / info->accel_state->texH[0];
+ vb[16] = xFixedToFloat(maskBottomRight.x) / info->accel_state->texW[1];
+ vb[17] = xFixedToFloat(maskBottomRight.y) / info->accel_state->texH[1];
+
+ vb[18] = (float)(dstX + w);
+ vb[19] = (float)dstY;
+ vb[20] = xFixedToFloat(srcTopRight.x) / info->accel_state->texW[0];
+ vb[21] = xFixedToFloat(srcTopRight.y) / info->accel_state->texH[0];
+ vb[22] = xFixedToFloat(maskTopRight.x) / info->accel_state->texW[1];
+ vb[23] = xFixedToFloat(maskTopRight.y) / info->accel_state->texH[1];
+
+ radeon_vbo_commit(pScrn);
+ } else {
+
+ vb = radeon_vbo_space(pScrn, 16);
+
+ vb[0] = (float)dstX;
+ vb[1] = (float)dstY;
+ vb[2] = xFixedToFloat(srcTopLeft.x) / info->accel_state->texW[0];
+ vb[3] = xFixedToFloat(srcTopLeft.y) / info->accel_state->texH[0];
+
+ vb[4] = (float)dstX;
+ vb[5] = (float)(dstY + h);
+ vb[6] = xFixedToFloat(srcBottomLeft.x) / info->accel_state->texW[0];
+ vb[7] = xFixedToFloat(srcBottomLeft.y) / info->accel_state->texH[0];
+
+ vb[8] = (float)(dstX + w);
+ vb[9] = (float)(dstY + h);
+ vb[10] = xFixedToFloat(srcBottomRight.x) / info->accel_state->texW[0];
+ vb[11] = xFixedToFloat(srcBottomRight.y) / info->accel_state->texH[0];
+
+ vb[12] = (float)(dstX + w);
+ vb[13] = (float)dstY;
+ vb[14] = xFixedToFloat(srcTopRight.x) / info->accel_state->texW[0];
+ vb[15] = xFixedToFloat(srcTopRight.y) / info->accel_state->texH[0];
+
+ radeon_vbo_commit(pScrn);
+ }
+
+
+ LEAVE_DRAW(0);
+}
+#undef VTX_OUT
+#undef VTX_OUT_MASK
+#endif
+
+
#undef ONLY_ONCE
#undef FUNC_NAME
diff --git a/src/radeon_reg.h b/src/radeon_reg.h
index 377c26b..77e77f3 100644
--- a/src/radeon_reg.h
+++ b/src/radeon_reg.h
@@ -3197,6 +3197,7 @@
#define RADEON_CP_PACKET3_3D_DRAW_IMMD 0xC0002900
#define RADEON_CP_PACKET3_3D_DRAW_INDX 0xC0002A00
#define RADEON_CP_PACKET3_LOAD_PALETTE 0xC0002C00
+#define R200_CP_PACKET3_3D_DRAW_VBUF_2 0xc0003400
#define R200_CP_PACKET3_3D_DRAW_IMMD_2 0xc0003500
#define RADEON_CP_PACKET3_3D_LOAD_VBPNTR 0xC0002F00
#define RADEON_CP_PACKET3_CNTL_PAINT 0xC0009100
commit c79ce215a01b45fc63b483da167ae37ec7aefad6
Author: Dave Airlie <airlied at redhat.com>
Date: Sun Aug 1 16:51:48 2010 +1000
radeon/r600: restructure exa + vbo to provide more sharing
This is a precursor for r300/500 vbo support.
Signed-off-by: Dave Airlie <airlied at redhat.com>
diff --git a/src/Makefile.am b/src/Makefile.am
index 5750770..f53f958 100644
--- a/src/Makefile.am
+++ b/src/Makefile.am
@@ -53,7 +53,7 @@ RADEON_KMS_SRCS=radeon_dri2.c radeon_kms.c drmmode_display.c radeon_vbo.c
endif
if USE_EXA
-RADEON_EXA_SOURCES = radeon_exa.c r600_exa.c r6xx_accel.c r600_textured_videofuncs.c r600_shader.c
+RADEON_EXA_SOURCES = radeon_exa.c r600_exa.c r6xx_accel.c r600_textured_videofuncs.c r600_shader.c radeon_exa_shared.c
endif
AM_CFLAGS = \
diff --git a/src/r600_exa.c b/src/r600_exa.c
index 72c4ff8..b16c40f 100644
--- a/src/r600_exa.c
+++ b/src/r600_exa.c
@@ -38,44 +38,11 @@
#include "r600_shader.h"
#include "r600_reg.h"
#include "r600_state.h"
+#include "radeon_exa_shared.h"
#include "radeon_vbo.h"
-#define RADEON_TRACE_FALL 0
-#define RADEON_TRACE_DRAW 0
-
-#if RADEON_TRACE_FALL
-#define RADEON_FALLBACK(x) \
-do { \
- ErrorF("%s: ", __FUNCTION__); \
- ErrorF x; \
- return FALSE; \
-} while (0)
-#else
-#define RADEON_FALLBACK(x) return FALSE
-#endif
-
-extern PixmapPtr
-RADEONGetDrawablePixmap(DrawablePtr pDrawable);
-
/* #define SHOW_VERTEXES */
-# define RADEON_ROP3_ZERO 0x00000000
-# define RADEON_ROP3_DSa 0x00880000
-# define RADEON_ROP3_SDna 0x00440000
-# define RADEON_ROP3_S 0x00cc0000
-# define RADEON_ROP3_DSna 0x00220000
-# define RADEON_ROP3_D 0x00aa0000
-# define RADEON_ROP3_DSx 0x00660000
-# define RADEON_ROP3_DSo 0x00ee0000
-# define RADEON_ROP3_DSon 0x00110000
-# define RADEON_ROP3_DSxn 0x00990000
-# define RADEON_ROP3_Dn 0x00550000
-# define RADEON_ROP3_SDno 0x00dd0000
-# define RADEON_ROP3_Sn 0x00330000
-# define RADEON_ROP3_DSno 0x00bb0000
-# define RADEON_ROP3_DSan 0x00770000
-# define RADEON_ROP3_ONE 0x00ff0000
-
uint32_t RADEON_ROP[16] = {
RADEON_ROP3_ZERO, /* GXclear */
RADEON_ROP3_DSa, /* Gxand */
@@ -95,29 +62,6 @@ uint32_t RADEON_ROP[16] = {
RADEON_ROP3_ONE, /* GXset */
};
-static void R600VlineHelperClear(ScrnInfoPtr pScrn)
-{
- RADEONInfoPtr info = RADEONPTR(pScrn);
- struct radeon_accel_state *accel_state = info->accel_state;
-
- accel_state->vline_crtc = NULL;
- accel_state->vline_y1 = -1;
- accel_state->vline_y2 = 0;
-}
-
-static void R600VlineHelperSet(ScrnInfoPtr pScrn, int x1, int y1, int x2, int y2)
-{
- RADEONInfoPtr info = RADEONPTR(pScrn);
- struct radeon_accel_state *accel_state = info->accel_state;
-
- accel_state->vline_crtc = radeon_pick_best_crtc(pScrn, x1, x2, y1, y2);
- if (accel_state->vline_y1 == -1)
- accel_state->vline_y1 = y1;
- if (y1 < accel_state->vline_y1)
- accel_state->vline_y1 = y1;
- if (y2 > accel_state->vline_y2)
- accel_state->vline_y2 = y2;
-}
static Bool R600ValidPM(uint32_t pm, int bpp)
{
@@ -265,22 +209,9 @@ R600SetAccelState(ScrnInfoPtr pScrn,
return TRUE;
}
-#if defined(XF86DRM_MODE)
-static inline void radeon_add_pixmap(struct radeon_cs *cs, PixmapPtr pPix, int read_domains, int write_domain)
-{
- struct radeon_exa_pixmap_priv *driver_priv = exaGetPixmapDriverPrivate(pPix);
-
- radeon_cs_space_add_persistent_bo(cs, driver_priv->bo, read_domains, write_domain);
-}
-#endif
-
static void
R600DoneSolid(PixmapPtr pPix);
-static void
-R600DoneComposite(PixmapPtr pDst);
-
-
static Bool
R600PrepareSolid(PixmapPtr pPix, int alu, Pixel pm, Pixel fg)
{
@@ -329,7 +260,7 @@ R600PrepareSolid(PixmapPtr pPix, int alu, Pixel pm, Pixel fg)
CLEAR (ps_conf);
radeon_vbo_check(pScrn, 16);
- r600_cp_start(pScrn);
+ radeon_cp_start(pScrn);
set_default_state(pScrn, accel_state->ib);
@@ -445,7 +376,7 @@ R600PrepareSolid(PixmapPtr pPix, int alu, Pixel pm, Pixel fg)
sizeof(ps_alu_consts) / SQ_ALU_CONSTANT_offset, ps_alu_consts);
if (accel_state->vsync)
- R600VlineHelperClear(pScrn);
+ RADEONVlineHelperClear(pScrn);
return TRUE;
}
@@ -460,7 +391,7 @@ R600Solid(PixmapPtr pPix, int x1, int y1, int x2, int y2)
float *vb;
if (accel_state->vsync)
- R600VlineHelperSet(pScrn, x1, y1, x2, y2);
+ RADEONVlineHelperSet(pScrn, x1, y1, x2, y2);
vb = radeon_vbo_space(pScrn, 8);
@@ -510,7 +441,7 @@ R600DoPrepareCopy(ScrnInfoPtr pScrn)
CLEAR (ps_conf);
radeon_vbo_check(pScrn, 16);
- r600_cp_start(pScrn);
+ radeon_cp_start(pScrn);
set_default_state(pScrn, accel_state->ib);
@@ -797,7 +728,7 @@ R600PrepareCopy(PixmapPtr pSrc, PixmapPtr pDst,
R600DoPrepareCopy(pScrn);
if (accel_state->vsync)
- R600VlineHelperClear(pScrn);
+ RADEONVlineHelperClear(pScrn);
return TRUE;
}
@@ -816,7 +747,7 @@ R600Copy(PixmapPtr pDst,
return;
if (accel_state->vsync)
- R600VlineHelperSet(pScrn, dstX, dstY, dstX + w, dstY + h);
+ RADEONVlineHelperSet(pScrn, dstX, dstY, dstX + w, dstY + h);
if (accel_state->same_surface && accel_state->copy_area) {
uint32_t orig_offset, tmp_offset;
@@ -1468,7 +1399,7 @@ static Bool R600PrepareComposite(int op, PicturePtr pSrcPicture,
else
radeon_vbo_check(pScrn, 16);
- r600_cp_start(pScrn);
+ radeon_cp_start(pScrn);
set_default_state(pScrn, accel_state->ib);
@@ -1478,14 +1409,14 @@ static Bool R600PrepareComposite(int op, PicturePtr pSrcPicture,
if (!R600TextureSetup(pSrcPicture, pSrc, 0)) {
R600IBDiscard(pScrn, accel_state->ib);
- r600_vb_discard(pScrn);
+ radeon_vb_discard(pScrn);
return FALSE;
}
if (pMask) {
if (!R600TextureSetup(pMaskPicture, pMask, 1)) {
R600IBDiscard(pScrn, accel_state->ib);
- r600_vb_discard(pScrn);
+ radeon_vb_discard(pScrn);
return FALSE;
}
} else
@@ -1615,7 +1546,7 @@ static Bool R600PrepareComposite(int op, PicturePtr pSrcPicture,
END_BATCH();
if (accel_state->vsync)
- R600VlineHelperClear(pScrn);
+ RADEONVlineHelperClear(pScrn);
return TRUE;
}
@@ -1635,7 +1566,7 @@ static void R600Composite(PixmapPtr pDst,
srcX, srcY, maskX, maskY,dstX, dstY, w, h); */
if (accel_state->vsync)
- R600VlineHelperSet(pScrn, dstX, dstY, dstX + w, dstY + h);
+ RADEONVlineHelperSet(pScrn, dstX, dstY, dstX + w, dstY + h);
if (accel_state->msk_pic) {
@@ -1697,10 +1628,10 @@ static void R600DoneComposite(PixmapPtr pDst)
int vtx_size;
if (accel_state->vsync)
- cp_wait_vline_sync(pScrn, accel_state->ib, pDst,
- accel_state->vline_crtc,
- accel_state->vline_y1,
- accel_state->vline_y2);
+ cp_wait_vline_sync(pScrn, accel_state->ib, pDst,
+ accel_state->vline_crtc,
+ accel_state->vline_y1,
+ accel_state->vline_y2);
vtx_size = accel_state->msk_pic ? 24 : 16;
@@ -1797,7 +1728,7 @@ R600CopyToVRAM(ScrnInfoPtr pScrn,
}
R600IBDiscard(pScrn, scratch);
- r600_vb_discard(pScrn);
+ radeon_vb_discard(pScrn);
return TRUE;
}
@@ -1911,7 +1842,7 @@ R600DownloadFromScreen(PixmapPtr pSrc, int x, int y, int w, int h,
}
R600IBDiscard(pScrn, scratch);
- r600_vb_discard(pScrn);
+ radeon_vb_discard(pScrn);
return TRUE;
@@ -1994,7 +1925,7 @@ R600UploadToScreenCS(PixmapPtr pDst, int x, int y, int w, int h,
radeon_bo_unmap(scratch);
if (info->accel_state->vsync)
- R600VlineHelperSet(pScrn, x, y, x + w, y + h);
+ RADEONVlineHelperSet(pScrn, x, y, x + w, y + h);
/* blit from gart to vram */
R600DoPrepareCopy(pScrn);
@@ -2380,7 +2311,9 @@ R600DrawInit(ScreenPtr pScreen)
info->accel_state->dst_obj.bo = NULL;
info->accel_state->copy_area_bo = NULL;
info->accel_state->vb_start_op = -1;
- R600VlineHelperClear(pScrn);
+ info->accel_state->finish_op = r600_finish_op;
+ info->accel_state->verts_per_op = 3;
+ RADEONVlineHelperClear(pScrn);
#ifdef XF86DRM_MODE
radeon_vbo_init_lists(pScrn);
diff --git a/src/r600_state.h b/src/r600_state.h
index 43dc929..710ec6d 100644
--- a/src/r600_state.h
+++ b/src/r600_state.h
@@ -320,12 +320,6 @@ draw_immd(ScrnInfoPtr pScrn, drmBufPtr ib, draw_config_t *draw_conf, uint32_t *i
void
draw_auto(ScrnInfoPtr pScrn, drmBufPtr ib, draw_config_t *draw_conf);
-Bool
-r600_vb_get(ScrnInfoPtr pScrn);
-void
-r600_vb_discard(ScrnInfoPtr pScrn);
-int
-r600_cp_start(ScrnInfoPtr pScrn);
void r600_finish_op(ScrnInfoPtr pScrn, int vtx_size);
Bool
diff --git a/src/r600_textured_videofuncs.c b/src/r600_textured_videofuncs.c
index e75d9fe..9f91f6e 100644
--- a/src/r600_textured_videofuncs.c
+++ b/src/r600_textured_videofuncs.c
@@ -45,6 +45,7 @@
#include "damage.h"
+#include "radeon_exa_shared.h"
#include "radeon_vbo.h"
/* Parameters for ITU-R BT.601 and ITU-R BT.709 colour spaces
@@ -206,7 +207,7 @@ R600DisplayTexturedVideo(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv)
#endif
radeon_vbo_check(pScrn, 16);
- r600_cp_start(pScrn);
+ radeon_cp_start(pScrn);
set_default_state(pScrn, accel_state->ib);
diff --git a/src/r6xx_accel.c b/src/r6xx_accel.c
index 73f9462..8e8c1bf 100644
--- a/src/r6xx_accel.c
+++ b/src/r6xx_accel.c
@@ -39,6 +39,7 @@
#include "radeon_drm.h"
#include "radeon_vbo.h"
+#include "radeon_exa_shared.h"
/* we try and batch operations together under KMS -
but it doesn't work yet without misrendering */
@@ -85,34 +86,9 @@ void R600CPFlushIndirect(ScrnInfoPtr pScrn, drmBufPtr ib)
void R600IBDiscard(ScrnInfoPtr pScrn, drmBufPtr ib)
{
#if defined(XF86DRM_MODE)
- int ret;
RADEONInfoPtr info = RADEONPTR(pScrn);
if (info->cs) {
- if (info->accel_state->ib_reset_op) {
- /* if we have data just reset the CS and ignore the operation */
- info->cs->cdw = info->accel_state->ib_reset_op;
- info->accel_state->ib_reset_op = 0;
- return;
- }
- if (info->accel_state->vb_ptr) {
- info->accel_state->vb_ptr = NULL;
- }
-
- info->accel_state->vb_offset = 0;
- info->accel_state->vb_start_op = -1;
-
- if (CS_FULL(info->cs)) {
- radeon_cs_flush_indirect(pScrn);
- return;
- }
- radeon_cs_erase(info->cs);
- ret = radeon_cs_space_check(info->cs);
- if (ret)
- ErrorF("space check failed in flush\n");
- if (info->dri2.enabled) {
- info->accel_state->XInited3D = FALSE;
- info->accel_state->engineMode = EXA_ENGINEMODE_UNKNOWN;
- }
+ radeon_ib_discard(pScrn);
}
#endif
if (!ib) return;
@@ -1138,57 +1114,6 @@ draw_auto(ScrnInfoPtr pScrn, drmBufPtr ib, draw_config_t *draw_conf)
END_BATCH();
}
-Bool
-r600_vb_get(ScrnInfoPtr pScrn)
-{
- RADEONInfoPtr info = RADEONPTR(pScrn);
- struct radeon_accel_state *accel_state = info->accel_state;
-
- accel_state->vb_mc_addr = info->gartLocation + info->dri->bufStart +
- (accel_state->ib->idx*accel_state->ib->total)+
- (accel_state->ib->total / 2);
- accel_state->vb_total = (accel_state->ib->total / 2);
- accel_state->vb_ptr = (pointer)((char*)accel_state->ib->address +
- (accel_state->ib->total / 2));
- accel_state->vb_offset = 0;
- return TRUE;
-}
-
-void
-r600_vb_discard(ScrnInfoPtr pScrn)
-{
- RADEONInfoPtr info = RADEONPTR(pScrn);
-
- info->accel_state->vb_start_op = -1;
-}
-
-
-
-int
-r600_cp_start(ScrnInfoPtr pScrn)
-{
- RADEONInfoPtr info = RADEONPTR(pScrn);
- struct radeon_accel_state *accel_state = info->accel_state;
-
-#if defined(XF86DRM_MODE)
- if (info->cs) {
- if (CS_FULL(info->cs)) {
- radeon_cs_flush_indirect(pScrn);
- }
- accel_state->ib_reset_op = info->cs->cdw;
- accel_state->vb_start_op = accel_state->vb_offset;
- } else
-#endif
- {
- accel_state->ib = RADEONCPGetBuffer(pScrn);
- if (!r600_vb_get(pScrn)) {
- return -1;
- }
- accel_state->vb_start_op = accel_state->vb_offset;
- }
- return 0;
-}
-
void r600_finish_op(ScrnInfoPtr pScrn, int vtx_size)
{
RADEONInfoPtr info = RADEONPTR(pScrn);
@@ -1204,7 +1129,7 @@ void r600_finish_op(ScrnInfoPtr pScrn, int vtx_size)
if (accel_state->vb_offset == accel_state->vb_start_op) {
R600IBDiscard(pScrn, accel_state->ib);
- r600_vb_discard(pScrn);
+ radeon_vb_discard(pScrn);
return;
}
@@ -1260,31 +1185,3 @@ void r600_finish_op(ScrnInfoPtr pScrn, int vtx_size)
R600CPFlushIndirect(pScrn, accel_state->ib);
}
-void r600_vb_no_space(ScrnInfoPtr pScrn, int vert_size)
-{
- RADEONInfoPtr info = RADEONPTR(pScrn);
- struct radeon_accel_state *accel_state = info->accel_state;
-#ifdef XF86DRM_MODE
-
- if (info->cs) {
- if (accel_state->vb_bo) {
- if (accel_state->vb_start_op != accel_state->vb_offset) {
- r600_finish_op(pScrn, vert_size);
- accel_state->ib_reset_op = info->cs->cdw;
- }
-
- /* release the current VBO */
- radeon_vbo_put(pScrn);
- }
-
- /* get a new one */
- radeon_vbo_get(pScrn);
- return;
- }
-#endif
-
- if (accel_state->vb_start_op != -1) {
- r600_finish_op(pScrn, vert_size);
- r600_cp_start(pScrn);
- }
-}
diff --git a/src/radeon.h b/src/radeon.h
index 61f07ba..55d673a 100644
--- a/src/radeon.h
+++ b/src/radeon.h
@@ -721,7 +721,7 @@ struct radeon_accel_state {
uint32_t *draw_header;
unsigned vtx_count;
unsigned num_vtx;
-
+ unsigned verts_per_op;
Bool vsync;
drmBufPtr ib;
@@ -741,7 +741,7 @@ struct radeon_accel_state {
struct radeon_dma_bo bo_reserved;
Bool use_vbos;
#endif
-
+ void (*finish_op)(ScrnInfoPtr, int);
// shader storage
ExaOffscreenArea *shaders;
struct radeon_bo *shaders_bo;
diff --git a/src/radeon_exa.c b/src/radeon_exa.c
index d7fba65..7dd792e 100644
--- a/src/radeon_exa.c
+++ b/src/radeon_exa.c
@@ -42,6 +42,7 @@
#include "radeon_macros.h"
#include "radeon_probe.h"
#include "radeon_version.h"
+#include "radeon_exa_shared.h"
#include "xf86.h"
@@ -50,26 +51,6 @@
#define RINFO_FROM_SCREEN(pScr) ScrnInfoPtr pScrn = xf86Screens[pScr->myNum]; \
RADEONInfoPtr info = RADEONPTR(pScrn)
-#define RADEON_TRACE_FALL 0
-#define RADEON_TRACE_DRAW 0
-
-#if RADEON_TRACE_FALL
-#define RADEON_FALLBACK(x) \
-do { \
- ErrorF("%s: ", __FUNCTION__); \
- ErrorF x; \
- return FALSE; \
-} while (0)
-#else
-#define RADEON_FALLBACK(x) return FALSE
-#endif
-
-#if RADEON_TRACE_DRAW
-#define TRACE do { ErrorF("TRACE: %s\n", __FUNCTION__); } while(0)
-#else
-#define TRACE
-#endif
-
static struct {
int rop;
int pattern;
@@ -121,18 +102,6 @@ static __inline__ uint32_t F_TO_DW(float val)
}
-#ifdef XF86DRM_MODE
-
-static inline void radeon_add_pixmap(struct radeon_cs *cs, PixmapPtr pPix, int read_domains, int write_domain)
-{
- struct radeon_exa_pixmap_priv *driver_priv = exaGetPixmapDriverPrivate(pPix);
-
- radeon_cs_space_add_persistent_bo(cs, driver_priv->bo, read_domains, write_domain);
-}
-
-#endif /* XF86DRM_MODE */
-
-
/* Assumes that depth 15 and 16 can be used as depth 16, which is okay since we
* require src and dest datatypes to be equal.
*/
diff --git a/src/radeon_exa_render.c b/src/radeon_exa_render.c
index cf773b0..da72416 100644
--- a/src/radeon_exa_render.c
+++ b/src/radeon_exa_render.c
@@ -496,14 +496,6 @@ static Bool FUNC_NAME(R100TextureSetup)(PicturePtr pPict, PixmapPtr pPix,
#ifdef ONLY_ONCE
-PixmapPtr
-RADEONGetDrawablePixmap(DrawablePtr pDrawable)
-{
- if (pDrawable->type == DRAWABLE_WINDOW)
- return pDrawable->pScreen->GetWindowPixmap((WindowPtr)pDrawable);
- else
- return (PixmapPtr)pDrawable;
-}
static Bool R100CheckComposite(int op, PicturePtr pSrcPicture,
PicturePtr pMaskPicture, PicturePtr pDstPicture)
diff --git a/src/radeon_exa_shared.c b/src/radeon_exa_shared.c
new file mode 100644
index 0000000..7489a3d
--- /dev/null
+++ b/src/radeon_exa_shared.c
@@ -0,0 +1,186 @@
+/*
+ * Copyright 2005 Eric Anholt
+ * Copyright 2005 Benjamin Herrenschmidt
+ * Copyright 2008 Advanced Micro Devices, Inc.
+ * All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+ * SOFTWARE.
+ *
+ * Authors:
+ * Eric Anholt <anholt at FreeBSD.org>
+ * Zack Rusin <zrusin at trolltech.com>
+ * Benjamin Herrenschmidt <benh at kernel.crashing.org>
+ * Alex Deucher <alexander.deucher at amd.com>
+ * Matthias Hopf <mhopf at suse.de>
+ */
+#ifdef HAVE_CONFIG_H
+#include "config.h"
+#endif
+
+#include "radeon.h"
+#include "radeon_reg.h"
+#include "r600_reg.h"
+#ifdef XF86DRI
+#include "radeon_drm.h"
+#endif
+#include "radeon_macros.h"
+#include "radeon_probe.h"
+#include "radeon_version.h"
+#include "radeon_vbo.h"
+
+PixmapPtr
+RADEONGetDrawablePixmap(DrawablePtr pDrawable)
+{
+ if (pDrawable->type == DRAWABLE_WINDOW)
+ return pDrawable->pScreen->GetWindowPixmap((WindowPtr)pDrawable);
+ else
+ return (PixmapPtr)pDrawable;
+}
+
+void RADEONVlineHelperClear(ScrnInfoPtr pScrn)
+{
+ RADEONInfoPtr info = RADEONPTR(pScrn);
+ struct radeon_accel_state *accel_state = info->accel_state;
+
+ accel_state->vline_crtc = NULL;
+ accel_state->vline_y1 = -1;
+ accel_state->vline_y2 = 0;
+}
+
+void RADEONVlineHelperSet(ScrnInfoPtr pScrn, int x1, int y1, int x2, int y2)
+{
+ RADEONInfoPtr info = RADEONPTR(pScrn);
+ struct radeon_accel_state *accel_state = info->accel_state;
+
+ accel_state->vline_crtc = radeon_pick_best_crtc(pScrn, x1, x2, y1, y2);
+ if (accel_state->vline_y1 == -1)
+ accel_state->vline_y1 = y1;
+ if (y1 < accel_state->vline_y1)
+ accel_state->vline_y1 = y1;
+ if (y2 > accel_state->vline_y2)
+ accel_state->vline_y2 = y2;
+}
+
+static Bool radeon_vb_get(ScrnInfoPtr pScrn)
+{
+ RADEONInfoPtr info = RADEONPTR(pScrn);
+ struct radeon_accel_state *accel_state = info->accel_state;
+
+ accel_state->vb_mc_addr = info->gartLocation + info->dri->bufStart +
+ (accel_state->ib->idx*accel_state->ib->total)+
+ (accel_state->ib->total / 2);
+ accel_state->vb_total = (accel_state->ib->total / 2);
+ accel_state->vb_ptr = (pointer)((char*)accel_state->ib->address +
+ (accel_state->ib->total / 2));
+ accel_state->vb_offset = 0;
+ return TRUE;
+}
+
+void radeon_vb_discard(ScrnInfoPtr pScrn)
+{
+ RADEONInfoPtr info = RADEONPTR(pScrn);
+
+ info->accel_state->vb_start_op = -1;
+}
+
+int radeon_cp_start(ScrnInfoPtr pScrn)
+{
+ RADEONInfoPtr info = RADEONPTR(pScrn);
+ struct radeon_accel_state *accel_state = info->accel_state;
+
+#if defined(XF86DRM_MODE)
+ if (info->cs) {
+ if (CS_FULL(info->cs)) {
+ radeon_cs_flush_indirect(pScrn);
+ }
+ accel_state->ib_reset_op = info->cs->cdw;
+ accel_state->vb_start_op = accel_state->vb_offset;
+ } else
+#endif
+ {
+ accel_state->ib = RADEONCPGetBuffer(pScrn);
+ if (!radeon_vb_get(pScrn)) {
+ return -1;
+ }
+ accel_state->vb_start_op = accel_state->vb_offset;
+ }
+ return 0;
+}
+
+void radeon_vb_no_space(ScrnInfoPtr pScrn, int vert_size)
+{
+ RADEONInfoPtr info = RADEONPTR(pScrn);
+ struct radeon_accel_state *accel_state = info->accel_state;
+
+ if (info->cs) {
+ if (accel_state->vb_bo) {
+ if (accel_state->vb_start_op != accel_state->vb_offset) {
+ accel_state->finish_op(pScrn, vert_size);
+ accel_state->ib_reset_op = info->cs->cdw;
+ }
+
+ /* release the current VBO */
+ radeon_vbo_put(pScrn);
+ }
+ /* get a new one */
+ radeon_vbo_get(pScrn);
+ return;
+ }
+
+ if (accel_state->vb_start_op != -1) {
+ accel_state->finish_op(pScrn, vert_size);
+ radeon_cp_start(pScrn);
+ }
+ return;
+}
+
+void radeon_ib_discard(ScrnInfoPtr pScrn)
+{
+ RADEONInfoPtr info = RADEONPTR(pScrn);
+ int ret;
+
+ if (info->accel_state->ib_reset_op) {
+ /* if we have data just reset the CS and ignore the operation */
+ info->cs->cdw = info->accel_state->ib_reset_op;
+ info->accel_state->ib_reset_op = 0;
+ goto out;
+ }
+
+ info->accel_state->vb_offset = 0;
+ info->accel_state->vb_start_op = -1;
+
+ if (CS_FULL(info->cs)) {
+ radeon_cs_flush_indirect(pScrn);
+ return;
+ }
+ radeon_cs_erase(info->cs);
+ ret = radeon_cs_space_check_with_bo(info->cs,
+ info->accel_state->vb_bo,
+ RADEON_GEM_DOMAIN_GTT, 0);
+ if (ret)
+ ErrorF("space check failed in flush\n");
+
+ out:
+ if (info->dri2.enabled) {
+ info->accel_state->XInited3D = FALSE;
+ info->accel_state->engineMode = EXA_ENGINEMODE_UNKNOWN;
+ }
+
+}
diff --git a/src/radeon_exa_shared.h b/src/radeon_exa_shared.h
new file mode 100644
index 0000000..286886d
--- /dev/null
+++ b/src/radeon_exa_shared.h
@@ -0,0 +1,79 @@
+/*
+ * Copyright 2005 Eric Anholt
+ * Copyright 2005 Benjamin Herrenschmidt
+ * Copyright 2008 Advanced Micro Devices, Inc.
+ * All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+ * SOFTWARE.
+ *
+ * Authors:
+ * Eric Anholt <anholt at FreeBSD.org>
+ * Zack Rusin <zrusin at trolltech.com>
+ * Benjamin Herrenschmidt <benh at kernel.crashing.org>
+ * Alex Deucher <alexander.deucher at amd.com>
+ * Matthias Hopf <mhopf at suse.de>
+ */
+#ifndef RADEON_EXA_SHARED_H
+
+#define RADEON_EXA_SHARED_H
+
+extern PixmapPtr RADEONGetDrawablePixmap(DrawablePtr pDrawable);
+
+extern void RADEONVlineHelperClear(ScrnInfoPtr pScrn);
+extern void RADEONVlineHelperSet(ScrnInfoPtr pScrn, int x1, int y1, int x2, int y2);
+
+
+#define RADEON_TRACE_FALL 0
+#define RADEON_TRACE_DRAW 0
+
+#if RADEON_TRACE_FALL
+#define RADEON_FALLBACK(x) \
+do { \
+ ErrorF("%s: ", __FUNCTION__); \
+ ErrorF x; \
+ return FALSE; \
+} while (0)
+#else
+#define RADEON_FALLBACK(x) return FALSE
+#endif
+
+#if RADEON_TRACE_DRAW
+#define TRACE do { ErrorF("TRACE: %s\n", __FUNCTION__); } while(0)
+#else
+#define TRACE
+#endif
+
+#ifdef XF86DRM_MODE
+static inline void radeon_add_pixmap(struct radeon_cs *cs, PixmapPtr pPix, int read_domains, int write_domain)
+{
+ struct radeon_exa_pixmap_priv *driver_priv = exaGetPixmapDriverPrivate(pPix);
+
+ radeon_cs_space_add_persistent_bo(cs, driver_priv->bo, read_domains, write_domain);
+}
+
+#endif /* XF86DRM_MODE */
+
+extern void radeon_vb_discard(ScrnInfoPtr pScrn);
+extern int radeon_cp_start(ScrnInfoPtr pScrn);
+extern void radeon_vb_no_space(ScrnInfoPtr pScrn, int vert_size);
+extern void radeon_vbo_done_composite(PixmapPtr pDst);
+
+extern void radeon_ib_discard(ScrnInfoPtr pScrn);
+#endif
diff --git a/src/radeon_kms.c b/src/radeon_kms.c
index c0d2ae6..772be8f 100644
--- a/src/radeon_kms.c
+++ b/src/radeon_kms.c
@@ -82,9 +82,6 @@ void radeon_cs_flush_indirect(ScrnInfoPtr pScrn)
if (!info->cs->cdw)
return;
- if (info->accel_state->vb_ptr)
- info->accel_state->vb_ptr = NULL;
-
/* release the current VBO so we don't block on mapping it later */
if (info->accel_state->vb_offset && info->accel_state->vb_bo) {
radeon_vbo_put(pScrn);
diff --git a/src/radeon_vbo.h b/src/radeon_vbo.h
index a8c70b3..b505f66 100644
--- a/src/radeon_vbo.h
+++ b/src/radeon_vbo.h
@@ -2,7 +2,7 @@
#ifndef RADEON_VBO_H
#define RADEON_VBO_H
-extern void r600_vb_no_space(ScrnInfoPtr pScrn, int vert_size);
+extern void radeon_vb_no_space(ScrnInfoPtr pScrn, int vert_size);
extern void radeon_vbo_init_lists(ScrnInfoPtr pScrn);
extern void radeon_vbo_free_lists(ScrnInfoPtr pScrn);
extern void radeon_vbo_flush_bos(ScrnInfoPtr pScrn);
@@ -14,8 +14,8 @@ static inline void radeon_vbo_check(ScrnInfoPtr pScrn, int vert_size)
RADEONInfoPtr info = RADEONPTR(pScrn);
struct radeon_accel_state *accel_state = info->accel_state;
- if ((accel_state->vb_offset + (3 * vert_size)) > accel_state->vb_total) {
- r600_vb_no_space(pScrn, vert_size);
+ if ((accel_state->vb_offset + (accel_state->verts_per_op * vert_size)) > accel_state->vb_total) {
+ radeon_vb_no_space(pScrn, vert_size);
}
}
@@ -28,9 +28,8 @@ radeon_vbo_space(ScrnInfoPtr pScrn, int vert_size)
/* we've ran out of space in the vertex buffer - need to get a
new one */
- if ((accel_state->vb_offset + (3 * vert_size)) > accel_state->vb_total) {
- r600_vb_no_space(pScrn, vert_size);
- }
+ radeon_vbo_check(pScrn, vert_size);
+
accel_state->vb_op_vert_size = vert_size;
#if defined(XF86DRM_MODE)
if (info->cs) {
@@ -56,7 +55,7 @@ static inline void radeon_vbo_commit(ScrnInfoPtr pScrn)
RADEONInfoPtr info = RADEONPTR(pScrn);
struct radeon_accel_state *accel_state = info->accel_state;
- accel_state->vb_offset += 3 * accel_state->vb_op_vert_size;
+ accel_state->vb_offset += accel_state->verts_per_op * accel_state->vb_op_vert_size;
}
#endif
commit 82254b59268140c4102ae3cd713743ae2be15c00
Author: Alex Deucher <alexdeucher at gmail.com>
Date: Fri Jul 30 17:15:05 2010 -0400
r6xx/r7xx: unify composite mask and non-mask pixel shader
diff --git a/src/r600_exa.c b/src/r600_exa.c
index 89d5877..72c4ff8 100644
--- a/src/r600_exa.c
+++ b/src/r600_exa.c
@@ -1427,7 +1427,7 @@ static Bool R600PrepareComposite(int op, PicturePtr pSrcPicture,
&src_obj,
&mask_obj,
&dst_obj,
- accel_state->comp_vs_offset, accel_state->comp_mask_ps_offset,
+ accel_state->comp_vs_offset, accel_state->comp_ps_offset,
3, 0xffffffff))
return FALSE;
@@ -1491,10 +1491,13 @@ static Bool R600PrepareComposite(int op, PicturePtr pSrcPicture,
} else
accel_state->is_transform[1] = FALSE;
- if (pMask)
+ if (pMask) {
set_bool_consts(pScrn, accel_state->ib, SQ_BOOL_CONST_vs, (1 << 0));
- else
+ set_bool_consts(pScrn, accel_state->ib, SQ_BOOL_CONST_ps, (1 << 0));
+ } else {
set_bool_consts(pScrn, accel_state->ib, SQ_BOOL_CONST_vs, (0 << 0));
+ set_bool_consts(pScrn, accel_state->ib, SQ_BOOL_CONST_ps, (0 << 0));
+ }
/* Shader */
@@ -1516,7 +1519,7 @@ static Bool R600PrepareComposite(int op, PicturePtr pSrcPicture,
ps_conf.shader_addr = accel_state->ps_mc_addr;
ps_conf.num_gprs = 3;
- ps_conf.stack_size = 0;
+ ps_conf.stack_size = 1;
ps_conf.uncached_first_inst = 1;
ps_conf.clamp_consts = 0;
ps_conf.export_mode = 2;
@@ -2224,16 +2227,12 @@ R600LoadShaders(ScrnInfoPtr pScrn)
accel_state->comp_ps_offset = 2560;
R600_comp_ps(ChipSet, shader + accel_state->comp_ps_offset / 4);
- /* comp mask ps --------------------------------------- */
- accel_state->comp_mask_ps_offset = 3072;
- R600_comp_mask_ps(ChipSet, shader + accel_state->comp_mask_ps_offset / 4);
-
/* xv vs --------------------------------------- */
- accel_state->xv_vs_offset = 3584;
+ accel_state->xv_vs_offset = 3072;
R600_xv_vs(ChipSet, shader + accel_state->xv_vs_offset / 4);
/* xv ps --------------------------------------- */
- accel_state->xv_ps_offset = 4096;
+ accel_state->xv_ps_offset = 3584;
R600_xv_ps(ChipSet, shader + accel_state->xv_ps_offset / 4);
#ifdef XF86DRM_MODE
diff --git a/src/r600_shader.c b/src/r600_shader.c
index 47bc007..e2a4163 100644
--- a/src/r600_shader.c
+++ b/src/r600_shader.c
@@ -1149,230 +1149,6 @@ int R600_xv_ps(RADEONChipFamily ChipSet, uint32_t* shader)
return i;
}
-/* comp mask ps --------------------------------------- */
-int R600_comp_mask_ps(RADEONChipFamily ChipSet, uint32_t* shader)
-{
- int i = 0;
-
- /* 0 */
- shader[i++] = CF_DWORD0(ADDR(8));
- shader[i++] = CF_DWORD1(POP_COUNT(0),
- CF_CONST(0),
- COND(SQ_CF_COND_ACTIVE),
- I_COUNT(2),
- CALL_COUNT(0),
- END_OF_PROGRAM(0),
- VALID_PIXEL_MODE(0),
- CF_INST(SQ_CF_INST_TEX),
- WHOLE_QUAD_MODE(0),
- BARRIER(1));
-
- /* 1 */
- shader[i++] = CF_ALU_DWORD0(ADDR(3),
- KCACHE_BANK0(0),
- KCACHE_BANK1(0),
- KCACHE_MODE0(SQ_CF_KCACHE_NOP));
- shader[i++] = CF_ALU_DWORD1(KCACHE_MODE1(SQ_CF_KCACHE_NOP),
- KCACHE_ADDR0(0),
- KCACHE_ADDR1(0),
- I_COUNT(4),
- USES_WATERFALL(0),
- CF_INST(SQ_CF_INST_ALU),
- WHOLE_QUAD_MODE(0),
- BARRIER(1));
-
- /* 2 */
- shader[i++] = CF_ALLOC_IMP_EXP_DWORD0(ARRAY_BASE(CF_PIXEL_MRT0),
- TYPE(SQ_EXPORT_PIXEL),
- RW_GPR(2),
- RW_REL(ABSOLUTE),
- INDEX_GPR(0),
- ELEM_SIZE(1));
-
- shader[i++] = CF_ALLOC_IMP_EXP_DWORD1_SWIZ(SRC_SEL_X(SQ_SEL_X),
- SRC_SEL_Y(SQ_SEL_Y),
- SRC_SEL_Z(SQ_SEL_Z),
- SRC_SEL_W(SQ_SEL_W),
- R6xx_ELEM_LOOP(0),
- BURST_COUNT(1),
- END_OF_PROGRAM(1),
- VALID_PIXEL_MODE(0),
- CF_INST(SQ_CF_INST_EXPORT_DONE),
- WHOLE_QUAD_MODE(0),
- BARRIER(1));
-
- /* 3 - alu 0 */
- /* MUL gpr[2].x gpr[1].x gpr[0].x */
- shader[i++] = ALU_DWORD0(SRC0_SEL(1),
- SRC0_REL(ABSOLUTE),
- SRC0_ELEM(ELEM_X),
- SRC0_NEG(0),
- SRC1_SEL(0),
- SRC1_REL(ABSOLUTE),
- SRC1_ELEM(ELEM_X),
- SRC1_NEG(0),
- INDEX_MODE(SQ_INDEX_LOOP),
- PRED_SEL(SQ_PRED_SEL_OFF),
- LAST(0));
- shader[i++] = ALU_DWORD1_OP2(ChipSet,
- SRC0_ABS(0),
- SRC1_ABS(0),
- UPDATE_EXECUTE_MASK(0),
- UPDATE_PRED(0),
- WRITE_MASK(1),
- FOG_MERGE(0),
- OMOD(SQ_ALU_OMOD_OFF),
- ALU_INST(SQ_OP2_INST_MUL),
- BANK_SWIZZLE(SQ_ALU_VEC_012),
- DST_GPR(2),
- DST_REL(ABSOLUTE),
- DST_ELEM(ELEM_X),
- CLAMP(1));
- /* 4 - alu 1 */
- /* MUL gpr[2].y gpr[1].y gpr[0].y */
- shader[i++] = ALU_DWORD0(SRC0_SEL(1),
- SRC0_REL(ABSOLUTE),
- SRC0_ELEM(ELEM_Y),
- SRC0_NEG(0),
- SRC1_SEL(0),
- SRC1_REL(ABSOLUTE),
- SRC1_ELEM(ELEM_Y),
- SRC1_NEG(0),
- INDEX_MODE(SQ_INDEX_LOOP),
- PRED_SEL(SQ_PRED_SEL_OFF),
- LAST(0));
- shader[i++] = ALU_DWORD1_OP2(ChipSet,
- SRC0_ABS(0),
- SRC1_ABS(0),
- UPDATE_EXECUTE_MASK(0),
- UPDATE_PRED(0),
- WRITE_MASK(1),
- FOG_MERGE(0),
- OMOD(SQ_ALU_OMOD_OFF),
- ALU_INST(SQ_OP2_INST_MUL),
- BANK_SWIZZLE(SQ_ALU_VEC_012),
- DST_GPR(2),
- DST_REL(ABSOLUTE),
- DST_ELEM(ELEM_Y),
- CLAMP(1));
- /* 5 - alu 2 */
- /* MUL gpr[2].z gpr[1].z gpr[0].z */
- shader[i++] = ALU_DWORD0(SRC0_SEL(1),
- SRC0_REL(ABSOLUTE),
- SRC0_ELEM(ELEM_Z),
- SRC0_NEG(0),
- SRC1_SEL(0),
- SRC1_REL(ABSOLUTE),
- SRC1_ELEM(ELEM_Z),
- SRC1_NEG(0),
- INDEX_MODE(SQ_INDEX_LOOP),
- PRED_SEL(SQ_PRED_SEL_OFF),
- LAST(0));
- shader[i++] = ALU_DWORD1_OP2(ChipSet,
- SRC0_ABS(0),
- SRC1_ABS(0),
- UPDATE_EXECUTE_MASK(0),
- UPDATE_PRED(0),
- WRITE_MASK(1),
- FOG_MERGE(0),
- OMOD(SQ_ALU_OMOD_OFF),
- ALU_INST(SQ_OP2_INST_MUL),
- BANK_SWIZZLE(SQ_ALU_VEC_012),
- DST_GPR(2),
- DST_REL(ABSOLUTE),
- DST_ELEM(ELEM_Z),
- CLAMP(1));
- /* 6 - alu 3 */
- /* MUL gpr[2].w gpr[1].w gpr[0].w */
- shader[i++] = ALU_DWORD0(SRC0_SEL(1),
- SRC0_REL(ABSOLUTE),
- SRC0_ELEM(ELEM_W),
- SRC0_NEG(0),
- SRC1_SEL(0),
- SRC1_REL(ABSOLUTE),
- SRC1_ELEM(ELEM_W),
- SRC1_NEG(0),
- INDEX_MODE(SQ_INDEX_LOOP),
- PRED_SEL(SQ_PRED_SEL_OFF),
- LAST(1));
- shader[i++] = ALU_DWORD1_OP2(ChipSet,
- SRC0_ABS(0),
- SRC1_ABS(0),
- UPDATE_EXECUTE_MASK(0),
- UPDATE_PRED(0),
- WRITE_MASK(1),
- FOG_MERGE(0),
- OMOD(SQ_ALU_OMOD_OFF),
- ALU_INST(SQ_OP2_INST_MUL),
- BANK_SWIZZLE(SQ_ALU_VEC_012),
- DST_GPR(2),
- DST_REL(ABSOLUTE),
- DST_ELEM(ELEM_W),
- CLAMP(1));
- /* 7 */
- shader[i++] = 0x00000000;
- shader[i++] = 0x00000000;
-
- /* 8/9 - src */
- shader[i++] = TEX_DWORD0(TEX_INST(SQ_TEX_INST_SAMPLE),
- BC_FRAC_MODE(0),
- FETCH_WHOLE_QUAD(0),
- RESOURCE_ID(0),
- SRC_GPR(0),
- SRC_REL(ABSOLUTE),
- R7xx_ALT_CONST(0));
- shader[i++] = TEX_DWORD1(DST_GPR(0),
- DST_REL(ABSOLUTE),
- DST_SEL_X(SQ_SEL_X),
- DST_SEL_Y(SQ_SEL_Y),
- DST_SEL_Z(SQ_SEL_Z),
- DST_SEL_W(SQ_SEL_W),
- LOD_BIAS(0),
- COORD_TYPE_X(TEX_NORMALIZED),
- COORD_TYPE_Y(TEX_NORMALIZED),
- COORD_TYPE_Z(TEX_NORMALIZED),
- COORD_TYPE_W(TEX_NORMALIZED));
- shader[i++] = TEX_DWORD2(OFFSET_X(0),
- OFFSET_Y(0),
- OFFSET_Z(0),
- SAMPLER_ID(0),
- SRC_SEL_X(SQ_SEL_X),
- SRC_SEL_Y(SQ_SEL_Y),
- SRC_SEL_Z(SQ_SEL_0),
- SRC_SEL_W(SQ_SEL_1));
- shader[i++] = TEX_DWORD_PAD;
- /* 10/11 - mask */
- shader[i++] = TEX_DWORD0(TEX_INST(SQ_TEX_INST_SAMPLE),
- BC_FRAC_MODE(0),
- FETCH_WHOLE_QUAD(0),
- RESOURCE_ID(1),
- SRC_GPR(1),
- SRC_REL(ABSOLUTE),
- R7xx_ALT_CONST(0));
- shader[i++] = TEX_DWORD1(DST_GPR(1),
- DST_REL(ABSOLUTE),
- DST_SEL_X(SQ_SEL_X),
- DST_SEL_Y(SQ_SEL_Y),
- DST_SEL_Z(SQ_SEL_Z),
- DST_SEL_W(SQ_SEL_W),
- LOD_BIAS(0),
- COORD_TYPE_X(TEX_NORMALIZED),
- COORD_TYPE_Y(TEX_NORMALIZED),
- COORD_TYPE_Z(TEX_NORMALIZED),
- COORD_TYPE_W(TEX_NORMALIZED));
- shader[i++] = TEX_DWORD2(OFFSET_X(0),
- OFFSET_Y(0),
- OFFSET_Z(0),
- SAMPLER_ID(1),
- SRC_SEL_X(SQ_SEL_X),
- SRC_SEL_Y(SQ_SEL_Y),
- SRC_SEL_Z(SQ_SEL_0),
- SRC_SEL_W(SQ_SEL_1));
- shader[i++] = TEX_DWORD_PAD;
-
- return i;
-}
-
/* comp vs --------------------------------------- */
int R600_comp_vs(RADEONChipFamily ChipSet, uint32_t* shader)
{
@@ -2152,7 +1928,102 @@ int R600_comp_ps(RADEONChipFamily ChipSet, uint32_t* shader)
int i = 0;
/* 0 */
- shader[i++] = CF_DWORD0(ADDR(2));
+ shader[i++] = CF_DWORD0(ADDR(3));
+ shader[i++] = CF_DWORD1(POP_COUNT(0),
+ CF_CONST(0),
+ COND(SQ_CF_COND_BOOL),
+ I_COUNT(0),
+ CALL_COUNT(0),
+ END_OF_PROGRAM(0),
+ VALID_PIXEL_MODE(0),
+ CF_INST(SQ_CF_INST_CALL),
+ WHOLE_QUAD_MODE(0),
+ BARRIER(0));
+ /* 1 */
+ shader[i++] = CF_DWORD0(ADDR(7));
+ shader[i++] = CF_DWORD1(POP_COUNT(0),
+ CF_CONST(0),
+ COND(SQ_CF_COND_NOT_BOOL),
+ I_COUNT(0),
+ CALL_COUNT(0),
+ END_OF_PROGRAM(0),
+ VALID_PIXEL_MODE(0),
+ CF_INST(SQ_CF_INST_CALL),
+ WHOLE_QUAD_MODE(0),
+ BARRIER(0));
+ /* 2 */
+ shader[i++] = CF_DWORD0(ADDR(0));
+ shader[i++] = CF_DWORD1(POP_COUNT(0),
+ CF_CONST(0),
+ COND(SQ_CF_COND_ACTIVE),
+ I_COUNT(0),
+ CALL_COUNT(0),
+ END_OF_PROGRAM(1),
+ VALID_PIXEL_MODE(0),
+ CF_INST(SQ_CF_INST_NOP),
+ WHOLE_QUAD_MODE(0),
+ BARRIER(1));
+
+ /* 3 - mask sub */
+ shader[i++] = CF_DWORD0(ADDR(14));
+ shader[i++] = CF_DWORD1(POP_COUNT(0),
+ CF_CONST(0),
+ COND(SQ_CF_COND_ACTIVE),
+ I_COUNT(2),
+ CALL_COUNT(0),
+ END_OF_PROGRAM(0),
+ VALID_PIXEL_MODE(0),
+ CF_INST(SQ_CF_INST_TEX),
+ WHOLE_QUAD_MODE(0),
+ BARRIER(1));
+
+ /* 4 */
+ shader[i++] = CF_ALU_DWORD0(ADDR(10),
+ KCACHE_BANK0(0),
+ KCACHE_BANK1(0),
+ KCACHE_MODE0(SQ_CF_KCACHE_NOP));
+ shader[i++] = CF_ALU_DWORD1(KCACHE_MODE1(SQ_CF_KCACHE_NOP),
+ KCACHE_ADDR0(0),
+ KCACHE_ADDR1(0),
+ I_COUNT(4),
+ USES_WATERFALL(0),
+ CF_INST(SQ_CF_INST_ALU),
+ WHOLE_QUAD_MODE(0),
+ BARRIER(1));
+
+ /* 5 */
+ shader[i++] = CF_ALLOC_IMP_EXP_DWORD0(ARRAY_BASE(CF_PIXEL_MRT0),
+ TYPE(SQ_EXPORT_PIXEL),
+ RW_GPR(2),
+ RW_REL(ABSOLUTE),
+ INDEX_GPR(0),
+ ELEM_SIZE(1));
+ shader[i++] = CF_ALLOC_IMP_EXP_DWORD1_SWIZ(SRC_SEL_X(SQ_SEL_X),
+ SRC_SEL_Y(SQ_SEL_Y),
+ SRC_SEL_Z(SQ_SEL_Z),
+ SRC_SEL_W(SQ_SEL_W),
+ R6xx_ELEM_LOOP(0),
+ BURST_COUNT(1),
+ END_OF_PROGRAM(0),
+ VALID_PIXEL_MODE(0),
+ CF_INST(SQ_CF_INST_EXPORT_DONE),
+ WHOLE_QUAD_MODE(0),
+ BARRIER(1));
+ /* 6 */
+ shader[i++] = CF_DWORD0(ADDR(0));
+ shader[i++] = CF_DWORD1(POP_COUNT(0),
+ CF_CONST(0),
+ COND(SQ_CF_COND_ACTIVE),
+ I_COUNT(0),
+ CALL_COUNT(0),
+ END_OF_PROGRAM(0),
+ VALID_PIXEL_MODE(0),
+ CF_INST(SQ_CF_INST_RETURN),
+ WHOLE_QUAD_MODE(0),
+ BARRIER(1));
+
+ /* 7 non-mask sub */
+ shader[i++] = CF_DWORD0(ADDR(18));
shader[i++] = CF_DWORD1(POP_COUNT(0),
CF_CONST(0),
COND(SQ_CF_COND_ACTIVE),
@@ -2163,28 +2034,204 @@ int R600_comp_ps(RADEONChipFamily ChipSet, uint32_t* shader)
CF_INST(SQ_CF_INST_TEX),
WHOLE_QUAD_MODE(0),
BARRIER(1));
- /* 1 */
+ /* 8 */
shader[i++] = CF_ALLOC_IMP_EXP_DWORD0(ARRAY_BASE(CF_PIXEL_MRT0),
TYPE(SQ_EXPORT_PIXEL),
RW_GPR(0),
RW_REL(ABSOLUTE),
INDEX_GPR(0),
ELEM_SIZE(1));
-
shader[i++] = CF_ALLOC_IMP_EXP_DWORD1_SWIZ(SRC_SEL_X(SQ_SEL_X),
SRC_SEL_Y(SQ_SEL_Y),
SRC_SEL_Z(SQ_SEL_Z),
SRC_SEL_W(SQ_SEL_W),
R6xx_ELEM_LOOP(0),
BURST_COUNT(1),
- END_OF_PROGRAM(1),
+ END_OF_PROGRAM(0),
VALID_PIXEL_MODE(0),
CF_INST(SQ_CF_INST_EXPORT_DONE),
WHOLE_QUAD_MODE(0),
BARRIER(1));
+ /* 9 */
+ shader[i++] = CF_DWORD0(ADDR(0));
+ shader[i++] = CF_DWORD1(POP_COUNT(0),
+ CF_CONST(0),
+ COND(SQ_CF_COND_ACTIVE),
+ I_COUNT(0),
+ CALL_COUNT(0),
+ END_OF_PROGRAM(0),
+ VALID_PIXEL_MODE(0),
+ CF_INST(SQ_CF_INST_RETURN),
+ WHOLE_QUAD_MODE(0),
+ BARRIER(1));
+
+ /* 10 - alu 0 */
+ /* MUL gpr[2].x gpr[1].x gpr[0].x */
+ shader[i++] = ALU_DWORD0(SRC0_SEL(1),
+ SRC0_REL(ABSOLUTE),
+ SRC0_ELEM(ELEM_X),
+ SRC0_NEG(0),
+ SRC1_SEL(0),
+ SRC1_REL(ABSOLUTE),
+ SRC1_ELEM(ELEM_X),
+ SRC1_NEG(0),
+ INDEX_MODE(SQ_INDEX_LOOP),
+ PRED_SEL(SQ_PRED_SEL_OFF),
+ LAST(0));
+ shader[i++] = ALU_DWORD1_OP2(ChipSet,
+ SRC0_ABS(0),
+ SRC1_ABS(0),
+ UPDATE_EXECUTE_MASK(0),
+ UPDATE_PRED(0),
+ WRITE_MASK(1),
+ FOG_MERGE(0),
+ OMOD(SQ_ALU_OMOD_OFF),
+ ALU_INST(SQ_OP2_INST_MUL),
+ BANK_SWIZZLE(SQ_ALU_VEC_012),
+ DST_GPR(2),
+ DST_REL(ABSOLUTE),
+ DST_ELEM(ELEM_X),
+ CLAMP(1));
+ /* 11 - alu 1 */
+ /* MUL gpr[2].y gpr[1].y gpr[0].y */
+ shader[i++] = ALU_DWORD0(SRC0_SEL(1),
+ SRC0_REL(ABSOLUTE),
+ SRC0_ELEM(ELEM_Y),
+ SRC0_NEG(0),
+ SRC1_SEL(0),
+ SRC1_REL(ABSOLUTE),
+ SRC1_ELEM(ELEM_Y),
+ SRC1_NEG(0),
+ INDEX_MODE(SQ_INDEX_LOOP),
+ PRED_SEL(SQ_PRED_SEL_OFF),
+ LAST(0));
+ shader[i++] = ALU_DWORD1_OP2(ChipSet,
+ SRC0_ABS(0),
+ SRC1_ABS(0),
+ UPDATE_EXECUTE_MASK(0),
+ UPDATE_PRED(0),
+ WRITE_MASK(1),
+ FOG_MERGE(0),
+ OMOD(SQ_ALU_OMOD_OFF),
+ ALU_INST(SQ_OP2_INST_MUL),
+ BANK_SWIZZLE(SQ_ALU_VEC_012),
+ DST_GPR(2),
+ DST_REL(ABSOLUTE),
+ DST_ELEM(ELEM_Y),
+ CLAMP(1));
+ /* 12 - alu 2 */
+ /* MUL gpr[2].z gpr[1].z gpr[0].z */
+ shader[i++] = ALU_DWORD0(SRC0_SEL(1),
+ SRC0_REL(ABSOLUTE),
+ SRC0_ELEM(ELEM_Z),
+ SRC0_NEG(0),
+ SRC1_SEL(0),
+ SRC1_REL(ABSOLUTE),
+ SRC1_ELEM(ELEM_Z),
+ SRC1_NEG(0),
+ INDEX_MODE(SQ_INDEX_LOOP),
+ PRED_SEL(SQ_PRED_SEL_OFF),
+ LAST(0));
+ shader[i++] = ALU_DWORD1_OP2(ChipSet,
+ SRC0_ABS(0),
+ SRC1_ABS(0),
+ UPDATE_EXECUTE_MASK(0),
+ UPDATE_PRED(0),
+ WRITE_MASK(1),
+ FOG_MERGE(0),
+ OMOD(SQ_ALU_OMOD_OFF),
+ ALU_INST(SQ_OP2_INST_MUL),
+ BANK_SWIZZLE(SQ_ALU_VEC_012),
+ DST_GPR(2),
+ DST_REL(ABSOLUTE),
+ DST_ELEM(ELEM_Z),
+ CLAMP(1));
+ /* 13 - alu 3 */
+ /* MUL gpr[2].w gpr[1].w gpr[0].w */
+ shader[i++] = ALU_DWORD0(SRC0_SEL(1),
+ SRC0_REL(ABSOLUTE),
+ SRC0_ELEM(ELEM_W),
+ SRC0_NEG(0),
+ SRC1_SEL(0),
+ SRC1_REL(ABSOLUTE),
+ SRC1_ELEM(ELEM_W),
+ SRC1_NEG(0),
+ INDEX_MODE(SQ_INDEX_LOOP),
+ PRED_SEL(SQ_PRED_SEL_OFF),
+ LAST(1));
+ shader[i++] = ALU_DWORD1_OP2(ChipSet,
+ SRC0_ABS(0),
+ SRC1_ABS(0),
+ UPDATE_EXECUTE_MASK(0),
+ UPDATE_PRED(0),
+ WRITE_MASK(1),
+ FOG_MERGE(0),
+ OMOD(SQ_ALU_OMOD_OFF),
+ ALU_INST(SQ_OP2_INST_MUL),
+ BANK_SWIZZLE(SQ_ALU_VEC_012),
+ DST_GPR(2),
+ DST_REL(ABSOLUTE),
+ DST_ELEM(ELEM_W),
+ CLAMP(1));
+ /* 14/15 - src - mask */
+ shader[i++] = TEX_DWORD0(TEX_INST(SQ_TEX_INST_SAMPLE),
+ BC_FRAC_MODE(0),
+ FETCH_WHOLE_QUAD(0),
+ RESOURCE_ID(0),
+ SRC_GPR(0),
+ SRC_REL(ABSOLUTE),
+ R7xx_ALT_CONST(0));
+ shader[i++] = TEX_DWORD1(DST_GPR(0),
+ DST_REL(ABSOLUTE),
+ DST_SEL_X(SQ_SEL_X),
+ DST_SEL_Y(SQ_SEL_Y),
+ DST_SEL_Z(SQ_SEL_Z),
+ DST_SEL_W(SQ_SEL_W),
+ LOD_BIAS(0),
+ COORD_TYPE_X(TEX_NORMALIZED),
+ COORD_TYPE_Y(TEX_NORMALIZED),
+ COORD_TYPE_Z(TEX_NORMALIZED),
+ COORD_TYPE_W(TEX_NORMALIZED));
+ shader[i++] = TEX_DWORD2(OFFSET_X(0),
+ OFFSET_Y(0),
+ OFFSET_Z(0),
+ SAMPLER_ID(0),
+ SRC_SEL_X(SQ_SEL_X),
+ SRC_SEL_Y(SQ_SEL_Y),
+ SRC_SEL_Z(SQ_SEL_0),
+ SRC_SEL_W(SQ_SEL_1));
+ shader[i++] = TEX_DWORD_PAD;
+ /* 16/17 - mask */
+ shader[i++] = TEX_DWORD0(TEX_INST(SQ_TEX_INST_SAMPLE),
+ BC_FRAC_MODE(0),
+ FETCH_WHOLE_QUAD(0),
+ RESOURCE_ID(1),
+ SRC_GPR(1),
+ SRC_REL(ABSOLUTE),
+ R7xx_ALT_CONST(0));
+ shader[i++] = TEX_DWORD1(DST_GPR(1),
+ DST_REL(ABSOLUTE),
+ DST_SEL_X(SQ_SEL_X),
+ DST_SEL_Y(SQ_SEL_Y),
+ DST_SEL_Z(SQ_SEL_Z),
+ DST_SEL_W(SQ_SEL_W),
+ LOD_BIAS(0),
+ COORD_TYPE_X(TEX_NORMALIZED),
+ COORD_TYPE_Y(TEX_NORMALIZED),
+ COORD_TYPE_Z(TEX_NORMALIZED),
+ COORD_TYPE_W(TEX_NORMALIZED));
+ shader[i++] = TEX_DWORD2(OFFSET_X(0),
+ OFFSET_Y(0),
+ OFFSET_Z(0),
+ SAMPLER_ID(1),
+ SRC_SEL_X(SQ_SEL_X),
+ SRC_SEL_Y(SQ_SEL_Y),
+ SRC_SEL_Z(SQ_SEL_0),
+ SRC_SEL_W(SQ_SEL_1));
+ shader[i++] = TEX_DWORD_PAD;
- /* 2/3 - src */
+ /* 18/19 - src - non-mask */
shader[i++] = TEX_DWORD0(TEX_INST(SQ_TEX_INST_SAMPLE),
BC_FRAC_MODE(0),
FETCH_WHOLE_QUAD(0),
diff --git a/src/r600_shader.h b/src/r600_shader.h
index 6c12614..a68d6c2 100644
--- a/src/r600_shader.h
+++ b/src/r600_shader.h
@@ -353,7 +353,6 @@ extern int R600_xv_vs(RADEONChipFamily ChipSet, uint32_t* shader);
extern int R600_xv_ps(RADEONChipFamily ChipSet, uint32_t* shader);
extern int R600_comp_vs(RADEONChipFamily ChipSet, uint32_t* vs);
-extern int R600_comp_mask_ps(RADEONChipFamily ChipSet, uint32_t* ps);
extern int R600_comp_ps(RADEONChipFamily ChipSet, uint32_t* ps);
#endif
diff --git a/src/radeon.h b/src/radeon.h
index 56bc076..61f07ba 100644
--- a/src/radeon.h
+++ b/src/radeon.h
@@ -751,7 +751,6 @@ struct radeon_accel_state {
uint32_t copy_ps_offset;
uint32_t comp_vs_offset;
uint32_t comp_ps_offset;
- uint32_t comp_mask_ps_offset;
uint32_t xv_vs_offset;
uint32_t xv_ps_offset;
commit 1c17f3a192f644e8e38b5cfb1470f49434bfba27
Author: Alex Deucher <alexdeucher at gmail.com>
Date: Fri Jul 30 16:34:54 2010 -0400
r6xx/r7xx: clean up composite vertex shader
keep CF, ALU, Fetch instructions in separate groups
diff --git a/src/r600_shader.c b/src/r600_shader.c
index 7e25f6d..47bc007 100644
--- a/src/r600_shader.c
+++ b/src/r600_shader.c
@@ -1391,7 +1391,7 @@ int R600_comp_vs(RADEONChipFamily ChipSet, uint32_t* shader)
WHOLE_QUAD_MODE(0),
BARRIER(0));
/* 1 */
- shader[i++] = CF_DWORD0(ADDR(28));
+ shader[i++] = CF_DWORD0(ADDR(9));
shader[i++] = CF_DWORD1(POP_COUNT(0),
CF_CONST(0),
COND(SQ_CF_COND_NOT_BOOL),
@@ -1415,7 +1415,7 @@ int R600_comp_vs(RADEONChipFamily ChipSet, uint32_t* shader)
WHOLE_QUAD_MODE(0),
BARRIER(1));
/* 3 - mask sub */
- shader[i++] = CF_DWORD0(ADDR(22));
+ shader[i++] = CF_DWORD0(ADDR(32));
shader[i++] = CF_DWORD1(POP_COUNT(0),
CF_CONST(0),
COND(SQ_CF_COND_ACTIVE),
@@ -1428,7 +1428,7 @@ int R600_comp_vs(RADEONChipFamily ChipSet, uint32_t* shader)
BARRIER(1));
/* 4 - ALU */
- shader[i++] = CF_ALU_DWORD0(ADDR(9),
+ shader[i++] = CF_ALU_DWORD0(ADDR(14),
KCACHE_BANK0(0),
KCACHE_BANK1(0),
KCACHE_MODE0(SQ_CF_KCACHE_NOP));
@@ -1507,9 +1507,84 @@ int R600_comp_vs(RADEONChipFamily ChipSet, uint32_t* shader)
CF_INST(SQ_CF_INST_RETURN),
WHOLE_QUAD_MODE(0),
BARRIER(1));
+ /* 9 - non-mask sub */
+ shader[i++] = CF_DWORD0(ADDR(38));
+ shader[i++] = CF_DWORD1(POP_COUNT(0),
+ CF_CONST(0),
+ COND(SQ_CF_COND_ACTIVE),
+ I_COUNT(2),
+ CALL_COUNT(0),
+ END_OF_PROGRAM(0),
+ VALID_PIXEL_MODE(0),
+ CF_INST(SQ_CF_INST_VTX),
+ WHOLE_QUAD_MODE(0),
+ BARRIER(1));
+
+ /* 10 - ALU */
+ shader[i++] = CF_ALU_DWORD0(ADDR(26),
+ KCACHE_BANK0(0),
+ KCACHE_BANK1(0),
+ KCACHE_MODE0(SQ_CF_KCACHE_NOP));
+ shader[i++] = CF_ALU_DWORD1(KCACHE_MODE1(SQ_CF_KCACHE_NOP),
+ KCACHE_ADDR0(0),
+ KCACHE_ADDR1(0),
+ I_COUNT(6),
+ USES_WATERFALL(0),
+ CF_INST(SQ_CF_INST_ALU),
+ WHOLE_QUAD_MODE(0),
+ BARRIER(1));
+
+ /* 11 - dst */
+ shader[i++] = CF_ALLOC_IMP_EXP_DWORD0(ARRAY_BASE(CF_POS0),
+ TYPE(SQ_EXPORT_POS),
+ RW_GPR(1),
+ RW_REL(ABSOLUTE),
+ INDEX_GPR(0),
+ ELEM_SIZE(0));
+ shader[i++] = CF_ALLOC_IMP_EXP_DWORD1_SWIZ(SRC_SEL_X(SQ_SEL_X),
+ SRC_SEL_Y(SQ_SEL_Y),
+ SRC_SEL_Z(SQ_SEL_0),
+ SRC_SEL_W(SQ_SEL_1),
+ R6xx_ELEM_LOOP(0),
+ BURST_COUNT(0),
+ END_OF_PROGRAM(0),
+ VALID_PIXEL_MODE(0),
+ CF_INST(SQ_CF_INST_EXPORT_DONE),
+ WHOLE_QUAD_MODE(0),
+ BARRIER(1));
+ /* 12 - src */
+ shader[i++] = CF_ALLOC_IMP_EXP_DWORD0(ARRAY_BASE(0),
+ TYPE(SQ_EXPORT_PARAM),
+ RW_GPR(0),
+ RW_REL(ABSOLUTE),
+ INDEX_GPR(0),
+ ELEM_SIZE(0));
+ shader[i++] = CF_ALLOC_IMP_EXP_DWORD1_SWIZ(SRC_SEL_X(SQ_SEL_X),
+ SRC_SEL_Y(SQ_SEL_Y),
+ SRC_SEL_Z(SQ_SEL_0),
+ SRC_SEL_W(SQ_SEL_1),
+ R6xx_ELEM_LOOP(0),
+ BURST_COUNT(0),
+ END_OF_PROGRAM(0),
+ VALID_PIXEL_MODE(0),
+ CF_INST(SQ_CF_INST_EXPORT_DONE),
+ WHOLE_QUAD_MODE(0),
+ BARRIER(0));
+ /* 13 */
+ shader[i++] = CF_DWORD0(ADDR(0));
+ shader[i++] = CF_DWORD1(POP_COUNT(0),
+ CF_CONST(0),
+ COND(SQ_CF_COND_ACTIVE),
+ I_COUNT(0),
+ CALL_COUNT(0),
+ END_OF_PROGRAM(0),
+ VALID_PIXEL_MODE(0),
+ CF_INST(SQ_CF_INST_RETURN),
+ WHOLE_QUAD_MODE(0),
+ BARRIER(1));
- /* 9 srcX MAD */
+ /* 14 srcX MAD - mask */
shader[i++] = ALU_DWORD0(SRC0_SEL(256),
SRC0_REL(ABSOLUTE),
SRC0_ELEM(ELEM_Y),
@@ -1531,7 +1606,7 @@ int R600_comp_vs(RADEONChipFamily ChipSet, uint32_t* shader)
DST_REL(ABSOLUTE),
DST_ELEM(ELEM_Z),
CLAMP(0));
- /* 10 srcY MAD */
+ /* 15 srcY MAD */
shader[i++] = ALU_DWORD0(SRC0_SEL(257),
SRC0_REL(ABSOLUTE),
SRC0_ELEM(ELEM_Y),
@@ -1554,7 +1629,7 @@ int R600_comp_vs(RADEONChipFamily ChipSet, uint32_t* shader)
DST_ELEM(ELEM_W),
CLAMP(0));
- /* 11 srcX MAD */
+ /* 16 srcX MAD */
shader[i++] = ALU_DWORD0(SRC0_SEL(256),
SRC0_REL(ABSOLUTE),
SRC0_ELEM(ELEM_X),
@@ -1576,7 +1651,7 @@ int R600_comp_vs(RADEONChipFamily ChipSet, uint32_t* shader)
DST_REL(ABSOLUTE),
DST_ELEM(ELEM_X),
CLAMP(0));
- /* 12 srcY MAD */
+ /* 17 srcY MAD */
shader[i++] = ALU_DWORD0(SRC0_SEL(257),
SRC0_REL(ABSOLUTE),
SRC0_ELEM(ELEM_X),
@@ -1599,7 +1674,7 @@ int R600_comp_vs(RADEONChipFamily ChipSet, uint32_t* shader)
DST_ELEM(ELEM_Y),
CLAMP(0));
- /* 13 maskX MAD */
+ /* 18 maskX MAD */
shader[i++] = ALU_DWORD0(SRC0_SEL(258),
SRC0_REL(ABSOLUTE),
SRC0_ELEM(ELEM_Y),
@@ -1622,7 +1697,7 @@ int R600_comp_vs(RADEONChipFamily ChipSet, uint32_t* shader)
DST_ELEM(ELEM_Z),
CLAMP(0));
- /* 14 maskY MAD */
+ /* 19 maskY MAD */
shader[i++] = ALU_DWORD0(SRC0_SEL(259),
SRC0_REL(ABSOLUTE),
SRC0_ELEM(ELEM_Y),
@@ -1645,7 +1720,7 @@ int R600_comp_vs(RADEONChipFamily ChipSet, uint32_t* shader)
DST_ELEM(ELEM_W),
CLAMP(0));
- /* 15 srcX MAD */
+ /* 20 srcX MAD */
shader[i++] = ALU_DWORD0(SRC0_SEL(258),
SRC0_REL(ABSOLUTE),
SRC0_ELEM(ELEM_X),
@@ -1667,7 +1742,7 @@ int R600_comp_vs(RADEONChipFamily ChipSet, uint32_t* shader)
DST_REL(ABSOLUTE),
DST_ELEM(ELEM_X),
CLAMP(0));
- /* 16 srcY MAD */
+ /* 21 srcY MAD */
shader[i++] = ALU_DWORD0(SRC0_SEL(259),
SRC0_REL(ABSOLUTE),
SRC0_ELEM(ELEM_X),
@@ -1690,7 +1765,7 @@ int R600_comp_vs(RADEONChipFamily ChipSet, uint32_t* shader)
DST_ELEM(ELEM_Y),
CLAMP(0));
- /* 17 srcX / w */
+ /* 22 srcX / w */
shader[i++] = ALU_DWORD0(SRC0_SEL(1),
SRC0_REL(ABSOLUTE),
SRC0_ELEM(ELEM_X),
@@ -1717,7 +1792,7 @@ int R600_comp_vs(RADEONChipFamily ChipSet, uint32_t* shader)
DST_ELEM(ELEM_X),
CLAMP(0));
- /* 18 srcY / h */
+ /* 23 srcY / h */
shader[i++] = ALU_DWORD0(SRC0_SEL(1),
SRC0_REL(ABSOLUTE),
SRC0_ELEM(ELEM_Y),
@@ -1744,7 +1819,7 @@ int R600_comp_vs(RADEONChipFamily ChipSet, uint32_t* shader)
DST_ELEM(ELEM_Y),
CLAMP(0));
- /* 19 maskX / w */
+ /* 24 maskX / w */
shader[i++] = ALU_DWORD0(SRC0_SEL(0),
SRC0_REL(ABSOLUTE),
SRC0_ELEM(ELEM_X),
@@ -1771,7 +1846,7 @@ int R600_comp_vs(RADEONChipFamily ChipSet, uint32_t* shader)
DST_ELEM(ELEM_X),
CLAMP(0));
- /* 20 maskY / h */
+ /* 25 maskY / h */
shader[i++] = ALU_DWORD0(SRC0_SEL(0),
SRC0_REL(ABSOLUTE),
SRC0_ELEM(ELEM_Y),
@@ -1797,164 +1872,8 @@ int R600_comp_vs(RADEONChipFamily ChipSet, uint32_t* shader)
DST_REL(ABSOLUTE),
DST_ELEM(ELEM_Y),
CLAMP(0));
- /* 21 */
- shader[i++] = 0x00000000;
- shader[i++] = 0x00000000;
-
- /* 22/23 - dst */
- shader[i++] = VTX_DWORD0(VTX_INST(SQ_VTX_INST_FETCH),
- FETCH_TYPE(SQ_VTX_FETCH_VERTEX_DATA),
- FETCH_WHOLE_QUAD(0),
- BUFFER_ID(0),
- SRC_GPR(0),
- SRC_REL(ABSOLUTE),
- SRC_SEL_X(SQ_SEL_X),
- MEGA_FETCH_COUNT(24));
- shader[i++] = VTX_DWORD1_GPR(DST_GPR(2),
- DST_REL(0),
- DST_SEL_X(SQ_SEL_X),
- DST_SEL_Y(SQ_SEL_Y),
- DST_SEL_Z(SQ_SEL_0),
- DST_SEL_W(SQ_SEL_1),
- USE_CONST_FIELDS(0),
- DATA_FORMAT(FMT_32_32_FLOAT),
- NUM_FORMAT_ALL(SQ_NUM_FORMAT_SCALED),
- FORMAT_COMP_ALL(SQ_FORMAT_COMP_SIGNED),
- SRF_MODE_ALL(SRF_MODE_ZERO_CLAMP_MINUS_ONE));
- shader[i++] = VTX_DWORD2(OFFSET(0),
- ENDIAN_SWAP(ENDIAN_NONE),
- CONST_BUF_NO_STRIDE(0),
- MEGA_FETCH(1));
- shader[i++] = VTX_DWORD_PAD;
- /* 24/25 - src */
- shader[i++] = VTX_DWORD0(VTX_INST(SQ_VTX_INST_FETCH),
- FETCH_TYPE(SQ_VTX_FETCH_VERTEX_DATA),
- FETCH_WHOLE_QUAD(0),
- BUFFER_ID(0),
- SRC_GPR(0),
- SRC_REL(ABSOLUTE),
- SRC_SEL_X(SQ_SEL_X),
- MEGA_FETCH_COUNT(8));
- shader[i++] = VTX_DWORD1_GPR(DST_GPR(1),
- DST_REL(0),
- DST_SEL_X(SQ_SEL_X),
- DST_SEL_Y(SQ_SEL_Y),
- DST_SEL_Z(SQ_SEL_1),
- DST_SEL_W(SQ_SEL_0),
- USE_CONST_FIELDS(0),
- DATA_FORMAT(FMT_32_32_FLOAT),
- NUM_FORMAT_ALL(SQ_NUM_FORMAT_SCALED),
- FORMAT_COMP_ALL(SQ_FORMAT_COMP_SIGNED),
- SRF_MODE_ALL(SRF_MODE_ZERO_CLAMP_MINUS_ONE));
- shader[i++] = VTX_DWORD2(OFFSET(8),
- ENDIAN_SWAP(ENDIAN_NONE),
- CONST_BUF_NO_STRIDE(0),
- MEGA_FETCH(0));
- shader[i++] = VTX_DWORD_PAD;
- /* 26/27 - mask */
- shader[i++] = VTX_DWORD0(VTX_INST(SQ_VTX_INST_FETCH),
- FETCH_TYPE(SQ_VTX_FETCH_VERTEX_DATA),
- FETCH_WHOLE_QUAD(0),
- BUFFER_ID(0),
- SRC_GPR(0),
- SRC_REL(ABSOLUTE),
- SRC_SEL_X(SQ_SEL_X),
- MEGA_FETCH_COUNT(8));
- shader[i++] = VTX_DWORD1_GPR(DST_GPR(0),
- DST_REL(0),
- DST_SEL_X(SQ_SEL_X),
- DST_SEL_Y(SQ_SEL_Y),
- DST_SEL_Z(SQ_SEL_1),
- DST_SEL_W(SQ_SEL_0),
- USE_CONST_FIELDS(0),
- DATA_FORMAT(FMT_32_32_FLOAT),
- NUM_FORMAT_ALL(SQ_NUM_FORMAT_SCALED),
- FORMAT_COMP_ALL(SQ_FORMAT_COMP_SIGNED),
- SRF_MODE_ALL(SRF_MODE_ZERO_CLAMP_MINUS_ONE));
- shader[i++] = VTX_DWORD2(OFFSET(16),
- ENDIAN_SWAP(ENDIAN_NONE),
- CONST_BUF_NO_STRIDE(0),
- MEGA_FETCH(0));
- shader[i++] = VTX_DWORD_PAD;
- /* 28 - non-mask sub */
- shader[i++] = CF_DWORD0(ADDR(40));
- shader[i++] = CF_DWORD1(POP_COUNT(0),
- CF_CONST(0),
- COND(SQ_CF_COND_ACTIVE),
- I_COUNT(2),
- CALL_COUNT(0),
- END_OF_PROGRAM(0),
- VALID_PIXEL_MODE(0),
- CF_INST(SQ_CF_INST_VTX),
- WHOLE_QUAD_MODE(0),
- BARRIER(1));
-
- /* 29 - ALU */
- shader[i++] = CF_ALU_DWORD0(ADDR(33),
- KCACHE_BANK0(0),
- KCACHE_BANK1(0),
- KCACHE_MODE0(SQ_CF_KCACHE_NOP));
- shader[i++] = CF_ALU_DWORD1(KCACHE_MODE1(SQ_CF_KCACHE_NOP),
- KCACHE_ADDR0(0),
- KCACHE_ADDR1(0),
- I_COUNT(6),
- USES_WATERFALL(0),
- CF_INST(SQ_CF_INST_ALU),
- WHOLE_QUAD_MODE(0),
- BARRIER(1));
-
- /* 30 - dst */
- shader[i++] = CF_ALLOC_IMP_EXP_DWORD0(ARRAY_BASE(CF_POS0),
- TYPE(SQ_EXPORT_POS),
- RW_GPR(1),
- RW_REL(ABSOLUTE),
- INDEX_GPR(0),
- ELEM_SIZE(0));
- shader[i++] = CF_ALLOC_IMP_EXP_DWORD1_SWIZ(SRC_SEL_X(SQ_SEL_X),
- SRC_SEL_Y(SQ_SEL_Y),
- SRC_SEL_Z(SQ_SEL_0),
- SRC_SEL_W(SQ_SEL_1),
- R6xx_ELEM_LOOP(0),
- BURST_COUNT(0),
- END_OF_PROGRAM(0),
- VALID_PIXEL_MODE(0),
- CF_INST(SQ_CF_INST_EXPORT_DONE),
- WHOLE_QUAD_MODE(0),
- BARRIER(1));
- /* 31 - src */
- shader[i++] = CF_ALLOC_IMP_EXP_DWORD0(ARRAY_BASE(0),
- TYPE(SQ_EXPORT_PARAM),
- RW_GPR(0),
- RW_REL(ABSOLUTE),
- INDEX_GPR(0),
- ELEM_SIZE(0));
- shader[i++] = CF_ALLOC_IMP_EXP_DWORD1_SWIZ(SRC_SEL_X(SQ_SEL_X),
- SRC_SEL_Y(SQ_SEL_Y),
- SRC_SEL_Z(SQ_SEL_0),
- SRC_SEL_W(SQ_SEL_1),
- R6xx_ELEM_LOOP(0),
- BURST_COUNT(0),
- END_OF_PROGRAM(0),
- VALID_PIXEL_MODE(0),
- CF_INST(SQ_CF_INST_EXPORT_DONE),
- WHOLE_QUAD_MODE(0),
- BARRIER(0));
- /* 32 */
- shader[i++] = CF_DWORD0(ADDR(0));
- shader[i++] = CF_DWORD1(POP_COUNT(0),
- CF_CONST(0),
- COND(SQ_CF_COND_ACTIVE),
- I_COUNT(0),
- CALL_COUNT(0),
- END_OF_PROGRAM(0),
- VALID_PIXEL_MODE(0),
- CF_INST(SQ_CF_INST_RETURN),
- WHOLE_QUAD_MODE(0),
- BARRIER(1));
-
-
- /* 33 srcX MAD */
+ /* 26 srcX MAD - non-mask */
shader[i++] = ALU_DWORD0(SRC0_SEL(256),
SRC0_REL(ABSOLUTE),
SRC0_ELEM(ELEM_Y),
@@ -1976,7 +1895,7 @@ int R600_comp_vs(RADEONChipFamily ChipSet, uint32_t* shader)
DST_REL(ABSOLUTE),
DST_ELEM(ELEM_Z),
CLAMP(0));
- /* 34 srcY MAD */
+ /* 27 srcY MAD */
shader[i++] = ALU_DWORD0(SRC0_SEL(257),
SRC0_REL(ABSOLUTE),
SRC0_ELEM(ELEM_Y),
@@ -1999,7 +1918,7 @@ int R600_comp_vs(RADEONChipFamily ChipSet, uint32_t* shader)
DST_ELEM(ELEM_W),
CLAMP(0));
- /* 35 srcX MAD */
+ /* 28 srcX MAD */
shader[i++] = ALU_DWORD0(SRC0_SEL(256),
SRC0_REL(ABSOLUTE),
SRC0_ELEM(ELEM_X),
@@ -2021,7 +1940,7 @@ int R600_comp_vs(RADEONChipFamily ChipSet, uint32_t* shader)
DST_REL(ABSOLUTE),
DST_ELEM(ELEM_X),
CLAMP(0));
- /* 36 srcY MAD */
+ /* 29 srcY MAD */
shader[i++] = ALU_DWORD0(SRC0_SEL(257),
SRC0_REL(ABSOLUTE),
SRC0_ELEM(ELEM_X),
@@ -2043,7 +1962,7 @@ int R600_comp_vs(RADEONChipFamily ChipSet, uint32_t* shader)
DST_REL(ABSOLUTE),
DST_ELEM(ELEM_Y),
CLAMP(0));
- /* 37 srcX / w */
+ /* 30 srcX / w */
shader[i++] = ALU_DWORD0(SRC0_SEL(0),
SRC0_REL(ABSOLUTE),
SRC0_ELEM(ELEM_X),
@@ -2070,7 +1989,7 @@ int R600_comp_vs(RADEONChipFamily ChipSet, uint32_t* shader)
DST_ELEM(ELEM_X),
CLAMP(0));
- /* 38 srcY / h */
+ /* 31 srcY / h */
shader[i++] = ALU_DWORD0(SRC0_SEL(0),
SRC0_REL(ABSOLUTE),
SRC0_ELEM(ELEM_Y),
@@ -2097,11 +2016,83 @@ int R600_comp_vs(RADEONChipFamily ChipSet, uint32_t* shader)
DST_ELEM(ELEM_Y),
CLAMP(0));
- /* 39 */
- shader[i++] = 0x00000000;
- shader[i++] = 0x00000000;
+ /* 32/33 - dst - mask */
+ shader[i++] = VTX_DWORD0(VTX_INST(SQ_VTX_INST_FETCH),
+ FETCH_TYPE(SQ_VTX_FETCH_VERTEX_DATA),
+ FETCH_WHOLE_QUAD(0),
+ BUFFER_ID(0),
+ SRC_GPR(0),
+ SRC_REL(ABSOLUTE),
+ SRC_SEL_X(SQ_SEL_X),
+ MEGA_FETCH_COUNT(24));
+ shader[i++] = VTX_DWORD1_GPR(DST_GPR(2),
+ DST_REL(0),
+ DST_SEL_X(SQ_SEL_X),
+ DST_SEL_Y(SQ_SEL_Y),
+ DST_SEL_Z(SQ_SEL_0),
+ DST_SEL_W(SQ_SEL_1),
+ USE_CONST_FIELDS(0),
+ DATA_FORMAT(FMT_32_32_FLOAT),
+ NUM_FORMAT_ALL(SQ_NUM_FORMAT_SCALED),
+ FORMAT_COMP_ALL(SQ_FORMAT_COMP_SIGNED),
+ SRF_MODE_ALL(SRF_MODE_ZERO_CLAMP_MINUS_ONE));
+ shader[i++] = VTX_DWORD2(OFFSET(0),
+ ENDIAN_SWAP(ENDIAN_NONE),
+ CONST_BUF_NO_STRIDE(0),
+ MEGA_FETCH(1));
+ shader[i++] = VTX_DWORD_PAD;
+ /* 34/35 - src */
+ shader[i++] = VTX_DWORD0(VTX_INST(SQ_VTX_INST_FETCH),
+ FETCH_TYPE(SQ_VTX_FETCH_VERTEX_DATA),
+ FETCH_WHOLE_QUAD(0),
+ BUFFER_ID(0),
+ SRC_GPR(0),
+ SRC_REL(ABSOLUTE),
+ SRC_SEL_X(SQ_SEL_X),
+ MEGA_FETCH_COUNT(8));
+ shader[i++] = VTX_DWORD1_GPR(DST_GPR(1),
+ DST_REL(0),
+ DST_SEL_X(SQ_SEL_X),
+ DST_SEL_Y(SQ_SEL_Y),
+ DST_SEL_Z(SQ_SEL_1),
+ DST_SEL_W(SQ_SEL_0),
+ USE_CONST_FIELDS(0),
+ DATA_FORMAT(FMT_32_32_FLOAT),
+ NUM_FORMAT_ALL(SQ_NUM_FORMAT_SCALED),
+ FORMAT_COMP_ALL(SQ_FORMAT_COMP_SIGNED),
+ SRF_MODE_ALL(SRF_MODE_ZERO_CLAMP_MINUS_ONE));
+ shader[i++] = VTX_DWORD2(OFFSET(8),
+ ENDIAN_SWAP(ENDIAN_NONE),
+ CONST_BUF_NO_STRIDE(0),
+ MEGA_FETCH(0));
+ shader[i++] = VTX_DWORD_PAD;
+ /* 36/37 - mask */
+ shader[i++] = VTX_DWORD0(VTX_INST(SQ_VTX_INST_FETCH),
+ FETCH_TYPE(SQ_VTX_FETCH_VERTEX_DATA),
+ FETCH_WHOLE_QUAD(0),
+ BUFFER_ID(0),
+ SRC_GPR(0),
+ SRC_REL(ABSOLUTE),
+ SRC_SEL_X(SQ_SEL_X),
+ MEGA_FETCH_COUNT(8));
+ shader[i++] = VTX_DWORD1_GPR(DST_GPR(0),
+ DST_REL(0),
+ DST_SEL_X(SQ_SEL_X),
+ DST_SEL_Y(SQ_SEL_Y),
+ DST_SEL_Z(SQ_SEL_1),
+ DST_SEL_W(SQ_SEL_0),
+ USE_CONST_FIELDS(0),
+ DATA_FORMAT(FMT_32_32_FLOAT),
+ NUM_FORMAT_ALL(SQ_NUM_FORMAT_SCALED),
+ FORMAT_COMP_ALL(SQ_FORMAT_COMP_SIGNED),
+ SRF_MODE_ALL(SRF_MODE_ZERO_CLAMP_MINUS_ONE));
+ shader[i++] = VTX_DWORD2(OFFSET(16),
+ ENDIAN_SWAP(ENDIAN_NONE),
+ CONST_BUF_NO_STRIDE(0),
+ MEGA_FETCH(0));
+ shader[i++] = VTX_DWORD_PAD;
- /* 40/41 - dst */
+ /* 38/39 - dst - non-mask */
shader[i++] = VTX_DWORD0(VTX_INST(SQ_VTX_INST_FETCH),
FETCH_TYPE(SQ_VTX_FETCH_VERTEX_DATA),
FETCH_WHOLE_QUAD(0),
@@ -2126,7 +2117,7 @@ int R600_comp_vs(RADEONChipFamily ChipSet, uint32_t* shader)
CONST_BUF_NO_STRIDE(0),
MEGA_FETCH(1));
shader[i++] = VTX_DWORD_PAD;
- /* 42/43 - src */
+ /* 40/41 - src */
shader[i++] = VTX_DWORD0(VTX_INST(SQ_VTX_INST_FETCH),
FETCH_TYPE(SQ_VTX_FETCH_VERTEX_DATA),
FETCH_WHOLE_QUAD(0),
commit f9d6c0de231357f96e2e0de71e6c9221bcb36bd4
Author: Gaetan Nadon <memsize at videotron.ca>
Date: Fri Jul 23 13:28:42 2010 -0400
The local copy of the modes code is no longer required.
The server 1.2 as shipped in the tarball on the web does not contain the
modes code. It was added just after and found in git branch server-1.2-branch.
The modes code was initially included in version ati 6.8.0 and fails to compile
with server 1.2 as it requires randr 1.2. The modes code is included in server
versions 1.3 and later, so there is no need to provide an unknown version of
the modes code in the ati driver tarball. It will never be used.
This patch makes the ati driver requiring server 1.3 or later.
Version 6.8.0 configures and builds ok on server 1.3
Master branch post 6.13.1 configures and builds ok on server 1.3
Signed-off-by: Gaetan Nadon <memsize at videotron.ca>
diff --git a/configure.ac b/configure.ac
index 45ecd38..decc46f 100644
--- a/configure.ac
+++ b/configure.ac
@@ -81,11 +81,6 @@ AC_ARG_ENABLE(kms,
[DRM_MODE="$enableval"],
[DRM_MODE=yes])
-AC_ARG_WITH(xserver-source,AS_HELP_STRING([--with-xserver-source=XSERVER_SOURCE],
- [Path to X server source tree]),
- [ XSERVER_SOURCE="$withval" ],
- [ XSERVER_SOURCE="" ])
-
# Store the list of server defined optional extensions in REQUIRED_MODULES
XORG_DRIVER_CHECK_EXT(RANDR, randrproto)
XORG_DRIVER_CHECK_EXT(RENDER, renderproto)
@@ -93,7 +88,7 @@ XORG_DRIVER_CHECK_EXT(XV, videoproto)
XORG_DRIVER_CHECK_EXT(DPMSExtension, xextproto)
# Obtain compiler/linker options for the driver dependencies
-PKG_CHECK_MODULES(XORG, [xorg-server >= 1.2 xproto fontsproto $REQUIRED_MODULES])
+PKG_CHECK_MODULES(XORG, [xorg-server >= 1.3 xproto fontsproto $REQUIRED_MODULES])
PKG_CHECK_MODULES(XEXT, [xextproto >= 7.0.99.1],
HAVE_XEXTPROTO_71="yes"; AC_DEFINE(HAVE_XEXTPROTO_71, 1, [xextproto 7.1 available]),
HAVE_XEXTPROTO_71="no")
@@ -168,11 +163,6 @@ fi
AM_CONDITIONAL(DRM_MODE, test x$DRM_MODE = xyes)
AM_CONDITIONAL(LIBUDEV, test x$LIBUDEV = xyes)
-save_CFLAGS="$CFLAGS"
-CFLAGS="$XORG_CFLAGS"
-AC_CHECK_HEADER(xf86Modes.h,[XMODES=yes],[XMODES=no],[#include "xorg-server.h"])
-CFLAGS="$save_CFLAGS"
-
AC_DEFINE(USE_XAA, 1, [Build support for XAA])
# Properly handle EXA.
@@ -243,48 +233,6 @@ AC_CHECK_DECL(XSERVER_LIBPCIACCESS,
[XSERVER_LIBPCIACCESS=yes],[XSERVER_LIBPCIACCESS=no],
[#include "xorg-server.h"])
-AM_CONDITIONAL(XMODES, test "x$XMODES" = xno)
-
-if test "x$XSERVER_SOURCE" = x; then
- if test -d ../../xserver; then
- XSERVER_SOURCE="`cd ../../xserver && pwd`"
- fi
-fi
-
-if test -d "$XSERVER_SOURCE"; then
- case "$XSERVER_SOURCE" in
- /*)
- ;;
- *)
- XSERVER_SOURCE="`cd $XSERVER_SOURCE && pwd`"
- esac
- if test -f src/modes/xf86Modes.h; then
- :
- else
- ln -sf $XSERVER_SOURCE/hw/xfree86/modes src/modes
- fi
-
- if test -f src/parser/xf86Parser.h; then
- :
- else
- ln -sf $XSERVER_SOURCE/hw/xfree86/parser src/parser
- fi
-fi
-if test "x$XMODES" = xyes; then
- AC_MSG_NOTICE([X server has new mode code])
- AC_DEFINE(XMODES, 1,[X server has built-in mode code])
- XMODES_CFLAGS=
-else
- if test -f src/modes/xf86Modes.h -a -f src/parser/xf86Parser.h; then
- AC_MSG_NOTICE([X server is missing new mode code, using local copy])
- else
- AC_MSG_ERROR([Must have X server >= 1.3 source tree for mode setting code. Please specify --with-xserver-source])
- fi
- XMODES_CFLAGS='-DXF86_MODES_RENAME -I$(top_srcdir)/src -I$(top_srcdir)/src/modes -I$(top_srcdir)/src/parser'
-fi
-
-AC_SUBST([XMODES_CFLAGS])
-
CPPFLAGS="$SAVE_CPPFLAGS"
AM_CONDITIONAL(USE_EXA, test "x$USE_EXA" = xyes)
diff --git a/src/Makefile.am b/src/Makefile.am
index 0ce46b0..5750770 100644
--- a/src/Makefile.am
+++ b/src/Makefile.am
@@ -48,23 +48,6 @@ RADEON_ATOMBIOS_SOURCES = \
AtomBios/includes/ObjectID.h \
AtomBios/includes/regsdef.h
-XMODE_SRCS=\
- local_xf86Rename.h \
- parser/xf86Parser.h \
- parser/xf86Optrec.h \
- modes/xf86Modes.h \
- modes/xf86Modes.c \
- modes/xf86cvt.c \
- modes/xf86Crtc.h \
- modes/xf86Crtc.c \
- modes/xf86Cursors.c \
- modes/xf86EdidModes.c \
- modes/xf86RandR12.c \
- modes/xf86RandR12.h \
- modes/xf86Rename.h \
- modes/xf86Rotate.c \
- modes/xf86DiDGA.c
-
if XF86DRM_MODE
RADEON_KMS_SRCS=radeon_dri2.c radeon_kms.c drmmode_display.c radeon_vbo.c
endif
@@ -77,7 +60,6 @@ AM_CFLAGS = \
@LIBDRM_RADEON_CFLAGS@ \
@XORG_CFLAGS@ \
@DRI_CFLAGS@ \
- @XMODES_CFLAGS@ \
@LIBUDEV_CFLAGS@ \
-DDISABLE_EASF \
-DENABLE_ALL_SERVICE_FUNCTIONS \
@@ -116,11 +98,6 @@ radeon_drv_la_SOURCES = \
$(RADEON_DRI_SRCS) $(RADEON_EXA_SOURCES) atombios_output.c atombios_crtc.c \
$(RADEON_KMS_SRCS)
-if XMODES
-radeon_drv_la_SOURCES += \
- $(XMODE_SRCS)
-endif
-
theatre_detect_drv_la_LTLIBRARIES = theatre_detect_drv.la
theatre_detect_drv_la_LDFLAGS = -module -avoid-version
theatre_detect_drv_ladir = @moduledir@/multimedia
@@ -143,7 +120,6 @@ theatre200_drv_la_SOURCES = \
theatre200.c theatre200_module.c
EXTRA_DIST = \
- $(XMODE_SRCS) \
radeon_render.c \
radeon_accelfuncs.c \
radeon_textured_videofuncs.c \
diff --git a/src/local_xf86Rename.h b/src/local_xf86Rename.h
deleted file mode 100644
index 5102170..0000000
--- a/src/local_xf86Rename.h
+++ /dev/null
@@ -1,23 +0,0 @@
-/*
- * Copyright © 2006 Keith Packard
- *
- * Permission to use, copy, modify, distribute, and sell this software and its
- * documentation for any purpose is hereby granted without fee, provided that
- * the above copyright notice appear in all copies and that both that copyright
- * notice and this permission notice appear in supporting documentation, and
- * that the name of the copyright holders not be used in advertising or
- * publicity pertaining to distribution of the software without specific,
- * written prior permission. The copyright holders make no representations
- * about the suitability of this software for any purpose. It is provided "as
- * is" without express or implied warranty.
- *
- * THE COPYRIGHT HOLDERS DISCLAIM ALL WARRANTIES WITH REGARD TO THIS SOFTWARE,
- * INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO
- * EVENT SHALL THE COPYRIGHT HOLDERS BE LIABLE FOR ANY SPECIAL, INDIRECT OR
- * CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE,
- * DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
- * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE
- * OF THIS SOFTWARE.
- */
-
-#define XF86NAME(x) radeon_##x
commit 0028419acb0762eeb950de5fe702c93e70301612
Author: Gaetan Nadon <memsize at videotron.ca>
Date: Sat Jul 24 10:51:18 2010 -0400
config: add AM_PROG_CC_C_O for per-target compilation flags
Per-target compilation flags (theatre200_drv_la_CFLAGS) are required
when multiple targets which require different compiler flags,
are build in the same makefile.
Automake issues a command with -c and -o flags which not all compilers
support. The object fles are prefixed with theatre200_drv_la.
The macro AM_PROG_CC_C_O must then be used to provide this feature
on compilers that do not have it. If not, a warning is issued at make time.
This macros checks for compiler support and if missing, uses a "compile"
script it generates in the package root directory.
Signed-off-by: Gaetan Nadon <memsize at videotron.ca>
diff --git a/configure.ac b/configure.ac
index c367e4d..45ecd38 100644
--- a/configure.ac
+++ b/configure.ac
@@ -48,6 +48,9 @@ AM_MAINTAINER_MODE
AC_DISABLE_STATIC
AC_PROG_LIBTOOL
+# Checks for programs.
+AM_PROG_CC_C_O
+
if test "x$GCC" = "xyes"; then
CPPFLAGS="$CPPFLAGS -Wall"
fi
commit aca0a8669b538d58f018f95c9b22e6b3ec1ffe50
Author: Gaetan Nadon <memsize at videotron.ca>
Date: Wed Jul 21 16:49:04 2010 -0400
config: add comments for main statements
diff --git a/configure.ac b/configure.ac
index 765ef64..c367e4d 100644
--- a/configure.ac
+++ b/configure.ac
@@ -20,6 +20,7 @@
#
# Process this file with autoconf to produce a configure script
+# Initialize Autoconf
AC_PREREQ([2.60])
AC_INIT([xf86-video-ati],
[6.13.99],
@@ -37,12 +38,13 @@ XORG_DEFAULT_OPTIONS
AC_CONFIG_AUX_DIR(.)
+# Initialize Automake
AM_INIT_AUTOMAKE([foreign dist-bzip2])
AC_SYS_LARGEFILE
AM_MAINTAINER_MODE
-# Checks for programs.
+# Initialize libtool
AC_DISABLE_STATIC
AC_PROG_LIBTOOL
@@ -52,6 +54,7 @@ fi
AH_TOP([#include "xorg-server.h"])
+# Define a configure option for an alternate module directory
AC_ARG_WITH(xorg-module-dir,
AS_HELP_STRING([--with-xorg-module-dir=DIR],
[Default xorg module directory [[default=$libdir/xorg/modules]]]),
@@ -80,13 +83,13 @@ AC_ARG_WITH(xserver-source,AS_HELP_STRING([--with-xserver-source=XSERVER_SOURCE]
[ XSERVER_SOURCE="$withval" ],
[ XSERVER_SOURCE="" ])
-# Checks for extensions
+# Store the list of server defined optional extensions in REQUIRED_MODULES
XORG_DRIVER_CHECK_EXT(RANDR, randrproto)
XORG_DRIVER_CHECK_EXT(RENDER, renderproto)
XORG_DRIVER_CHECK_EXT(XV, videoproto)
XORG_DRIVER_CHECK_EXT(DPMSExtension, xextproto)
-# Checks for pkg-config packages
+# Obtain compiler/linker options for the driver dependencies
PKG_CHECK_MODULES(XORG, [xorg-server >= 1.2 xproto fontsproto $REQUIRED_MODULES])
PKG_CHECK_MODULES(XEXT, [xextproto >= 7.0.99.1],
HAVE_XEXTPROTO_71="yes"; AC_DEFINE(HAVE_XEXTPROTO_71, 1, [xextproto 7.1 available]),
commit 66e614f7115efeec237b3b916d9637e8b3e8985c
Author: Gaetan Nadon <memsize at videotron.ca>
Date: Wed Jul 21 16:07:00 2010 -0400
config: replace deprecated use of AC_OUTPUT with AC_CONFIG_FILES
Signed-off-by: Gaetan Nadon <memsize at videotron.ca>
diff --git a/configure.ac b/configure.ac
index ddad246..765ef64 100644
--- a/configure.ac
+++ b/configure.ac
@@ -373,11 +373,12 @@ AC_MSG_NOTICE(
[Please install that driver as well for rage128-based cards.]
)
-AC_OUTPUT([
- Makefile
- src/Makefile
- man/Makefile
+AC_CONFIG_FILES([
+ Makefile
+ src/Makefile
+ man/Makefile
])
+AC_OUTPUT
dnl
dnl Output some configuration info for the user
commit 16e5510c90ef1ba2bbaab78d18943f080b86d809
Author: Gaetan Nadon <memsize at videotron.ca>
Date: Wed Jul 21 14:37:41 2010 -0400
config: replace deprecated AC_HELP_STRING with AS_HELP_STRING
Signed-off-by: Gaetan Nadon <memsize at videotron.ca>
diff --git a/configure.ac b/configure.ac
index 20fe026..ddad246 100644
--- a/configure.ac
+++ b/configure.ac
@@ -53,29 +53,29 @@ fi
AH_TOP([#include "xorg-server.h"])
AC_ARG_WITH(xorg-module-dir,
- AC_HELP_STRING([--with-xorg-module-dir=DIR],
+ AS_HELP_STRING([--with-xorg-module-dir=DIR],
[Default xorg module directory [[default=$libdir/xorg/modules]]]),
[moduledir="$withval"],
[moduledir="$libdir/xorg/modules"])
-AC_ARG_ENABLE(dri, AC_HELP_STRING([--disable-dri],
+AC_ARG_ENABLE(dri, AS_HELP_STRING([--disable-dri],
[Disable DRI support [[default=auto]]]),
[DRI="$enableval"],
[DRI=auto])
AC_ARG_ENABLE(exa,
- AC_HELP_STRING([--disable-exa],
+ AS_HELP_STRING([--disable-exa],
[Disable EXA support [[default=enabled]]]),
[EXA="$enableval"],
[EXA=yes])
AC_ARG_ENABLE(kms,
- AC_HELP_STRING([--disable-kms],
+ AS_HELP_STRING([--disable-kms],
[Disable KMS support [[default=enabled]]]),
[DRM_MODE="$enableval"],
[DRM_MODE=yes])
-AC_ARG_WITH(xserver-source,AC_HELP_STRING([--with-xserver-source=XSERVER_SOURCE],
+AC_ARG_WITH(xserver-source,AS_HELP_STRING([--with-xserver-source=XSERVER_SOURCE],
[Path to X server source tree]),
[ XSERVER_SOURCE="$withval" ],
[ XSERVER_SOURCE="" ])
commit b36d8c09e91382f4cfa71635374ec88f5b676d1c
Author: Gaetan Nadon <memsize at videotron.ca>
Date: Wed Jul 21 14:05:22 2010 -0400
config: replace deprecated AM_CONFIG_HEADER with AC_CONFIG_HEADERS
Signed-off-by: Gaetan Nadon <memsize at videotron.ca>
diff --git a/configure.ac b/configure.ac
index 9126e90..20fe026 100644
--- a/configure.ac
+++ b/configure.ac
@@ -27,7 +27,7 @@ AC_INIT([xf86-video-ati],
[xf86-video-ati])
AC_CONFIG_SRCDIR([Makefile.am])
-AM_CONFIG_HEADER([config.h])
+AC_CONFIG_HEADERS([config.h])
# Require X.Org macros 1.8 or later for MAN_SUBSTS set by XORG_MANPAGE_SECTIONS
m4_ifndef([XORG_MACROS_VERSION],
commit cd9351b04c2d6982b28c647a63d550eb3e1937eb
Author: Alex Deucher <alexdeucher at gmail.com>
Date: Wed Jul 21 13:48:24 2010 -0400
r6xx/r7xx: group op variable state
Group the op variable state into one emit block, re-order
to reduce dwords emitted.
diff --git a/src/r600_exa.c b/src/r600_exa.c
index b1c024a..89d5877 100644
--- a/src/r600_exa.c
+++ b/src/r600_exa.c
@@ -364,20 +364,6 @@ R600PrepareSolid(PixmapPtr pPix, int alu, Pixel pm, Pixel fg)
ps_conf.bo = accel_state->shaders_bo;
ps_setup (pScrn, accel_state->ib, &ps_conf, RADEON_GEM_DOMAIN_VRAM);
- /* Render setup */
- if (accel_state->planemask & 0x000000ff)
- pmask |= 4; /* B */
- if (accel_state->planemask & 0x0000ff00)
- pmask |= 2; /* G */
- if (accel_state->planemask & 0x00ff0000)
- pmask |= 1; /* R */
- if (accel_state->planemask & 0xff000000)
- pmask |= 8; /* A */
- BEGIN_BATCH(6);
- EREG(accel_state->ib, CB_TARGET_MASK, (pmask << TARGET0_ENABLE_shift));
- EREG(accel_state->ib, CB_COLOR_CONTROL, RADEON_ROP[accel_state->rop]);
- END_BATCH();
-
cb_conf.id = 0;
cb_conf.w = accel_state->dst_obj.pitch;
cb_conf.h = accel_state->dst_obj.height;
@@ -398,23 +384,36 @@ R600PrepareSolid(PixmapPtr pPix, int alu, Pixel pm, Pixel fg)
cb_conf.blend_clamp = 1;
set_render_target(pScrn, accel_state->ib, &cb_conf, accel_state->dst_obj.domain);
+ /* Render setup */
+ if (accel_state->planemask & 0x000000ff)
+ pmask |= 4; /* B */
+ if (accel_state->planemask & 0x0000ff00)
+ pmask |= 2; /* G */
+ if (accel_state->planemask & 0x00ff0000)
+ pmask |= 1; /* R */
+ if (accel_state->planemask & 0xff000000)
+ pmask |= 8; /* A */
+ BEGIN_BATCH(20);
+ EREG(accel_state->ib, CB_TARGET_MASK, (pmask << TARGET0_ENABLE_shift));
+ EREG(accel_state->ib, CB_COLOR_CONTROL, RADEON_ROP[accel_state->rop]);
+
/* Interpolator setup */
/* one unused export from VS (VS_EXPORT_COUNT is zero based, count minus one) */
- BEGIN_BATCH(18);
EREG(accel_state->ib, SPI_VS_OUT_CONFIG, (0 << VS_EXPORT_COUNT_shift));
EREG(accel_state->ib, SPI_VS_OUT_ID_0, (0 << SEMANTIC_0_shift));
-
- /* Enabling flat shading needs both FLAT_SHADE_bit in SPI_PS_INPUT_CNTL_x
- * *and* FLAT_SHADE_ENA_bit in SPI_INTERP_CONTROL_0 */
- /* no VS exports as PS input (NUM_INTERP is not zero based, no minus one) */
- EREG(accel_state->ib, SPI_PS_IN_CONTROL_0, (0 << NUM_INTERP_shift));
- EREG(accel_state->ib, SPI_PS_IN_CONTROL_1, 0);
/* color semantic id 0 -> GPR[0] */
- EREG(accel_state->ib, SPI_PS_INPUT_CNTL_0 + (0 <<2), ((0 << SEMANTIC_shift) |
+ EREG(accel_state->ib, SPI_PS_INPUT_CNTL_0 + (0 << 2), ((0 << SEMANTIC_shift) |
(0x03 << DEFAULT_VAL_shift) |
FLAT_SHADE_bit |
SEL_CENTROID_bit));
- EREG(accel_state->ib, SPI_INTERP_CONTROL_0, FLAT_SHADE_ENA_bit);
+
+ /* Enabling flat shading needs both FLAT_SHADE_bit in SPI_PS_INPUT_CNTL_x
+ * *and* FLAT_SHADE_ENA_bit in SPI_INTERP_CONTROL_0 */
+ /* no VS exports as PS input (NUM_INTERP is not zero based, no minus one) */
+ PACK0(accel_state->ib, SPI_PS_IN_CONTROL_0, 3);
+ E32(accel_state->ib, (0 << NUM_INTERP_shift));
+ E32(accel_state->ib, 0);
+ E32(accel_state->ib, FLAT_SHADE_ENA_bit);
END_BATCH();
/* PS alu constants */
@@ -598,21 +597,6 @@ R600DoPrepareCopy(ScrnInfoPtr pScrn)
tex_samp.mip_filter = 0; /* no mipmap */
set_tex_sampler (pScrn, accel_state->ib, &tex_samp);
-
- /* Render setup */
- if (accel_state->planemask & 0x000000ff)
- pmask |= 4; /* B */
- if (accel_state->planemask & 0x0000ff00)
- pmask |= 2; /* G */
- if (accel_state->planemask & 0x00ff0000)
- pmask |= 1; /* R */
- if (accel_state->planemask & 0xff000000)
- pmask |= 8; /* A */
- BEGIN_BATCH(6);
- EREG(accel_state->ib, CB_TARGET_MASK, (pmask << TARGET0_ENABLE_shift));
- EREG(accel_state->ib, CB_COLOR_CONTROL, RADEON_ROP[accel_state->rop]);
- END_BATCH();
-
cb_conf.id = 0;
cb_conf.w = accel_state->dst_obj.pitch;
cb_conf.h = accel_state->dst_obj.height;
@@ -632,22 +616,35 @@ R600DoPrepareCopy(ScrnInfoPtr pScrn)
cb_conf.blend_clamp = 1;
set_render_target(pScrn, accel_state->ib, &cb_conf, accel_state->dst_obj.domain);
+ /* Render setup */
+ if (accel_state->planemask & 0x000000ff)
+ pmask |= 4; /* B */
+ if (accel_state->planemask & 0x0000ff00)
+ pmask |= 2; /* G */
+ if (accel_state->planemask & 0x00ff0000)
+ pmask |= 1; /* R */
+ if (accel_state->planemask & 0xff000000)
+ pmask |= 8; /* A */
+ BEGIN_BATCH(20);
+ EREG(accel_state->ib, CB_TARGET_MASK, (pmask << TARGET0_ENABLE_shift));
+ EREG(accel_state->ib, CB_COLOR_CONTROL, RADEON_ROP[accel_state->rop]);
+
/* Interpolator setup */
/* export tex coord from VS */
- BEGIN_BATCH(18);
EREG(accel_state->ib, SPI_VS_OUT_CONFIG, ((1 - 1) << VS_EXPORT_COUNT_shift));
EREG(accel_state->ib, SPI_VS_OUT_ID_0, (0 << SEMANTIC_0_shift));
+ /* color semantic id 0 -> GPR[0] */
+ EREG(accel_state->ib, SPI_PS_INPUT_CNTL_0 + (0 << 2), ((0 << SEMANTIC_shift) |
+ (0x01 << DEFAULT_VAL_shift) |
+ SEL_CENTROID_bit));
/* Enabling flat shading needs both FLAT_SHADE_bit in SPI_PS_INPUT_CNTL_x
* *and* FLAT_SHADE_ENA_bit in SPI_INTERP_CONTROL_0 */
/* input tex coord from VS */
- EREG(accel_state->ib, SPI_PS_IN_CONTROL_0, ((1 << NUM_INTERP_shift)));
- EREG(accel_state->ib, SPI_PS_IN_CONTROL_1, 0);
- /* color semantic id 0 -> GPR[0] */
- EREG(accel_state->ib, SPI_PS_INPUT_CNTL_0 + (0 <<2), ((0 << SEMANTIC_shift) |
- (0x01 << DEFAULT_VAL_shift) |
- SEL_CENTROID_bit));
- EREG(accel_state->ib, SPI_INTERP_CONTROL_0, 0);
+ PACK0(accel_state->ib, SPI_PS_IN_CONTROL_0, 3);
+ E32(accel_state->ib, ((1 << NUM_INTERP_shift)));
+ E32(accel_state->ib, 0);
+ E32(accel_state->ib, 0);
END_BATCH();
}
@@ -1526,23 +1523,6 @@ static Bool R600PrepareComposite(int op, PicturePtr pSrcPicture,
ps_conf.bo = accel_state->shaders_bo;
ps_setup (pScrn, accel_state->ib, &ps_conf, RADEON_GEM_DOMAIN_VRAM);
- BEGIN_BATCH(9);
- EREG(accel_state->ib, CB_TARGET_MASK, (0xf << TARGET0_ENABLE_shift));
-
- blendcntl = R600GetBlendCntl(op, pMaskPicture, pDstPicture->format);
-
- if (info->ChipFamily == CHIP_FAMILY_R600) {
- /* no per-MRT blend on R600 */
- EREG(accel_state->ib, CB_COLOR_CONTROL, RADEON_ROP[3] | (1 << TARGET_BLEND_ENABLE_shift));
- EREG(accel_state->ib, CB_BLEND_CONTROL, blendcntl);
- } else {
- EREG(accel_state->ib, CB_COLOR_CONTROL, (RADEON_ROP[3] |
- (1 << TARGET_BLEND_ENABLE_shift) |
- PER_MRT_BLEND_bit));
- EREG(accel_state->ib, CB_BLEND0_CONTROL, blendcntl);
- }
- END_BATCH();
-
cb_conf.id = 0;
cb_conf.w = accel_state->dst_obj.pitch;
cb_conf.h = accel_state->dst_obj.height;
@@ -1579,34 +1559,56 @@ static Bool R600PrepareComposite(int op, PicturePtr pSrcPicture,
cb_conf.blend_clamp = 1;
set_render_target(pScrn, accel_state->ib, &cb_conf, accel_state->dst_obj.domain);
+ BEGIN_BATCH(24);
+ EREG(accel_state->ib, CB_TARGET_MASK, (0xf << TARGET0_ENABLE_shift));
+
+ blendcntl = R600GetBlendCntl(op, pMaskPicture, pDstPicture->format);
+
+ if (info->ChipFamily == CHIP_FAMILY_R600) {
+ /* no per-MRT blend on R600 */
+ EREG(accel_state->ib, CB_COLOR_CONTROL, RADEON_ROP[3] | (1 << TARGET_BLEND_ENABLE_shift));
+ EREG(accel_state->ib, CB_BLEND_CONTROL, blendcntl);
+ } else {
+ EREG(accel_state->ib, CB_COLOR_CONTROL, (RADEON_ROP[3] |
+ (1 << TARGET_BLEND_ENABLE_shift) |
+ PER_MRT_BLEND_bit));
+ EREG(accel_state->ib, CB_BLEND0_CONTROL, blendcntl);
+ }
+
/* Interpolator setup */
- BEGIN_BATCH(21);
if (pMask) {
/* export 2 tex coords from VS */
EREG(accel_state->ib, SPI_VS_OUT_CONFIG, ((2 - 1) << VS_EXPORT_COUNT_shift));
/* src = semantic id 0; mask = semantic id 1 */
EREG(accel_state->ib, SPI_VS_OUT_ID_0, ((0 << SEMANTIC_0_shift) |
(1 << SEMANTIC_1_shift)));
- /* input 2 tex coords from VS */
- EREG(accel_state->ib, SPI_PS_IN_CONTROL_0, (2 << NUM_INTERP_shift));
} else {
/* export 1 tex coords from VS */
EREG(accel_state->ib, SPI_VS_OUT_CONFIG, ((1 - 1) << VS_EXPORT_COUNT_shift));
/* src = semantic id 0 */
EREG(accel_state->ib, SPI_VS_OUT_ID_0, (0 << SEMANTIC_0_shift));
- /* input 1 tex coords from VS */
- EREG(accel_state->ib, SPI_PS_IN_CONTROL_0, (1 << NUM_INTERP_shift));
}
- EREG(accel_state->ib, SPI_PS_IN_CONTROL_1, 0);
+
+ PACK0(accel_state->ib, SPI_PS_INPUT_CNTL_0 + (0 << 2), 2);
/* SPI_PS_INPUT_CNTL_0 maps to GPR[0] - load with semantic id 0 */
- EREG(accel_state->ib, SPI_PS_INPUT_CNTL_0 + (0 <<2), ((0 << SEMANTIC_shift) |
- (0x01 << DEFAULT_VAL_shift) |
- SEL_CENTROID_bit));
+ E32(accel_state->ib, ((0 << SEMANTIC_shift) |
+ (0x01 << DEFAULT_VAL_shift) |
+ SEL_CENTROID_bit));
/* SPI_PS_INPUT_CNTL_1 maps to GPR[1] - load with semantic id 1 */
- EREG(accel_state->ib, SPI_PS_INPUT_CNTL_0 + (1 <<2), ((1 << SEMANTIC_shift) |
- (0x01 << DEFAULT_VAL_shift) |
- SEL_CENTROID_bit));
- EREG(accel_state->ib, SPI_INTERP_CONTROL_0, 0);
+ E32(accel_state->ib, ((1 << SEMANTIC_shift) |
+ (0x01 << DEFAULT_VAL_shift) |
+ SEL_CENTROID_bit));
+
+ PACK0(accel_state->ib, SPI_PS_IN_CONTROL_0, 3);
+ if (pMask) {
+ /* input 2 tex coords from VS */
+ E32(accel_state->ib, (2 << NUM_INTERP_shift));
+ } else {
+ /* input 1 tex coords from VS */
+ E32(accel_state->ib, (1 << NUM_INTERP_shift));
+ }
+ E32(accel_state->ib, 0);
+ E32(accel_state->ib, 0);
END_BATCH();
if (accel_state->vsync)
diff --git a/src/r600_textured_videofuncs.c b/src/r600_textured_videofuncs.c
index 2a86df3..e75d9fe 100644
--- a/src/r600_textured_videofuncs.c
+++ b/src/r600_textured_videofuncs.c
@@ -437,12 +437,6 @@ R600DisplayTexturedVideo(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv)
break;
}
- /* Render setup */
- BEGIN_BATCH(6);
- EREG(accel_state->ib, CB_TARGET_MASK, (0x0f << TARGET0_ENABLE_shift));
- EREG(accel_state->ib, CB_COLOR_CONTROL, (0xcc << ROP3_shift)); /* copy */
- END_BATCH();
-
cb_conf.id = 0;
cb_conf.w = accel_state->dst_obj.pitch;
cb_conf.h = accel_state->dst_obj.height;
@@ -471,20 +465,25 @@ R600DisplayTexturedVideo(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv)
cb_conf.blend_clamp = 1;
set_render_target(pScrn, accel_state->ib, &cb_conf, accel_state->dst_obj.domain);
+ /* Render setup */
+ BEGIN_BATCH(20);
+ EREG(accel_state->ib, CB_TARGET_MASK, (0x0f << TARGET0_ENABLE_shift));
+ EREG(accel_state->ib, CB_COLOR_CONTROL, (0xcc << ROP3_shift)); /* copy */
+
/* Interpolator setup */
/* export tex coords from VS */
- BEGIN_BATCH(18);
EREG(accel_state->ib, SPI_VS_OUT_CONFIG, ((1 - 1) << VS_EXPORT_COUNT_shift));
EREG(accel_state->ib, SPI_VS_OUT_ID_0, (0 << SEMANTIC_0_shift));
+ EREG(accel_state->ib, SPI_PS_INPUT_CNTL_0 + (0 << 2), ((0 << SEMANTIC_shift) |
+ (0x03 << DEFAULT_VAL_shift) |
+ SEL_CENTROID_bit));
/* Enabling flat shading needs both FLAT_SHADE_bit in SPI_PS_INPUT_CNTL_x
* *and* FLAT_SHADE_ENA_bit in SPI_INTERP_CONTROL_0 */
- EREG(accel_state->ib, SPI_PS_IN_CONTROL_0, ((1 << NUM_INTERP_shift)));
- EREG(accel_state->ib, SPI_PS_IN_CONTROL_1, 0);
- EREG(accel_state->ib, SPI_PS_INPUT_CNTL_0 + (0 <<2), ((0 << SEMANTIC_shift) |
- (0x03 << DEFAULT_VAL_shift) |
- SEL_CENTROID_bit));
- EREG(accel_state->ib, SPI_INTERP_CONTROL_0, 0);
+ PACK0(accel_state->ib, SPI_PS_IN_CONTROL_0, 3);
+ E32(accel_state->ib, ((1 << NUM_INTERP_shift)));
+ E32(accel_state->ib, 0);
+ E32(accel_state->ib, 0);
END_BATCH();
vs_alu_consts[0] = 1.0 / pPriv->w;
commit 5f838c664e8010f4e51afecd4100d73a96fe1209
Author: Gaetan Nadon <memsize at videotron.ca>
Date: Wed Jul 21 09:27:42 2010 -0400
config: complete AC_INIT m4 quoting
Signed-off-by: Gaetan Nadon <memsize at videotron.ca>
diff --git a/configure.ac b/configure.ac
index fb09d5e..9126e90 100644
--- a/configure.ac
+++ b/configure.ac
@@ -22,9 +22,9 @@
AC_PREREQ([2.60])
AC_INIT([xf86-video-ati],
- 6.13.99,
+ [6.13.99],
[https://bugs.freedesktop.org/enter_bug.cgi?product=xorg],
- xf86-video-ati)
+ [xf86-video-ati])
AC_CONFIG_SRCDIR([Makefile.am])
AM_CONFIG_HEADER([config.h])
commit 48ec2e65c268b426ab9a3e214d174447cf5b5936
Author: Gaetan Nadon <memsize at videotron.ca>
Date: Wed Jul 21 08:33:38 2010 -0400
config: remove unrequired AC_SUBST for LIBDRM and LIBUDEV
These macros are called by the PKG_CHECK_MODULES macro.
Signed-off-by: Gaetan Nadon <memsize at videotron.ca>
diff --git a/configure.ac b/configure.ac
index 8bd4b97..fb09d5e 100644
--- a/configure.ac
+++ b/configure.ac
@@ -356,10 +356,6 @@ case $host_os in
AC_DEFINE(FGL_LINUX, 1, [Use linux pragma pack]) ;;
esac
-AC_SUBST([LIBDRM_RADEON_CFLAGS])
-AC_SUBST([LIBDRM_RADEON_LIBS])
-AC_SUBST([LIBUDEV_CFLAGS])
-AC_SUBST([LIBUDEV_LIBS])
AC_SUBST([moduledir])
DRIVER_NAME=ati
commit 1aabb7eb7d8f06c7481151145db3b9a722ce4ef0
Author: Gaetan Nadon <memsize at videotron.ca>
Date: Tue Jul 20 21:54:11 2010 -0400
config: remove unrequired AC_SUBST([DRI_CFLAGS])
This macro is called by PKG_CHECK_MODULES
Signed-off-by: Gaetan Nadon <memsize at videotron.ca>
diff --git a/configure.ac b/configure.ac
index 97f2eda..8bd4b97 100644
--- a/configure.ac
+++ b/configure.ac
@@ -356,7 +356,6 @@ case $host_os in
AC_DEFINE(FGL_LINUX, 1, [Use linux pragma pack]) ;;
esac
-AC_SUBST([DRI_CFLAGS])
AC_SUBST([LIBDRM_RADEON_CFLAGS])
AC_SUBST([LIBDRM_RADEON_LIBS])
AC_SUBST([LIBUDEV_CFLAGS])
commit 8f92b349821a3ee5ed8df55273d905b9605385aa
Author: Gaetan Nadon <memsize at videotron.ca>
Date: Tue Jul 20 21:44:57 2010 -0400
config: remove unrequired AC_SUBST([XORG_CFLAGS])
This macro is called by PKG_CHECK_MODULES
Signed-off-by: Gaetan Nadon <memsize at videotron.ca>
diff --git a/configure.ac b/configure.ac
index c7e4f0b..97f2eda 100644
--- a/configure.ac
+++ b/configure.ac
@@ -356,7 +356,6 @@ case $host_os in
AC_DEFINE(FGL_LINUX, 1, [Use linux pragma pack]) ;;
esac
-AC_SUBST([XORG_CFLAGS])
AC_SUBST([DRI_CFLAGS])
AC_SUBST([LIBDRM_RADEON_CFLAGS])
AC_SUBST([LIBDRM_RADEON_LIBS])
commit 5b483b832f9c4a5b92ffb7f72a470669201f1fba
Author: Gaetan Nadon <memsize at videotron.ca>
Date: Tue Jul 20 20:24:42 2010 -0400
config: remove unrequired AC_HEADER_STDC
Autoconf says:
"This macro is obsolescent, as current systems have conforming
header files. New programs need not use this macro".
Signed-off-by: Gaetan Nadon <memsize at videotron.ca>
diff --git a/configure.ac b/configure.ac
index e21c1f4..c7e4f0b 100644
--- a/configure.ac
+++ b/configure.ac
@@ -95,8 +95,6 @@ AM_CONDITIONAL(HAVE_XEXTPROTO_71, [ test "$HAVE_XEXTPROTO_71" = "yes" ])
# Checks for libraries.
-# Checks for header files.
-AC_HEADER_STDC
if test "$DRI" != no; then
PKG_CHECK_MODULES(DRI, [libdrm >= 2.2 xf86driproto])
commit 6574e3a16eb3631ee7e00ee60a8c9ba95c8b84ef
Author: Gaetan Nadon <memsize at videotron.ca>
Date: Tue Jul 20 19:41:30 2010 -0400
config: remove AC_PROG_CC as it overrides AC_PROG_C_C99
XORG_STRICT_OPTION from XORG_DEFAULT_OPTIONS calls
AC_PROG_C_C99. This sets gcc with -std=gnu99.
If AC_PROG_CC macro is called afterwards, it resets CC to gcc.
Signed-off-by: Gaetan Nadon <memsize at videotron.ca>
diff --git a/configure.ac b/configure.ac
index d847a6b..e21c1f4 100644
--- a/configure.ac
+++ b/configure.ac
@@ -45,7 +45,6 @@ AM_MAINTAINER_MODE
# Checks for programs.
AC_DISABLE_STATIC
AC_PROG_LIBTOOL
-AC_PROG_CC
if test "x$GCC" = "xyes"; then
CPPFLAGS="$CPPFLAGS -Wall"
commit 593eff2924c2ad161d8b490fbf6d7e433fbe2a80
Author: Gaetan Nadon <memsize at videotron.ca>
Date: Tue Jul 20 18:45:18 2010 -0400
config: update AC_PREREQ statement to 2.60
Unrelated to the previous patches, the new value simply reflects
the reality that the minimum level for autoconf to configure
all x.org modules is 2.60 dated June 2006.
ftp://ftp.gnu.org/gnu/autoconf/autoconf-2.60.tar.gz
Signed-off-by: Gaetan Nadon <memsize at videotron.ca>
diff --git a/configure.ac b/configure.ac
index baf7030..d847a6b 100644
--- a/configure.ac
+++ b/configure.ac
@@ -20,7 +20,7 @@
#
# Process this file with autoconf to produce a configure script
-AC_PREREQ(2.57)
+AC_PREREQ([2.60])
AC_INIT([xf86-video-ati],
6.13.99,
[https://bugs.freedesktop.org/enter_bug.cgi?product=xorg],
commit c2ab6ffc25aa6759cbbb4c1fbbd4a136b38983bf
Author: Gaetan Nadon <memsize at videotron.ca>
Date: Tue Jul 20 16:15:29 2010 -0400
config: upgrade to util-macros 1.8 for additional man page support
Use MAN_SUBST now supplied in XORG_MANPAGE_SECTIONS
The value of MAN_SUBST is the same for all X.Org packages.
diff --git a/configure.ac b/configure.ac
index cf0a855..baf7030 100644
--- a/configure.ac
+++ b/configure.ac
@@ -29,10 +29,10 @@ AC_INIT([xf86-video-ati],
AC_CONFIG_SRCDIR([Makefile.am])
AM_CONFIG_HEADER([config.h])
-# Require xorg-macros: XORG_DEFAULT_OPTIONS
-m4_ifndef([XORG_MACROS_VERSION],
- [m4_fatal([must install xorg-macros 1.3 or later before running autoconf/autogen])])
-XORG_MACROS_VERSION(1.3)
+# Require X.Org macros 1.8 or later for MAN_SUBSTS set by XORG_MANPAGE_SECTIONS
+m4_ifndef([XORG_MACROS_VERSION],
+ [m4_fatal([must install xorg-macros 1.8 or later before running autoconf/autogen])])
+XORG_MACROS_VERSION(1.8)
XORG_DEFAULT_OPTIONS
AC_CONFIG_AUX_DIR(.)
diff --git a/man/Makefile.am b/man/Makefile.am
index 9496782..8533765 100644
--- a/man/Makefile.am
+++ b/man/Makefile.am
@@ -31,25 +31,11 @@ EXTRA_DIST = @DRIVER_NAME at .man radeon.man
CLEANFILES = $(driverman_DATA)
-SED = sed
-
-# Strings to replace in man pages
-XORGRELSTRING = @PACKAGE_STRING@
- XORGMANNAME = X Version 11
-
-MAN_SUBSTS = \
- -e 's|__vendorversion__|"$(XORGRELSTRING)" "$(XORGMANNAME)"|' \
- -e 's|__xorgversion__|"$(XORGRELSTRING)" "$(XORGMANNAME)"|' \
- -e 's|__xservername__|Xorg|g' \
- -e 's|__xconfigfile__|xorg.conf|g' \
- -e 's|__projectroot__|$(prefix)|g' \
- -e 's|__appmansuffix__|$(APP_MAN_SUFFIX)|g' \
- -e 's|__drivermansuffix__|$(DRIVER_MAN_SUFFIX)|g' \
- -e 's|__adminmansuffix__|$(ADMIN_MAN_SUFFIX)|g' \
- -e 's|__miscmansuffix__|$(MISC_MAN_SUFFIX)|g' \
- -e 's|__filemansuffix__|$(FILE_MAN_SUFFIX)|g'
+
+# String replacements in MAN_SUBSTS now come from xorg-macros.m4 via configure
+
SUFFIXES = .$(DRIVER_MAN_SUFFIX) .man
.man.$(DRIVER_MAN_SUFFIX):
- sed $(MAN_SUBSTS) < $< > $@
+ $(AM_V_GEN)$(SED) $(MAN_SUBSTS) < $< > $@
commit cdeb1949c820242f05a8897d3ddd0718f204dacf
Author: Jerome Glisse <jglisse at redhat.com>
Date: Thu Jul 15 16:21:41 2010 -0400
kms: don't call cursor helper if using software cursor
Fix :
https://bugzilla.redhat.com/show_bug.cgi?id=601713
https://bugzilla.redhat.com/show_bug.cgi?id=598358
Signed-off-by: Jerome Glisse <jglisse at redhat.com>
diff --git a/src/drmmode_display.c b/src/drmmode_display.c
index 1366b36..e2d516b 100644
--- a/src/drmmode_display.c
+++ b/src/drmmode_display.c
@@ -347,7 +347,8 @@ drmmode_set_mode_major(xf86CrtcPtr crtc, DisplayModePtr mode,
}
}
- if (pScrn->pScreen)
+ if (pScrn->pScreen &&
+ !xf86ReturnOptValBool(info->Options, OPTION_SW_CURSOR, FALSE))
xf86_reload_cursors(pScrn->pScreen);
done:
commit 06691376b1ee963c711420edaf5a03eab6f5658f
Author: Dave Airlie <airlied at redhat.com>
Date: Wed Jul 7 13:15:03 2010 +1000
fix build on non-kms
diff --git a/src/r6xx_accel.c b/src/r6xx_accel.c
index 0edfe8b..73f9462 100644
--- a/src/r6xx_accel.c
+++ b/src/r6xx_accel.c
@@ -1262,9 +1262,9 @@ void r600_finish_op(ScrnInfoPtr pScrn, int vtx_size)
void r600_vb_no_space(ScrnInfoPtr pScrn, int vert_size)
{
-#ifdef XF86DRM_MODE
RADEONInfoPtr info = RADEONPTR(pScrn);
struct radeon_accel_state *accel_state = info->accel_state;
+#ifdef XF86DRM_MODE
if (info->cs) {
if (accel_state->vb_bo) {
commit 052cf0169ae70d5448af6dc4db840b2fc195569b
Author: Dave Airlie <airlied at redhat.com>
Date: Wed Jul 7 11:10:46 2010 +1000
configure.ac: bump version post release
diff --git a/configure.ac b/configure.ac
index 3a1c46a..cf0a855 100644
--- a/configure.ac
+++ b/configure.ac
@@ -22,7 +22,7 @@
AC_PREREQ(2.57)
AC_INIT([xf86-video-ati],
- 6.13.1,
+ 6.13.99,
[https://bugs.freedesktop.org/enter_bug.cgi?product=xorg],
xf86-video-ati)
commit ad999e633ff41d27eed9d2c6535e163a7181b0bd
Author: Dave Airlie <airlied at redhat.com>
Date: Wed Jul 7 10:49:22 2010 +1000
set version for release
diff --git a/configure.ac b/configure.ac
index cf0a855..3a1c46a 100644
--- a/configure.ac
+++ b/configure.ac
@@ -22,7 +22,7 @@
AC_PREREQ(2.57)
AC_INIT([xf86-video-ati],
- 6.13.99,
+ 6.13.1,
[https://bugs.freedesktop.org/enter_bug.cgi?product=xorg],
xf86-video-ati)
commit 37b348059b1c15d7b381cd3df3db52bd9ee6613e
Author: Alex Deucher <alexdeucher at gmail.com>
Date: Wed Jun 30 12:56:48 2010 -0400
remove rv100 quirk
Some RV100 cards with 2 VGA ports show up with DVI+VGA, however
some boards with DVI+VGA have the same subsystem ids. Better
to have a VGA port show up as DVI than having a non-useable
DVI port.
reported by DHR in irc.
Signed-off-by: Alex Deucher <alexdeucher at gmail.com>
diff --git a/src/radeon_bios.c b/src/radeon_bios.c
index 7d615c0..5810bdb 100644
--- a/src/radeon_bios.c
+++ b/src/radeon_bios.c
@@ -548,15 +548,6 @@ static void RADEONApplyLegacyQuirks(ScrnInfoPtr pScrn, int index)
}
}
- /* Some RV100 cards with 2 VGA ports show up with DVI+VGA */
- if (info->Chipset == PCI_CHIP_RV100_QY &&
- PCI_SUB_VENDOR_ID(info->PciInfo) == 0x1002 &&
- PCI_SUB_DEVICE_ID(info->PciInfo) == 0x013a) {
- if (info->BiosConnector[index].ConnectorType == CONNECTOR_DVI_I) {
- info->BiosConnector[index].ConnectorType = CONNECTOR_VGA;
- }
- }
-
/* X300 card with extra non-existent DVI port */
if (info->Chipset == PCI_CHIP_RV370_5B60 &&
PCI_SUB_VENDOR_ID(info->PciInfo) == 0x17af &&
commit c8ea942bd0e9d1c055d50b94440aa4dae425f20b
Author: Cooper Yuan <cooperyuan at gmail.com>
Date: Tue Jun 29 20:34:57 2010 +0800
Remove HDP_SOFT_RESET function, there is no need to reset HDP block.
This commit can fix an issue reported on DELL server, system gets hang
during soft resetting while another application tries to access PCI
configuration space.
diff --git a/src/radeon_accel.c b/src/radeon_accel.c
index 92503d9..281bc6d 100644
--- a/src/radeon_accel.c
+++ b/src/radeon_accel.c
@@ -328,10 +328,6 @@ void RADEONEngineReset(ScrnInfoPtr pScrn)
INREG(RADEON_RBBM_SOFT_RESET);
}
- OUTREG(RADEON_HOST_PATH_CNTL, host_path_cntl | RADEON_HDP_SOFT_RESET);
- INREG(RADEON_HOST_PATH_CNTL);
- OUTREG(RADEON_HOST_PATH_CNTL, host_path_cntl);
-
if (!IS_R300_VARIANT && !IS_AVIVO_VARIANT)
OUTREG(RADEON_RBBM_SOFT_RESET, rbbm_soft_reset);
commit 139b38bf67ec10d876cc56df833541d497ae4fa4
Author: Alex Deucher <alexdeucher at gmail.com>
Date: Thu Jun 24 14:55:09 2010 -0400
r6xx shader: use ADDR() for CF_DWORD0
no change in functionality
diff --git a/src/r600_shader.c b/src/r600_shader.c
index e78aa32..7e25f6d 100644
--- a/src/r600_shader.c
+++ b/src/r600_shader.c
@@ -1403,7 +1403,7 @@ int R600_comp_vs(RADEONChipFamily ChipSet, uint32_t* shader)
WHOLE_QUAD_MODE(0),
BARRIER(0));
/* 2 */
- shader[i++] = CF_DWORD0(0);
+ shader[i++] = CF_DWORD0(ADDR(0));
shader[i++] = CF_DWORD1(POP_COUNT(0),
CF_CONST(0),
COND(SQ_CF_COND_ACTIVE),
commit 801e83227a59a29eea425ea612083bbf2b536c30
Author: Wolfram <bugzilla1 at malloc.de>
Date: Mon Jun 21 18:59:19 2010 -0400
r6xx/r7xx: fix ums cmd buffer leak
Fixes:
https://bugs.freedesktop.org/show_bug.cgi?id=27957
diff --git a/src/r6xx_accel.c b/src/r6xx_accel.c
index c8ef451..0edfe8b 100644
--- a/src/r6xx_accel.c
+++ b/src/r6xx_accel.c
@@ -1283,6 +1283,8 @@ void r600_vb_no_space(ScrnInfoPtr pScrn, int vert_size)
}
#endif
- r600_finish_op(pScrn, vert_size);
- r600_cp_start(pScrn);
+ if (accel_state->vb_start_op != -1) {
+ r600_finish_op(pScrn, vert_size);
+ r600_cp_start(pScrn);
+ }
}
commit b13d719080b75fc6db4d15d2d323b8fce8b7ad06
Author: Alex Deucher <alexdeucher at gmail.com>
Date: Mon Jun 21 18:49:44 2010 -0400
r6xx/r7xx: fix miscount in state emit
diff --git a/src/r6xx_accel.c b/src/r6xx_accel.c
index 603b271..c8ef451 100644
--- a/src/r6xx_accel.c
+++ b/src/r6xx_accel.c
@@ -979,7 +979,7 @@ set_default_state(ScrnInfoPtr pScrn, drmBufPtr ib)
for (i = 0; i < PA_SC_VPORT_SCISSOR_0_TL_num; i++)
set_vport_scissor (pScrn, ib, i, 0, 0, 8192, 8192);
- BEGIN_BATCH(40);
+ BEGIN_BATCH(42);
PACK0(ib, PA_SC_MPASS_PS_CNTL, 2);
E32(ib, 0);
if (info->ChipFamily < CHIP_FAMILY_RV770)
commit c3c5c8e2cc91b51a24effdffb85281216eed731d
Author: Alex Deucher <alexdeucher at gmail.com>
Date: Mon Jun 21 14:30:17 2010 -0400
r6xx/r7xx accel: add back some additional default state
This adds back everything removed in c29157bbf5b0dd26857675282ab094082fbaed0d
except CB_FOG_*, CB_CLEAR_* and the VPORT transforms. Those shouldn't
be needed as we aren't using fog or viewport transforms. We probably don't
need all the state that was added back either but I can't reproduce any
problems here, so it's hard to say which parts are problematic.
Should fix:
https://bugs.freedesktop.org/show_bug.cgi?id=28629
and several corruption reports on #radeon.
Signed-off-by: Alex Deucher <alexdeucher at gmail.com>
diff --git a/src/r6xx_accel.c b/src/r6xx_accel.c
index a0073ff..603b271 100644
--- a/src/r6xx_accel.c
+++ b/src/r6xx_accel.c
@@ -877,14 +877,50 @@ set_default_state(ScrnInfoPtr pScrn, drmBufPtr ib)
sq_setup(pScrn, ib, &sq_conf);
- BEGIN_BATCH(41);
+ BEGIN_BATCH(83);
+ if (info->ChipFamily < CHIP_FAMILY_RV770) {
+ EREG(ib, TA_CNTL_AUX, (( 3 << GRADIENT_CREDIT_shift) |
+ - (28 << TD_FIFO_CREDIT_shift)));
+ EREG(ib, VC_ENHANCE, 0);
+ EREG(ib, R7xx_SQ_DYN_GPR_CNTL_PS_FLUSH_REQ, 0);
+ EREG(ib, DB_DEBUG, 0x82000000); /* ? */
+ EREG(ib, DB_WATERMARKS, ((4 << DEPTH_FREE_shift) |
+ (16 << DEPTH_FLUSH_shift) |
+ (0 << FORCE_SUMMARIZE_shift) |
+ (4 << DEPTH_PENDING_FREE_shift) |
+ (16 << DEPTH_CACHELINE_FREE_shift) |
+ 0));
+ } else {
+ EREG(ib, TA_CNTL_AUX, (( 2 << GRADIENT_CREDIT_shift) |
+ - (28 << TD_FIFO_CREDIT_shift)));
+ EREG(ib, VC_ENHANCE, 0);
+ EREG(ib, R7xx_SQ_DYN_GPR_CNTL_PS_FLUSH_REQ, VS_PC_LIMIT_ENABLE_bit);
+ EREG(ib, DB_DEBUG, 0);
+ EREG(ib, DB_WATERMARKS, ((4 << DEPTH_FREE_shift) |
+ (16 << DEPTH_FLUSH_shift) |
+ (0 << FORCE_SUMMARIZE_shift) |
+ (4 << DEPTH_PENDING_FREE_shift) |
+ (4 << DEPTH_CACHELINE_FREE_shift) |
+ 0));
+ }
+
PACK0(ib, SQ_VTX_BASE_VTX_LOC, 2);
E32(ib, 0);
E32(ib, 0);
+ PACK0(ib, SQ_ESGS_RING_ITEMSIZE, 9);
+ E32(ib, 0); // SQ_ESGS_RING_ITEMSIZE
+ E32(ib, 0); // SQ_GSVS_RING_ITEMSIZE
+ E32(ib, 0); // SQ_ESTMP_RING_ITEMSIZE
+ E32(ib, 0); // SQ_GSTMP_RING_ITEMSIZE
+ E32(ib, 0); // SQ_VSTMP_RING_ITEMSIZE
+ E32(ib, 0); // SQ_PSTMP_RING_ITEMSIZE
+ E32(ib, 0); // SQ_FBUF_RING_ITEMSIZE
+ E32(ib, 0); // SQ_REDUC_RING_ITEMSIZE
+ E32(ib, 0); // SQ_GS_VERT_ITEMSIZE
+
// DB
EREG(ib, DB_DEPTH_INFO, 0);
-
EREG(ib, DB_DEPTH_CONTROL, 0);
PACK0(ib, DB_RENDER_CONTROL, 2);
E32(ib, STENCIL_COMPRESS_DISABLE_bit | DEPTH_COMPRESS_DISABLE_bit);
@@ -899,6 +935,15 @@ set_default_state(ScrnInfoPtr pScrn, drmBufPtr ib)
EREG(ib, DB_SHADER_CONTROL, ((1 << Z_ORDER_shift) | /* EARLY_Z_THEN_LATE_Z */
DUAL_EXPORT_ENABLE_bit)); /* Only useful if no depth export */
+ PACK0(ib, DB_STENCIL_CLEAR, 2);
+ E32(ib, 0); // DB_STENCIL_CLEAR
+ E32(ib, 0); // DB_DEPTH_CLEAR
+
+ PACK0(ib, DB_STENCILREFMASK, 3);
+ E32(ib, 0); // DB_STENCILREFMASK
+ E32(ib, 0); // DB_STENCILREFMASK_BF
+ E32(ib, 0); // SX_ALPHA_REF
+
PACK0(ib, CB_CLRCMP_CONTROL, 4);
E32(ib, 1 << CLRCMP_FCN_SEL_shift); // CB_CLRCMP_CONTROL: use CLRCMP_FCN_SRC
E32(ib, 0); // CB_CLRCMP_SRC
@@ -908,6 +953,13 @@ set_default_state(ScrnInfoPtr pScrn, drmBufPtr ib)
EREG(ib, CB_SHADER_MASK, OUTPUT0_ENABLE_mask);
EREG(ib, R7xx_CB_SHADER_CONTROL, (RT0_ENABLE_bit));
+ PACK0(ib, SX_ALPHA_TEST_CONTROL, 5);
+ E32(ib, 0); // SX_ALPHA_TEST_CONTROL
+ E32(ib, 0x00000000); // CB_BLEND_RED
+ E32(ib, 0x00000000); // CB_BLEND_GREEN
+ E32(ib, 0x00000000); // CB_BLEND_BLUE
+ E32(ib, 0x00000000); // CB_BLEND_ALPHA
+
EREG(ib, PA_SC_WINDOW_OFFSET, ((0 << WINDOW_X_OFFSET_shift) |
(0 << WINDOW_Y_OFFSET_shift)));
@@ -936,7 +988,7 @@ set_default_state(ScrnInfoPtr pScrn, drmBufPtr ib)
E32(ib, (FORCE_EOV_CNTDWN_ENABLE_bit | FORCE_EOV_REZ_ENABLE_bit |
0x00500000)); /* ? */
- PACK0(ib, PA_SC_LINE_CNTL, 7);
+ PACK0(ib, PA_SC_LINE_CNTL, 9);
E32(ib, 0); // PA_SC_LINE_CNTL
E32(ib, 0); // PA_SC_AA_CONFIG
E32(ib, ((2 << PA_SU_VTX_CNTL__ROUND_MODE_shift) | PIX_CENTER_bit | // PA_SU_VTX_CNTL
@@ -945,6 +997,8 @@ set_default_state(ScrnInfoPtr pScrn, drmBufPtr ib)
EFLOAT(ib, 1.0); // PA_CL_GB_VERT_DISC_ADJ
EFLOAT(ib, 1.0); // PA_CL_GB_HORZ_CLIP_ADJ
EFLOAT(ib, 1.0); // PA_CL_GB_HORZ_DISC_ADJ
+ E32(ib, 0); // PA_SC_AA_SAMPLE_LOCS_MCTX
+ E32(ib, 0); // PA_SC_AA_SAMPLE_LOCS_8S_WD1_M
EREG(ib, PA_SC_AA_MASK, 0xFFFFFFFF);
@@ -982,7 +1036,7 @@ set_default_state(ScrnInfoPtr pScrn, drmBufPtr ib)
fs_setup(pScrn, ib, &fs_conf, RADEON_GEM_DOMAIN_VRAM);
// VGT
- BEGIN_BATCH(39);
+ BEGIN_BATCH(43);
PACK0(ib, VGT_MAX_VTX_INDX, 4);
E32(ib, 2048); /* XXX set to a reasonably large number of indices */ // VGT_MAX_VTX_INDX
E32(ib, 0); // VGT_MIN_VTX_INDX
@@ -996,7 +1050,11 @@ set_default_state(ScrnInfoPtr pScrn, drmBufPtr ib)
E32(ib, 0); // VGT_INSTANCE_STEP_RATE_0
E32(ib, 0); // VGT_INSTANCE_STEP_RATE_1
- PACK0(ib, VGT_OUTPUT_PATH_CNTL, 13);
+ PACK0(ib, PA_SU_POINT_SIZE, 17);
+ E32(ib, 0); // PA_SU_POINT_SIZE
+ E32(ib, 0); // PA_SU_POINT_MINMAX
+ E32(ib, (8 << PA_SU_LINE_CNTL__WIDTH_shift)); /* Line width 1 pixel */ // PA_SU_LINE_CNTL
+ E32(ib, 0); // PA_SC_LINE_STIPPLE
E32(ib, 0); // VGT_OUTPUT_PATH_CNTL
E32(ib, 0); // VGT_HOS_CNTL
E32(ib, 0); // VGT_HOS_MAX_TESS_LEVEL
commit 800cb2088fec698d0626063a9ab198ff534938c0
Author: Michel Dänzer <daenzer at vmware.com>
Date: Mon Jun 21 08:15:14 2010 +0200
DRI2: Fix up confusion between windows and pixmaps.
Fixes crashes with xserver master, where looking up a pixmap private on a
window no longer happens to work.
diff --git a/src/radeon_dri2.c b/src/radeon_dri2.c
index 0ecdcd4..a0ed085 100644
--- a/src/radeon_dri2.c
+++ b/src/radeon_dri2.c
@@ -272,26 +272,28 @@ radeon_dri2_copy_region(DrawablePtr drawable,
struct dri2_buffer_priv *dst_private = dest_buffer->driverPrivate;
ScreenPtr pScreen = drawable->pScreen;
ScrnInfoPtr pScrn = xf86Screens[pScreen->myNum];
- PixmapPtr src_pixmap;
- PixmapPtr dst_pixmap;
+ DrawablePtr src_drawable;
+ DrawablePtr dst_drawable;
RegionPtr copy_clip;
GCPtr gc;
RADEONInfoPtr info = RADEONPTR(pScrn);
Bool vsync;
- src_pixmap = src_private->pixmap;
- dst_pixmap = dst_private->pixmap;
if (src_private->attachment == DRI2BufferFrontLeft) {
- src_pixmap = (PixmapPtr)drawable;
+ src_drawable = drawable;
+ } else {
+ src_drawable = &src_private->pixmap->drawable;
}
if (dst_private->attachment == DRI2BufferFrontLeft) {
- dst_pixmap = (PixmapPtr)drawable;
+ dst_drawable = drawable;
+ } else {
+ dst_drawable = &dst_private->pixmap->drawable;
}
- gc = GetScratchGC(drawable->depth, pScreen);
+ gc = GetScratchGC(dst_drawable->depth, pScreen);
copy_clip = REGION_CREATE(pScreen, NULL, 0);
REGION_COPY(pScreen, copy_clip, region);
(*gc->funcs->ChangeClip) (gc, CT_REGION, copy_clip, 0);
- ValidateGC(&dst_pixmap->drawable, gc);
+ ValidateGC(dst_drawable, gc);
/* If this is a full buffer swap or frontbuffer flush, throttle on the
* previous one
@@ -304,7 +306,7 @@ radeon_dri2_copy_region(DrawablePtr drawable,
extents->x2 == drawable->width &&
extents->y2 == drawable->height) {
struct radeon_exa_pixmap_priv *exa_priv =
- exaGetPixmapDriverPrivate(dst_pixmap);
+ exaGetPixmapDriverPrivate(dst_private->pixmap);
if (exa_priv && exa_priv->bo)
radeon_bo_wait(exa_priv->bo);
@@ -315,7 +317,7 @@ radeon_dri2_copy_region(DrawablePtr drawable,
vsync = info->accel_state->vsync;
info->accel_state->vsync = TRUE;
- (*gc->ops->CopyArea)(&src_pixmap->drawable, &dst_pixmap->drawable, gc,
+ (*gc->ops->CopyArea)(src_drawable, dst_drawable, gc,
0, 0, drawable->width, drawable->height, 0, 0);
info->accel_state->vsync = vsync;
commit f7a91ece264af9f3fd2fc18e99aefcda93ce9f5c
Author: Michel Dänzer <daenzer at vmware.com>
Date: Mon Jun 14 08:52:16 2010 +0200
Convert x(c)alloc/xfree to m/calloc/free.
Fixes deprecation warnings with xserver master and should also work with older
xservers.
diff --git a/src/drmmode_display.c b/src/drmmode_display.c
index c427bf1..1366b36 100644
--- a/src/drmmode_display.c
+++ b/src/drmmode_display.c
@@ -292,7 +292,7 @@ drmmode_set_mode_major(xf86CrtcPtr crtc, DisplayModePtr mode,
#endif
}
- output_ids = xcalloc(sizeof(uint32_t), xf86_config->num_output);
+ output_ids = calloc(sizeof(uint32_t), xf86_config->num_output);
if (!output_ids) {
ret = FALSE;
goto done;
@@ -649,15 +649,15 @@ drmmode_output_destroy(xf86OutputPtr output)
drmModeFreePropertyBlob(drmmode_output->edid_blob);
for (i = 0; i < drmmode_output->num_props; i++) {
drmModeFreeProperty(drmmode_output->props[i].mode_prop);
- xfree(drmmode_output->props[i].atoms);
+ free(drmmode_output->props[i].atoms);
}
for (i = 0; i < drmmode_output->mode_output->count_encoders; i++) {
drmModeFreeEncoder(drmmode_output->mode_encoders[i]);
- xfree(drmmode_output->mode_encoders);
+ free(drmmode_output->mode_encoders);
}
- xfree(drmmode_output->props);
+ free(drmmode_output->props);
drmModeFreeConnector(drmmode_output->mode_output);
- xfree(drmmode_output);
+ free(drmmode_output);
output->driver_private = NULL;
}
@@ -699,7 +699,7 @@ drmmode_output_create_resources(xf86OutputPtr output)
drmModePropertyPtr drmmode_prop;
int i, j, err;
- drmmode_output->props = xcalloc(mode_output->count_props, sizeof(drmmode_prop_rec));
+ drmmode_output->props = calloc(mode_output->count_props, sizeof(drmmode_prop_rec));
if (!drmmode_output->props)
return;
@@ -725,7 +725,7 @@ drmmode_output_create_resources(xf86OutputPtr output)
INT32 value = p->value;
p->num_atoms = 1;
- p->atoms = xcalloc(p->num_atoms, sizeof(Atom));
+ p->atoms = calloc(p->num_atoms, sizeof(Atom));
if (!p->atoms)
continue;
p->atoms[0] = MakeAtom(drmmode_prop->name, strlen(drmmode_prop->name), TRUE);
@@ -747,7 +747,7 @@ drmmode_output_create_resources(xf86OutputPtr output)
}
} else if (drmmode_prop->flags & DRM_MODE_PROP_ENUM) {
p->num_atoms = drmmode_prop->count_enums + 1;
- p->atoms = xcalloc(p->num_atoms, sizeof(Atom));
+ p->atoms = calloc(p->num_atoms, sizeof(Atom));
if (!p->atoms)
continue;
p->atoms[0] = MakeAtom(drmmode_prop->name, strlen(drmmode_prop->name), TRUE);
@@ -896,7 +896,7 @@ drmmode_output_init(ScrnInfoPtr pScrn, drmmode_ptr drmmode, int num)
if (!koutput)
return;
- kencoders = xcalloc(sizeof(drmModeEncoderPtr), koutput->count_encoders);
+ kencoders = calloc(sizeof(drmModeEncoderPtr), koutput->count_encoders);
if (!kencoders) {
goto out_free_encoders;
}
@@ -945,7 +945,7 @@ drmmode_output_init(ScrnInfoPtr pScrn, drmmode_ptr drmmode, int num)
goto out_free_encoders;
}
- drmmode_output = xcalloc(sizeof(drmmode_output_private_rec), 1);
+ drmmode_output = calloc(sizeof(drmmode_output_private_rec), 1);
if (!drmmode_output) {
xf86OutputDestroy(output);
goto out_free_encoders;
@@ -985,7 +985,7 @@ out_free_encoders:
if (kencoders){
for (i = 0; i < koutput->count_encoders; i++)
drmModeFreeEncoder(kencoders[i]);
- xfree(kencoders);
+ free(kencoders);
}
drmModeFreeConnector(koutput);
@@ -1130,10 +1130,10 @@ drmmode_xf86crtc_resize (ScrnInfoPtr scrn, int width, int height)
} else {
if (radeon_bo_map(info->front_bo, 1))
goto fail;
- fb_shadow = xcalloc(1, screen_size);
+ fb_shadow = calloc(1, screen_size);
if (fb_shadow == NULL)
goto fail;
- xfree(info->fb_shadow);
+ free(info->fb_shadow);
info->fb_shadow = fb_shadow;
screen->ModifyPixmapHeader(screen->GetScreenPixmap(screen),
width, height, -1, -1, pitch * cpp,
diff --git a/src/legacy_output.c b/src/legacy_output.c
index fe0fbe3..670f1ba 100644
--- a/src/legacy_output.c
+++ b/src/legacy_output.c
@@ -165,7 +165,7 @@ RADEONGetExtTMDSInfo(ScrnInfoPtr pScrn, radeon_dvo_ptr dvo)
dvo->DVOChip =
RADEONDVODeviceInit(dvo->pI2CBus, dvo->dvo_i2c_slave_addr);
if (!dvo->DVOChip)
- xfree(dvo->pI2CBus);
+ free(dvo->pI2CBus);
}
}
}
@@ -442,7 +442,7 @@ RADEONDVODeviceInit(I2CBusPtr b, I2CSlaveAddr addr)
{
I2CDevPtr dvo;
- dvo = xcalloc(1, sizeof(I2CDevRec));
+ dvo = calloc(1, sizeof(I2CDevRec));
if (dvo == NULL)
return NULL;
@@ -458,7 +458,7 @@ RADEONDVODeviceInit(I2CBusPtr b, I2CSlaveAddr addr)
return dvo;
}
- xfree(dvo);
+ free(dvo);
return NULL;
}
diff --git a/src/r600_exa.c b/src/r600_exa.c
index 26b59d8..b1c024a 100644
--- a/src/r600_exa.c
+++ b/src/r600_exa.c
@@ -2360,7 +2360,7 @@ R600DrawInit(ScreenPtr pScreen)
info->accel_state->vsync = FALSE;
if (!exaDriverInit(pScreen, info->accel_state->exa)) {
- xfree(info->accel_state->exa);
+ free(info->accel_state->exa);
return FALSE;
}
diff --git a/src/radeon_accelfuncs.c b/src/radeon_accelfuncs.c
index 36f25e7..d0bead3 100644
--- a/src/radeon_accelfuncs.c
+++ b/src/radeon_accelfuncs.c
@@ -1206,7 +1206,7 @@ FUNC_NAME(RADEONAccelInit)(ScreenPtr pScreen, XAAInfoRecPtr a)
a->ScanlineColorExpandBuffers = info->accel_state->scratch_buffer;
if (!info->accel_state->scratch_save)
info->accel_state->scratch_save
- = xalloc(((pScrn->virtualX+31)/32*4)
+ = malloc(((pScrn->virtualX+31)/32*4)
+ (pScrn->virtualX * info->CurrentLayout.pixel_bytes));
info->accel_state->scratch_buffer[0] = info->accel_state->scratch_save;
a->SetupForScanlineCPUToScreenColorExpandFill
diff --git a/src/radeon_atombios.c b/src/radeon_atombios.c
index 30dbaf6..996e6ee 100644
--- a/src/radeon_atombios.c
+++ b/src/radeon_atombios.c
@@ -490,7 +490,7 @@ rhdAtomAllocateFbScratch(atomBiosHandlePtr handle,
xf86DrvMsg(handle->scrnIndex, X_INFO,
"Cannot get VRAM scratch space. "
"Allocating in main memory instead\n");
- handle->scratchBase = xcalloc(fb_size,1);
+ handle->scratchBase = calloc(fb_size,1);
return ATOM_SUCCESS;
}
return ATOM_FAILED;
@@ -651,14 +651,14 @@ rhdAtomInit(atomBiosHandlePtr unused1, AtomBiosRequestID unused2,
BIOSImageSize = RADEON_VBIOS_SIZE;
#endif
- if (!(atomDataPtr = xcalloc(1, sizeof(atomDataTables)))) {
+ if (!(atomDataPtr = calloc(1, sizeof(atomDataTables)))) {
xf86DrvMsg(scrnIndex,X_ERROR,"Cannot allocate memory for "
"ATOM BIOS data tabes\n");
goto error;
}
if (!rhdAtomGetDataTable(scrnIndex, info->VBIOS, atomDataPtr, &cmd_offset, BIOSImageSize))
goto error1;
- if (!(handle = xcalloc(1, sizeof(atomBiosHandleRec)))) {
+ if (!(handle = calloc(1, sizeof(atomBiosHandleRec)))) {
xf86DrvMsg(scrnIndex,X_ERROR,"Cannot allocate memory\n");
goto error1;
}
@@ -677,7 +677,7 @@ rhdAtomInit(atomBiosHandlePtr unused1, AtomBiosRequestID unused2,
return ATOM_SUCCESS;
error1:
- xfree(atomDataPtr);
+ free(atomDataPtr);
error:
return ATOM_FAILED;
}
@@ -688,10 +688,10 @@ rhdAtomTearDown(atomBiosHandlePtr handle,
{
//RHDFUNC(handle);
- xfree(handle->BIOSBase);
- xfree(handle->atomDataPtr);
- if (handle->scratchBase) xfree(handle->scratchBase);
- xfree(handle);
+ free(handle->BIOSBase);
+ free(handle->atomDataPtr);
+ if (handle->scratchBase) free(handle->scratchBase);
+ free(handle);
return ATOM_SUCCESS;
}
@@ -777,7 +777,7 @@ rhdAtomDTDTimings(atomBiosHandlePtr handle, ATOM_DTD_FORMAT *dtd)
if (!dtd->usHActive || !dtd->usVActive)
return NULL;
- if (!(mode = (DisplayModePtr)xcalloc(1,sizeof(DisplayModeRec))))
+ if (!(mode = (DisplayModePtr)calloc(1,sizeof(DisplayModeRec))))
return NULL;
mode->CrtcHDisplay = mode->HDisplay = le16_to_cpu(dtd->usHActive);
@@ -861,7 +861,7 @@ rhdAtomLvdsDDC(atomBiosHandlePtr handle, uint32_t offset, unsigned char *record)
- sizeof(UCHAR);
if (offset > handle->BIOSImageSize) break;
/* dup string as we free it later */
- if (!(EDIDBlock = (unsigned char *)xalloc(
+ if (!(EDIDBlock = (unsigned char *)malloc(
((ATOM_FAKE_EDID_PATCH_RECORD*)record)->ucFakeEDIDLength)))
return NULL;
memcpy(EDIDBlock,&((ATOM_FAKE_EDID_PATCH_RECORD*)record)->ucFakeEDIDString,
@@ -871,7 +871,7 @@ rhdAtomLvdsDDC(atomBiosHandlePtr handle, uint32_t offset, unsigned char *record)
{
xf86MonPtr mon = xf86InterpretEDID(handle->scrnIndex,EDIDBlock);
xf86PrintEDID(mon);
- xfree(mon);
+ free(mon);
}
return EDIDBlock;
@@ -1802,9 +1802,9 @@ radeon_add_encoder(ScrnInfoPtr pScrn, uint32_t encoder_id, uint32_t device_suppo
if (device_support & ATOM_DEVICE_LCD1_SUPPORT) {
if (info->encoders[device_index]->dev_priv == NULL) {
info->encoders[device_index]->dev_priv =
- (radeon_lvds_ptr)xcalloc(1,sizeof(radeon_lvds_rec));
+ (radeon_lvds_ptr)calloc(1,sizeof(radeon_lvds_rec));
if (info->encoders[device_index]->dev_priv == NULL) {
- ErrorF("xalloc failed\n");
+ ErrorF("calloc failed\n");
return FALSE;
} else
RADEONGetATOMLVDSInfo(pScrn, (radeon_lvds_ptr)info->encoders[device_index]->dev_priv);
@@ -1816,7 +1816,7 @@ radeon_add_encoder(ScrnInfoPtr pScrn, uint32_t encoder_id, uint32_t device_suppo
}
}
- info->encoders[device_index] = (radeon_encoder_ptr)xcalloc(1,sizeof(radeon_encoder_rec));
+ info->encoders[device_index] = (radeon_encoder_ptr)calloc(1,sizeof(radeon_encoder_rec));
if (info->encoders[device_index] != NULL) {
info->encoders[device_index]->encoder_id = encoder_id;
info->encoders[device_index]->devices = 0;
@@ -1824,9 +1824,9 @@ radeon_add_encoder(ScrnInfoPtr pScrn, uint32_t encoder_id, uint32_t device_suppo
// add dev_priv stuff
switch (encoder_id) {
case ENCODER_OBJECT_ID_INTERNAL_LVDS:
- info->encoders[device_index]->dev_priv = (radeon_lvds_ptr)xcalloc(1,sizeof(radeon_lvds_rec));
+ info->encoders[device_index]->dev_priv = (radeon_lvds_ptr)calloc(1,sizeof(radeon_lvds_rec));
if (info->encoders[device_index]->dev_priv == NULL) {
- ErrorF("xalloc failed\n");
+ ErrorF("calloc failed\n");
return FALSE;
} else {
if (info->IsAtomBios)
@@ -1837,9 +1837,9 @@ radeon_add_encoder(ScrnInfoPtr pScrn, uint32_t encoder_id, uint32_t device_suppo
break;
case ENCODER_OBJECT_ID_INTERNAL_DAC2:
if (!IS_AVIVO_VARIANT) {
- info->encoders[device_index]->dev_priv = (radeon_tvdac_ptr)xcalloc(1,sizeof(radeon_tvdac_rec));
+ info->encoders[device_index]->dev_priv = (radeon_tvdac_ptr)calloc(1,sizeof(radeon_tvdac_rec));
if (info->encoders[device_index]->dev_priv == NULL) {
- ErrorF("xalloc failed\n");
+ ErrorF("calloc failed\n");
return FALSE;
} else
RADEONGetTVDacAdjInfo(pScrn, (radeon_tvdac_ptr)info->encoders[device_index]->dev_priv);
@@ -1847,9 +1847,9 @@ radeon_add_encoder(ScrnInfoPtr pScrn, uint32_t encoder_id, uint32_t device_suppo
break;
case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
if (!IS_AVIVO_VARIANT) {
- info->encoders[device_index]->dev_priv = (radeon_tmds_ptr)xcalloc(1,sizeof(radeon_tmds_rec));
+ info->encoders[device_index]->dev_priv = (radeon_tmds_ptr)calloc(1,sizeof(radeon_tmds_rec));
if (info->encoders[device_index]->dev_priv == NULL) {
- ErrorF("xalloc failed\n");
+ ErrorF("calloc failed\n");
return FALSE;
} else
RADEONGetTMDSInfo(pScrn, (radeon_tmds_ptr)info->encoders[device_index]->dev_priv);
@@ -1857,9 +1857,9 @@ radeon_add_encoder(ScrnInfoPtr pScrn, uint32_t encoder_id, uint32_t device_suppo
break;
case ENCODER_OBJECT_ID_INTERNAL_DVO1:
if (!IS_AVIVO_VARIANT) {
- info->encoders[device_index]->dev_priv = (radeon_dvo_ptr)xcalloc(1,sizeof(radeon_dvo_rec));
+ info->encoders[device_index]->dev_priv = (radeon_dvo_ptr)calloc(1,sizeof(radeon_dvo_rec));
if (info->encoders[device_index]->dev_priv == NULL) {
- ErrorF("xalloc failed\n");
+ ErrorF("calloc failed\n");
return FALSE;
} else
RADEONGetExtTMDSInfo(pScrn, (radeon_dvo_ptr)info->encoders[device_index]->dev_priv);
@@ -1871,9 +1871,9 @@ radeon_add_encoder(ScrnInfoPtr pScrn, uint32_t encoder_id, uint32_t device_suppo
case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
if (device_support & ATOM_DEVICE_LCD1_SUPPORT) {
- info->encoders[device_index]->dev_priv = (radeon_lvds_ptr)xcalloc(1,sizeof(radeon_lvds_rec));
+ info->encoders[device_index]->dev_priv = (radeon_lvds_ptr)calloc(1,sizeof(radeon_lvds_rec));
if (info->encoders[device_index]->dev_priv == NULL) {
- ErrorF("xalloc failed\n");
+ ErrorF("calloc failed\n");
return FALSE;
} else
RADEONGetATOMLVDSInfo(pScrn, (radeon_lvds_ptr)info->encoders[device_index]->dev_priv);
@@ -1882,7 +1882,7 @@ radeon_add_encoder(ScrnInfoPtr pScrn, uint32_t encoder_id, uint32_t device_suppo
}
return TRUE;
} else {
- ErrorF("xalloc failed\n");
+ ErrorF("calloc failed\n");
return FALSE;
}
}
diff --git a/src/radeon_bios.c b/src/radeon_bios.c
index d066edc..7d615c0 100644
--- a/src/radeon_bios.c
+++ b/src/radeon_bios.c
@@ -361,9 +361,9 @@ RADEONGetBIOSInfo(ScrnInfoPtr pScrn, xf86Int10InfoPtr pInt10)
#ifdef XSERVER_LIBPCIACCESS
int size = info->PciInfo->rom_size > RADEON_VBIOS_SIZE ? info->PciInfo->rom_size : RADEON_VBIOS_SIZE;
- info->VBIOS = xalloc(size);
+ info->VBIOS = malloc(size);
#else
- info->VBIOS = xalloc(RADEON_VBIOS_SIZE);
+ info->VBIOS = malloc(RADEON_VBIOS_SIZE);
#endif
if (!info->VBIOS) {
xf86DrvMsg(pScrn->scrnIndex, X_ERROR,
@@ -381,7 +381,7 @@ RADEONGetBIOSInfo(ScrnInfoPtr pScrn, xf86Int10InfoPtr pInt10)
if (info->VBIOS[0] != 0x55 || info->VBIOS[1] != 0xaa) {
xf86DrvMsg(pScrn->scrnIndex, X_WARNING,
"Unrecognized BIOS signature, BIOS data will not be used\n");
- xfree (info->VBIOS);
+ free (info->VBIOS);
info->VBIOS = NULL;
return FALSE;
}
@@ -396,7 +396,7 @@ RADEONGetBIOSInfo(ScrnInfoPtr pScrn, xf86Int10InfoPtr pInt10)
else if (info->VBIOS[dptr + 0x14] != 0x0) {
xf86DrvMsg(pScrn->scrnIndex, X_WARNING,
"Not an x86 BIOS ROM image, BIOS data will not be used\n");
- xfree (info->VBIOS);
+ free (info->VBIOS);
info->VBIOS = NULL;
return FALSE;
}
@@ -406,7 +406,7 @@ RADEONGetBIOSInfo(ScrnInfoPtr pScrn, xf86Int10InfoPtr pInt10)
if(!info->ROMHeaderStart) {
xf86DrvMsg(pScrn->scrnIndex, X_WARNING,
"Invalid ROM pointer, BIOS data will not be used\n");
- xfree (info->VBIOS);
+ free (info->VBIOS);
info->VBIOS = NULL;
return FALSE;
}
diff --git a/src/radeon_crtc.c b/src/radeon_crtc.c
index bc23ee5..5f4a0a7 100644
--- a/src/radeon_crtc.c
+++ b/src/radeon_crtc.c
@@ -866,7 +866,7 @@ Bool RADEONAllocateControllers(ScrnInfoPtr pScrn, int mask)
pRADEONEnt->Controller[1] = xnfcalloc(sizeof(RADEONCrtcPrivateRec), 1);
if (!pRADEONEnt->Controller[1])
{
- xfree(pRADEONEnt->Controller[0]);
+ free(pRADEONEnt->Controller[0]);
return FALSE;
}
@@ -894,7 +894,7 @@ Bool RADEONAllocateControllers(ScrnInfoPtr pScrn, int mask)
pRADEONEnt->Controller[i] = xnfcalloc(sizeof(RADEONCrtcPrivateRec), 1);
if (!pRADEONEnt->Controller[i])
{
- xfree(pRADEONEnt->Controller[i]);
+ free(pRADEONEnt->Controller[i]);
return FALSE;
}
diff --git a/src/radeon_dri.c b/src/radeon_dri.c
index 6d12435..ed167ed 100644
--- a/src/radeon_dri.c
+++ b/src/radeon_dri.c
@@ -122,21 +122,21 @@ static Bool RADEONInitVisualConfigs(ScreenPtr pScreen)
if (use_db) numConfigs *= 2;
if (!(pConfigs
- = (__GLXvisualConfig *)xcalloc(sizeof(__GLXvisualConfig),
- numConfigs))) {
+ = (__GLXvisualConfig *)calloc(sizeof(__GLXvisualConfig),
+ numConfigs))) {
return FALSE;
}
if (!(pRADEONConfigs
- = (RADEONConfigPrivPtr)xcalloc(sizeof(RADEONConfigPrivRec),
- numConfigs))) {
- xfree(pConfigs);
+ = (RADEONConfigPrivPtr)calloc(sizeof(RADEONConfigPrivRec),
+ numConfigs))) {
+ free(pConfigs);
return FALSE;
}
if (!(pRADEONConfigPtrs
- = (RADEONConfigPrivPtr *)xcalloc(sizeof(RADEONConfigPrivPtr),
- numConfigs))) {
- xfree(pConfigs);
- xfree(pRADEONConfigs);
+ = (RADEONConfigPrivPtr *)calloc(sizeof(RADEONConfigPrivPtr),
+ numConfigs))) {
+ free(pConfigs);
+ free(pRADEONConfigs);
return FALSE;
}
@@ -208,21 +208,21 @@ static Bool RADEONInitVisualConfigs(ScreenPtr pScreen)
if (use_db) numConfigs *= 2;
if (!(pConfigs
- = (__GLXvisualConfig *)xcalloc(sizeof(__GLXvisualConfig),
- numConfigs))) {
+ = (__GLXvisualConfig *)calloc(sizeof(__GLXvisualConfig),
+ numConfigs))) {
return FALSE;
}
if (!(pRADEONConfigs
- = (RADEONConfigPrivPtr)xcalloc(sizeof(RADEONConfigPrivRec),
- numConfigs))) {
- xfree(pConfigs);
+ = (RADEONConfigPrivPtr)calloc(sizeof(RADEONConfigPrivRec),
+ numConfigs))) {
+ free(pConfigs);
return FALSE;
}
if (!(pRADEONConfigPtrs
- = (RADEONConfigPrivPtr *)xcalloc(sizeof(RADEONConfigPrivPtr),
- numConfigs))) {
- xfree(pConfigs);
- xfree(pRADEONConfigs);
+ = (RADEONConfigPrivPtr *)calloc(sizeof(RADEONConfigPrivPtr),
+ numConfigs))) {
+ free(pConfigs);
+ free(pRADEONConfigs);
return FALSE;
}
@@ -523,12 +523,12 @@ static void RADEONDRIMoveBuffers(WindowPtr pParent, DDXPointRec ptOldOrg,
if (nbox > 1) {
/* Keep ordering in each band, reverse order of bands */
- pboxNew1 = (BoxPtr)xalloc(sizeof(BoxRec)*nbox);
+ pboxNew1 = (BoxPtr)malloc(sizeof(BoxRec)*nbox);
if (!pboxNew1) return;
- pptNew1 = (DDXPointPtr)xalloc(sizeof(DDXPointRec)*nbox);
+ pptNew1 = (DDXPointPtr)malloc(sizeof(DDXPointRec)*nbox);
if (!pptNew1) {
- xfree(pboxNew1);
+ free(pboxNew1);
return;
}
@@ -565,14 +565,14 @@ static void RADEONDRIMoveBuffers(WindowPtr pParent, DDXPointRec ptOldOrg,
if (nbox > 1) {
/* reverse order of rects in each band */
- pboxNew2 = (BoxPtr)xalloc(sizeof(BoxRec)*nbox);
- pptNew2 = (DDXPointPtr)xalloc(sizeof(DDXPointRec)*nbox);
+ pboxNew2 = (BoxPtr)malloc(sizeof(BoxRec)*nbox);
+ pptNew2 = (DDXPointPtr)malloc(sizeof(DDXPointRec)*nbox);
if (!pboxNew2 || !pptNew2) {
- xfree(pptNew2);
- xfree(pboxNew2);
- xfree(pptNew1);
- xfree(pboxNew1);
+ free(pptNew2);
+ free(pboxNew2);
+ free(pptNew1);
+ free(pboxNew1);
return;
}
@@ -643,10 +643,10 @@ static void RADEONDRIMoveBuffers(WindowPtr pParent, DDXPointRec ptOldOrg,
info->accel_state->dst_pitch_offset = info->dri->frontPitchOffset;;
- xfree(pptNew2);
- xfree(pboxNew2);
- xfree(pptNew1);
- xfree(pboxNew1);
+ free(pptNew2);
+ free(pboxNew2);
+ free(pptNew1);
+ free(pboxNew1);
info->accel_state->accel->NeedToSync = TRUE;
#endif /* USE_XAA */
@@ -1410,7 +1410,7 @@ Bool RADEONDRIGetVersion(ScrnInfoPtr pScrn)
if (xf86LoaderCheckSymbol("DRICreatePCIBusID")) {
busId = DRICreatePCIBusID(info->PciInfo);
} else {
- busId = xalloc(64);
+ busId = malloc(64);
sprintf(busId,
"PCI:%d:%d:%d",
PCI_DEV_BUS(info->PciInfo),
@@ -1420,7 +1420,7 @@ Bool RADEONDRIGetVersion(ScrnInfoPtr pScrn)
/* Low level DRM open */
fd = drmOpen(RADEON_DRIVER_NAME, busId);
- xfree(busId);
+ free(busId);
if (fd < 0) {
xf86DrvMsg(pScrn->scrnIndex, X_ERROR,
"[dri] RADEONDRIGetVersion failed to open the DRM\n"
@@ -1557,7 +1557,7 @@ Bool RADEONDRIScreenInit(ScreenPtr pScreen)
if (xf86LoaderCheckSymbol("DRICreatePCIBusID")) {
pDRIInfo->busIdString = DRICreatePCIBusID(info->PciInfo);
} else {
- pDRIInfo->busIdString = xalloc(64);
+ pDRIInfo->busIdString = malloc(64);
sprintf(pDRIInfo->busIdString,
"PCI:%d:%d:%d",
PCI_DEV_BUS(info->PciInfo),
@@ -1598,7 +1598,7 @@ Bool RADEONDRIScreenInit(ScreenPtr pScreen)
pDRIInfo->SAREASize = SAREA_MAX;
#endif
- if (!(pRADEONDRI = (RADEONDRIPtr)xcalloc(sizeof(RADEONDRIRec),1))) {
+ if (!(pRADEONDRI = (RADEONDRIPtr)calloc(sizeof(RADEONDRIRec),1))) {
DRIDestroyInfoRec(info->dri->pDRIInfo);
info->dri->pDRIInfo = NULL;
return FALSE;
@@ -1645,7 +1645,7 @@ Bool RADEONDRIScreenInit(ScreenPtr pScreen)
if (!DRIScreenInit(pScreen, pDRIInfo, &info->dri->drmFD)) {
xf86DrvMsg(pScreen->myNum, X_ERROR,
"[dri] DRIScreenInit failed. Disabling DRI.\n");
- xfree(pDRIInfo->devPrivate);
+ free(pDRIInfo->devPrivate);
pDRIInfo->devPrivate = NULL;
DRIDestroyInfoRec(pDRIInfo);
pDRIInfo = NULL;
@@ -1934,7 +1934,7 @@ void RADEONDRICloseScreen(ScreenPtr pScreen)
}
if (info->dri->pciGartBackup) {
- xfree(info->dri->pciGartBackup);
+ free(info->dri->pciGartBackup);
info->dri->pciGartBackup = NULL;
}
@@ -1944,18 +1944,18 @@ void RADEONDRICloseScreen(ScreenPtr pScreen)
/* De-allocate all DRI data structures */
if (info->dri->pDRIInfo) {
if (info->dri->pDRIInfo->devPrivate) {
- xfree(info->dri->pDRIInfo->devPrivate);
+ free(info->dri->pDRIInfo->devPrivate);
info->dri->pDRIInfo->devPrivate = NULL;
}
DRIDestroyInfoRec(info->dri->pDRIInfo);
info->dri->pDRIInfo = NULL;
}
if (info->dri->pVisualConfigs) {
- xfree(info->dri->pVisualConfigs);
+ free(info->dri->pVisualConfigs);
info->dri->pVisualConfigs = NULL;
}
if (info->dri->pVisualConfigsPriv) {
- xfree(info->dri->pVisualConfigsPriv);
+ free(info->dri->pVisualConfigsPriv);
info->dri->pVisualConfigsPriv = NULL;
}
}
diff --git a/src/radeon_dri2.c b/src/radeon_dri2.c
index 7d5205e..0ecdcd4 100644
--- a/src/radeon_dri2.c
+++ b/src/radeon_dri2.c
@@ -74,13 +74,13 @@ radeon_dri2_create_buffers(DrawablePtr drawable,
int i, r;
int flags = 0;
- buffers = xcalloc(count, sizeof *buffers);
+ buffers = calloc(count, sizeof *buffers);
if (buffers == NULL) {
return NULL;
}
- privates = xcalloc(count, sizeof(struct dri2_buffer_priv));
+ privates = calloc(count, sizeof(struct dri2_buffer_priv));
if (privates == NULL) {
- xfree(buffers);
+ free(buffers);
return NULL;
}
@@ -156,13 +156,13 @@ radeon_dri2_create_buffer(DrawablePtr drawable,
int r;
int flags;
- buffers = xcalloc(1, sizeof *buffers);
+ buffers = calloc(1, sizeof *buffers);
if (buffers == NULL) {
return NULL;
}
- privates = xcalloc(1, sizeof(struct dri2_buffer_priv));
+ privates = calloc(1, sizeof(struct dri2_buffer_priv));
if (privates == NULL) {
- xfree(buffers);
+ free(buffers);
return NULL;
}
@@ -240,8 +240,8 @@ radeon_dri2_destroy_buffers(DrawablePtr drawable,
(*pScreen->DestroyPixmap)(private->pixmap);
}
if (buffers) {
- xfree(buffers[0].driverPrivate);
- xfree(buffers);
+ free(buffers[0].driverPrivate);
+ free(buffers);
}
}
#else
@@ -256,8 +256,8 @@ radeon_dri2_destroy_buffer(DrawablePtr drawable, BufferPtr buffers)
private = buffers->driverPrivate;
(*pScreen->DestroyPixmap)(private->pixmap);
- xfree(buffers->driverPrivate);
- xfree(buffers);
+ free(buffers->driverPrivate);
+ free(buffers);
}
}
#endif
@@ -361,7 +361,7 @@ void radeon_dri2_frame_event_handler(unsigned int frame, unsigned int tv_sec,
status = dixLookupDrawable(&drawable, event->drawable_id, serverClient,
M_ANY, DixWriteAccess);
if (status != Success) {
- xfree(event);
+ free(event);
return;
}
@@ -392,7 +392,7 @@ void radeon_dri2_frame_event_handler(unsigned int frame, unsigned int tv_sec,
break;
}
- xfree(event);
+ free(event);
}
static int radeon_dri2_drawable_crtc(DrawablePtr pDraw)
@@ -480,7 +480,7 @@ static int radeon_dri2_schedule_wait_msc(ClientPtr client, DrawablePtr draw,
if (crtc == -1)
goto out_complete;
- wait_info = xcalloc(1, sizeof(DRI2FrameEventRec));
+ wait_info = calloc(1, sizeof(DRI2FrameEventRec));
if (!wait_info)
goto out_complete;
@@ -614,7 +614,7 @@ static int radeon_dri2_schedule_swap(ClientPtr client, DrawablePtr draw,
divisor &= 0xffffffff;
remainder &= 0xffffffff;
- swap_info = xcalloc(1, sizeof(DRI2FrameEventRec));
+ swap_info = calloc(1, sizeof(DRI2FrameEventRec));
/* Drawable not displayed... just complete the swap */
if (crtc == -1 || !swap_info)
@@ -749,7 +749,7 @@ blit_fallback:
DRI2SwapComplete(client, draw, 0, 0, 0, DRI2_BLIT_COMPLETE, func, data);
if (swap_info)
- xfree(swap_info);
+ free(swap_info);
*target_msc = 0; /* offscreen, so zero out target vblank count */
return TRUE;
}
diff --git a/src/radeon_driver.c b/src/radeon_driver.c
index 7167ea0..2b7be55 100644
--- a/src/radeon_driver.c
+++ b/src/radeon_driver.c
@@ -368,32 +368,32 @@ void RADEONFreeRec(ScrnInfoPtr pScrn)
info = RADEONPTR(pScrn);
if (info->cp) {
- xfree(info->cp);
+ free(info->cp);
info->cp = NULL;
}
if (info->dri) {
- xfree(info->dri);
+ free(info->dri);
info->dri = NULL;
}
if (info->accel_state) {
- xfree(info->accel_state);
+ free(info->accel_state);
info->accel_state = NULL;
}
for (i = 0; i < RADEON_MAX_BIOS_CONNECTOR; i++) {
if (info->encoders[i]) {
if (info->encoders[i]->dev_priv) {
- xfree(info->encoders[i]->dev_priv);
+ free(info->encoders[i]->dev_priv);
info->encoders[i]->dev_priv = NULL;
}
- xfree(info->encoders[i]);
+ free(info->encoders[i]);
info->encoders[i]= NULL;
}
}
- xfree(pScrn->driverPrivate);
+ free(pScrn->driverPrivate);
pScrn->driverPrivate = NULL;
}
@@ -2158,7 +2158,7 @@ static Bool RADEONPreInitAccel(ScrnInfoPtr pScrn)
int maxy = info->FbMapSize / (pScrn->displayWidth * info->CurrentLayout.pixel_bytes);
#endif
- if (!(info->accel_state = xcalloc(1, sizeof(struct radeon_accel_state)))) {
+ if (!(info->accel_state = calloc(1, sizeof(struct radeon_accel_state)))) {
xf86DrvMsg(pScrn->scrnIndex, X_ERROR, "Unable to allocate accel_state rec!\n");
return FALSE;
}
@@ -2329,12 +2329,12 @@ static Bool RADEONPreInitDRI(ScrnInfoPtr pScrn)
info->directRenderingEnabled = FALSE;
info->directRenderingInited = FALSE;
- if (!(info->dri = xcalloc(1, sizeof(struct radeon_dri)))) {
+ if (!(info->dri = calloc(1, sizeof(struct radeon_dri)))) {
xf86DrvMsg(pScrn->scrnIndex, X_ERROR,"Unable to allocate dri rec!\n");
return FALSE;
}
- if (!(info->cp = xcalloc(1, sizeof(struct radeon_cp)))) {
+ if (!(info->cp = calloc(1, sizeof(struct radeon_cp)))) {
xf86DrvMsg(pScrn->scrnIndex, X_ERROR,"Unable to allocate cp rec!\n");
return FALSE;
}
@@ -3085,7 +3085,7 @@ Bool RADEONPreInit(ScrnInfoPtr pScrn, int flags)
/* We can't do this until we have a
pScrn->display. */
xf86CollectOptions(pScrn, NULL);
- if (!(info->Options = xalloc(sizeof(RADEONOptions))))
+ if (!(info->Options = malloc(sizeof(RADEONOptions))))
goto fail;
memcpy(info->Options, RADEONOptions, sizeof(RADEONOptions));
@@ -3249,7 +3249,7 @@ fail:
/* Pre-init failed. */
/* Free the video bios (if applicable) */
if (info->VBIOS) {
- xfree(info->VBIOS);
+ free(info->VBIOS);
info->VBIOS = NULL;
}
@@ -3670,9 +3670,9 @@ Bool RADEONScreenInit(int scrnIndex, ScreenPtr pScreen,
"Initializing fb layer\n");
if (info->r600_shadow_fb) {
- info->fb_shadow = xcalloc(1,
- pScrn->displayWidth * pScrn->virtualY *
- ((pScrn->bitsPerPixel + 7) >> 3));
+ info->fb_shadow = calloc(1,
+ pScrn->displayWidth * pScrn->virtualY *
+ ((pScrn->bitsPerPixel + 7) >> 3));
if (info->fb_shadow == NULL) {
xf86DrvMsg(pScrn->scrnIndex, X_ERROR,
"Failed to allocate shadow framebuffer\n");
@@ -6018,7 +6018,7 @@ static Bool RADEONCloseScreen(int scrnIndex, ScreenPtr pScreen)
#ifdef USE_EXA
if (info->accel_state->exa) {
exaDriverFini(pScreen);
- xfree(info->accel_state->exa);
+ free(info->accel_state->exa);
info->accel_state->exa = NULL;
}
#endif /* USE_EXA */
@@ -6029,7 +6029,7 @@ static Bool RADEONCloseScreen(int scrnIndex, ScreenPtr pScreen)
info->accel_state->accel = NULL;
if (info->accel_state->scratch_save)
- xfree(info->accel_state->scratch_save);
+ free(info->accel_state->scratch_save);
info->accel_state->scratch_save = NULL;
}
#endif /* USE_XAA */
diff --git a/src/radeon_exa.c b/src/radeon_exa.c
index 4f974c3..d7fba65 100644
--- a/src/radeon_exa.c
+++ b/src/radeon_exa.c
@@ -372,7 +372,7 @@ void *RADEONEXACreatePixmap(ScreenPtr pScreen, int size, int align)
}
#endif
- new_priv = xcalloc(1, sizeof(struct radeon_exa_pixmap_priv));
+ new_priv = calloc(1, sizeof(struct radeon_exa_pixmap_priv));
if (!new_priv)
return NULL;
@@ -382,7 +382,7 @@ void *RADEONEXACreatePixmap(ScreenPtr pScreen, int size, int align)
new_priv->bo = radeon_bo_open(info->bufmgr, 0, size, align,
RADEON_GEM_DOMAIN_VRAM, 0);
if (!new_priv->bo) {
- xfree(new_priv);
+ free(new_priv);
ErrorF("Failed to alloc memory\n");
return NULL;
}
@@ -471,7 +471,7 @@ void *RADEONEXACreatePixmap2(ScreenPtr pScreen, int width, int height,
padded_width = RADEON_ALIGN(padded_width, pixmap_align);
size = height * padded_width;
- new_priv = xcalloc(1, sizeof(struct radeon_exa_pixmap_priv));
+ new_priv = calloc(1, sizeof(struct radeon_exa_pixmap_priv));
if (!new_priv)
return NULL;
@@ -483,7 +483,7 @@ void *RADEONEXACreatePixmap2(ScreenPtr pScreen, int width, int height,
new_priv->bo = radeon_bo_open(info->bufmgr, 0, size, 0,
RADEON_GEM_DOMAIN_VRAM, 0);
if (!new_priv->bo) {
- xfree(new_priv);
+ free(new_priv);
ErrorF("Failed to alloc memory\n");
return NULL;
}
@@ -503,7 +503,7 @@ void RADEONEXADestroyPixmap(ScreenPtr pScreen, void *driverPriv)
if (driver_priv->bo)
radeon_bo_unref(driver_priv->bo);
- xfree(driverPriv);
+ free(driverPriv);
}
struct radeon_bo *radeon_get_pixmap_bo(PixmapPtr pPix)
diff --git a/src/radeon_exa_funcs.c b/src/radeon_exa_funcs.c
index cdc0edb..2df6ccb 100644
--- a/src/radeon_exa_funcs.c
+++ b/src/radeon_exa_funcs.c
@@ -904,7 +904,7 @@ Bool FUNC_NAME(RADEONDrawInit)(ScreenPtr pScreen)
RADEONEngineInit(pScrn);
if (!exaDriverInit(pScreen, info->accel_state->exa)) {
- xfree(info->accel_state->exa);
+ free(info->accel_state->exa);
return FALSE;
}
exaMarkSync(pScreen);
diff --git a/src/radeon_kms.c b/src/radeon_kms.c
index a28f5e6..c0d2ae6 100644
--- a/src/radeon_kms.c
+++ b/src/radeon_kms.c
@@ -227,7 +227,7 @@ static Bool RADEONPreInitAccel_KMS(ScrnInfoPtr pScrn)
{
RADEONInfoPtr info = RADEONPTR(pScrn);
- if (!(info->accel_state = xcalloc(1, sizeof(struct radeon_accel_state)))) {
+ if (!(info->accel_state = calloc(1, sizeof(struct radeon_accel_state)))) {
xf86DrvMsg(pScrn->scrnIndex, X_ERROR, "Unable to allocate accel_state rec!\n");
return FALSE;
}
@@ -356,12 +356,12 @@ static Bool RADEONPreInitChipType_KMS(ScrnInfoPtr pScrn)
static Bool radeon_alloc_dri(ScrnInfoPtr pScrn)
{
RADEONInfoPtr info = RADEONPTR(pScrn);
- if (!(info->dri = xcalloc(1, sizeof(struct radeon_dri)))) {
+ if (!(info->dri = calloc(1, sizeof(struct radeon_dri)))) {
xf86DrvMsg(pScrn->scrnIndex, X_ERROR,"Unable to allocate dri rec!\n");
return FALSE;
}
- if (!(info->cp = xcalloc(1, sizeof(struct radeon_cp)))) {
+ if (!(info->cp = calloc(1, sizeof(struct radeon_cp)))) {
xf86DrvMsg(pScrn->scrnIndex, X_ERROR,"Unable to allocate cp rec!\n");
return FALSE;
}
@@ -394,10 +394,10 @@ static Bool radeon_open_drm_master(ScrnInfoPtr pScrn)
xf86DrvMsg(pScrn->scrnIndex, X_ERROR,
"[drm] Failed to open DRM device for %s: %s\n",
busid, strerror(errno));
- xfree(busid);
+ free(busid);
return FALSE;
}
- xfree(busid);
+ free(busid);
/* Check that what we opened was a master or a master-capable FD,
* by setting the version of the interface we'll use to talk to it.
@@ -472,7 +472,7 @@ Bool RADEONPreInit_KMS(ScrnInfoPtr pScrn, int flags)
goto fail;
xf86CollectOptions(pScrn, NULL);
- if (!(info->Options = xalloc(sizeof(RADEONOptions_KMS))))
+ if (!(info->Options = malloc(sizeof(RADEONOptions_KMS))))
goto fail;
memcpy(info->Options, RADEONOptions_KMS, sizeof(RADEONOptions_KMS));
@@ -643,7 +643,7 @@ static Bool RADEONCloseScreen_KMS(int scrnIndex, ScreenPtr pScreen)
if (info->accel_state->exa) {
exaDriverFini(pScreen);
- xfree(info->accel_state->exa);
+ free(info->accel_state->exa);
info->accel_state->exa = NULL;
}
@@ -741,9 +741,9 @@ Bool RADEONScreenInit_KMS(int scrnIndex, ScreenPtr pScreen,
front_ptr = info->front_bo->ptr;
if (info->r600_shadow_fb) {
- info->fb_shadow = xcalloc(1,
- pScrn->displayWidth * pScrn->virtualY *
- ((pScrn->bitsPerPixel + 7) >> 3));
+ info->fb_shadow = calloc(1,
+ pScrn->displayWidth * pScrn->virtualY *
+ ((pScrn->bitsPerPixel + 7) >> 3));
if (info->fb_shadow == NULL) {
xf86DrvMsg(pScrn->scrnIndex, X_ERROR,
"Failed to allocate shadow framebuffer\n");
diff --git a/src/radeon_output.c b/src/radeon_output.c
index 3a0d1e9..172b871 100644
--- a/src/radeon_output.c
+++ b/src/radeon_output.c
@@ -418,7 +418,7 @@ radeon_ddc_connected(xf86OutputPtr output)
if (!xf86ReturnOptValBool(info->Options, OPTION_IGNORE_EDID, FALSE))
xf86OutputSetEDID(output, MonInfo);
} else
- xfree(MonInfo);
+ free(MonInfo);
} else
MonType = MT_NONE;
@@ -1295,7 +1295,7 @@ static void
radeon_destroy (xf86OutputPtr output)
{
if (output->driver_private)
- xfree(output->driver_private);
+ free(output->driver_private);
}
static void
diff --git a/src/radeon_probe.c b/src/radeon_probe.c
index 1429835..4405d40 100644
--- a/src/radeon_probe.c
+++ b/src/radeon_probe.c
@@ -100,7 +100,7 @@ static Bool radeon_kernel_mode_enabled(ScrnInfoPtr pScrn, struct pci_device *pci
busIdString = DRICreatePCIBusID(pci_dev);
ret = drmCheckModesettingSupported(busIdString);
- xfree(busIdString);
+ free(busIdString);
if (ret) {
xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, 0,
"[KMS] drm report modesetting isn't supported.\n");
@@ -195,7 +195,7 @@ radeon_get_scrninfo(int entity_num, void *pci_dev)
}
}
- xfree(pEnt);
+ free(pEnt);
return TRUE;
}
@@ -239,8 +239,8 @@ RADEONProbe(DriverPtr drv, int flags)
}
}
- xfree(usedChips);
- xfree(devSections);
+ free(usedChips);
+ free(devSections);
return foundScreen;
}
diff --git a/src/radeon_textured_video.c b/src/radeon_textured_video.c
index 5c52a5f..c19066b 100644
--- a/src/radeon_textured_video.c
+++ b/src/radeon_textured_video.c
@@ -769,8 +769,8 @@ RADEONSetupImageTexturedVideo(ScreenPtr pScreen)
int i;
int num_texture_ports = 16;
- adapt = xcalloc(1, sizeof(XF86VideoAdaptorRec) + num_texture_ports *
- (sizeof(RADEONPortPrivRec) + sizeof(DevUnion)));
+ adapt = calloc(1, sizeof(XF86VideoAdaptorRec) + num_texture_ports *
+ (sizeof(RADEONPortPrivRec) + sizeof(DevUnion)));
if (adapt == NULL)
return NULL;
diff --git a/src/radeon_vbo.c b/src/radeon_vbo.c
index ad650b2..0735540 100644
--- a/src/radeon_vbo.c
+++ b/src/radeon_vbo.c
@@ -97,19 +97,19 @@ void radeon_vbo_free_lists(ScrnInfoPtr pScrn)
foreach_s(dma_bo, temp, &accel_state->bo_free) {
remove_from_list(dma_bo);
radeon_bo_unref(dma_bo->bo);
- xfree(dma_bo);
+ free(dma_bo);
}
foreach_s(dma_bo, temp, &accel_state->bo_wait) {
remove_from_list(dma_bo);
radeon_bo_unref(dma_bo->bo);
- xfree(dma_bo);
+ free(dma_bo);
}
foreach_s(dma_bo, temp, &accel_state->bo_reserved) {
remove_from_list(dma_bo);
radeon_bo_unref(dma_bo->bo);
- xfree(dma_bo);
+ free(dma_bo);
}
}
@@ -126,7 +126,7 @@ void radeon_vbo_flush_bos(ScrnInfoPtr pScrn)
ErrorF("leaking dma buffer\n");
while ((dma_bo->bo = radeon_bo_unref(dma_bo->bo))) {}
remove_from_list(dma_bo);
- xfree(dma_bo);
+ free(dma_bo);
continue;
}
@@ -157,7 +157,7 @@ void radeon_vbo_flush_bos(ScrnInfoPtr pScrn)
remove_from_list(dma_bo);
radeon_bo_unref(dma_bo->bo);
- xfree(dma_bo);
+ free(dma_bo);
}
}
@@ -169,7 +169,7 @@ static struct radeon_bo *radeon_vbo_get_bo(ScrnInfoPtr pScrn)
struct radeon_bo *bo;
if (is_empty_list(&accel_state->bo_free)) {
- dma_bo = xcalloc(1, sizeof(struct radeon_dma_bo));
+ dma_bo = calloc(1, sizeof(struct radeon_dma_bo));
if (!dma_bo)
return NULL;
diff --git a/src/radeon_video.c b/src/radeon_video.c
index 5e2a723..dc75279 100644
--- a/src/radeon_video.c
+++ b/src/radeon_video.c
@@ -281,7 +281,7 @@ void RADEONInitVideo(ScreenPtr pScreen)
return;
num_adaptors = xf86XVListGenericAdaptors(pScrn, &adaptors);
- newAdaptors = xalloc((num_adaptors + 2) * sizeof(XF86VideoAdaptorPtr *));
+ newAdaptors = malloc((num_adaptors + 2) * sizeof(XF86VideoAdaptorPtr *));
if (newAdaptors == NULL)
return;
@@ -316,7 +316,7 @@ void RADEONInitVideo(ScreenPtr pScreen)
xf86XVScreenInit(pScreen, adaptors, num_adaptors);
if(newAdaptors)
- xfree(newAdaptors);
+ free(newAdaptors);
}
@@ -1404,7 +1404,7 @@ static void RADEONSetupTheatre(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv)
xf86DrvMsg(pScrn->scrnIndex, X_INFO,
"Unsupported reference clock frequency, Rage Theatre disabled\n");
t->theatre_num=-1;
- xfree(pPriv->theatre);
+ free(pPriv->theatre);
pPriv->theatre = NULL;
return;
}
@@ -1423,9 +1423,9 @@ RADEONAllocAdaptor(ScrnInfoPtr pScrn)
if(!(adapt = xf86XVAllocateVideoAdaptorRec(pScrn)))
return NULL;
- if(!(pPriv = xcalloc(1, sizeof(RADEONPortPrivRec) + sizeof(DevUnion))))
+ if(!(pPriv = calloc(1, sizeof(RADEONPortPrivRec) + sizeof(DevUnion))))
{
- xfree(adapt);
+ free(adapt);
return NULL;
}
@@ -1538,7 +1538,7 @@ RADEONAllocAdaptor(ScrnInfoPtr pScrn)
if(!xf86LoadSubModule(pScrn,"theatre"))
{
xf86DrvMsg(pScrn->scrnIndex,X_ERROR,"Unable to load Rage Theatre module\n");
- xfree(pPriv->theatre);
+ free(pPriv->theatre);
goto skip_theatre;
}
break;
@@ -1548,7 +1548,7 @@ RADEONAllocAdaptor(ScrnInfoPtr pScrn)
if(!xf86LoadSubModule(pScrn,"theatre200"))
{
xf86DrvMsg(pScrn->scrnIndex,X_ERROR,"Unable to load Rage Theatre module\n");
- xfree(pPriv->theatre);
+ free(pPriv->theatre);
goto skip_theatre;
}
pPriv->theatre->microc_path = info->RageTheatreMicrocPath;
@@ -1558,7 +1558,7 @@ RADEONAllocAdaptor(ScrnInfoPtr pScrn)
default:
{
xf86DrvMsg(pScrn->scrnIndex,X_ERROR,"Unknown Theatre chip\n");
- xfree(pPriv->theatre);
+ free(pPriv->theatre);
goto skip_theatre;
}
}
@@ -1569,7 +1569,7 @@ RADEONAllocAdaptor(ScrnInfoPtr pScrn)
xf86_InitTheatre(pPriv->theatre);
if(pPriv->theatre->mode == MODE_UNINITIALIZED)
{
- Xfree(pPriv->theatre);
+ free(pPriv->theatre);
pPriv->theatre = NULL;
xf86DrvMsg(pScrn->scrnIndex,X_INFO,"Rage Theatre disabled\n");
/* Here the modules must be unloaded */
@@ -3192,18 +3192,18 @@ RADEONAllocateSurface(
surface->width = w;
surface->height = h;
- if(!(surface->pitches = xalloc(sizeof(int)))) {
+ if(!(surface->pitches = malloc(sizeof(int)))) {
radeon_legacy_free_memory(pScrn, surface_memory);
return BadAlloc;
}
- if(!(surface->offsets = xalloc(sizeof(int)))) {
- xfree(surface->pitches);
+ if(!(surface->offsets = malloc(sizeof(int)))) {
+ free(surface->pitches);
radeon_legacy_free_memory(pScrn, surface_memory);
return BadAlloc;
}
- if(!(pPriv = xalloc(sizeof(OffscreenPrivRec)))) {
- xfree(surface->pitches);
- xfree(surface->offsets);
+ if(!(pPriv = malloc(sizeof(OffscreenPrivRec)))) {
+ free(surface->pitches);
+ free(surface->offsets);
radeon_legacy_free_memory(pScrn, surface_memory);
return BadAlloc;
}
@@ -3247,9 +3247,9 @@ RADEONFreeSurface(
RADEONStopSurface(surface);
radeon_legacy_free_memory(pScrn, pPriv->surface_memory);
pPriv->surface_memory = NULL;
- xfree(surface->pitches);
- xfree(surface->offsets);
- xfree(surface->devPrivate.ptr);
+ free(surface->pitches);
+ free(surface->offsets);
+ free(surface->devPrivate.ptr);
return Success;
}
@@ -3364,7 +3364,7 @@ RADEONInitOffscreenImages(ScreenPtr pScreen)
XF86OffscreenImagePtr offscreenImages;
/* need to free this someplace */
- if (!(offscreenImages = xalloc(sizeof(XF86OffscreenImageRec))))
+ if (!(offscreenImages = malloc(sizeof(XF86OffscreenImageRec))))
return;
offscreenImages[0].image = &Images[0];
diff --git a/src/radeon_vip.c b/src/radeon_vip.c
index 05b90f1..8457078 100644
--- a/src/radeon_vip.c
+++ b/src/radeon_vip.c
@@ -349,7 +349,7 @@ void RADEONVIP_reset(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv)
void RADEONVIP_init(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv)
{
- pPriv->VIP=xcalloc(1,sizeof(GENERIC_BUS_Rec));
+ pPriv->VIP=calloc(1,sizeof(GENERIC_BUS_Rec));
pPriv->VIP->scrnIndex=pScrn->scrnIndex;
pPriv->VIP->DriverPrivate.ptr=pPriv;
pPriv->VIP->ioctl=RADEONVIP_ioctl;
diff --git a/src/theatre200.c b/src/theatre200.c
index c150ed4..16b1840 100644
--- a/src/theatre200.c
+++ b/src/theatre200.c
@@ -318,10 +318,10 @@ fail_exit:
curr_seg = seg_list;
while(curr_seg)
{
- Xfree(curr_seg->data);
+ free(curr_seg->data);
prev_seg = curr_seg;
curr_seg = curr_seg->next;
- Xfree(prev_seg);
+ free(prev_seg);
}
fclose(file);
@@ -335,10 +335,10 @@ static void microc_clean(struct rt200_microc_data* microc_datap, int screen)
while(seg_list)
{
- Xfree(seg_list->data);
+ free(seg_list->data);
prev_seg = seg_list;
seg_list = seg_list->next;
- Xfree(prev_seg);
+ free(prev_seg);
}
}
commit ea37d24b1b6d4cbcf73e680846de25b72af216e3
Author: Dave Airlie <airlied at redhat.com>
Date: Mon Jun 21 13:55:15 2010 +1000
radeon: fix support for 1.9 server master.
This moves pixmap and mode set into CSR where its allowed. Should work fine on
old servers also.
Signed-off-by: Dave Airlie <airlied at redhat.com>
diff --git a/src/radeon_kms.c b/src/radeon_kms.c
index 3f77207..a28f5e6 100644
--- a/src/radeon_kms.c
+++ b/src/radeon_kms.c
@@ -159,6 +159,11 @@ static Bool RADEONCreateScreenResources_KMS(ScreenPtr pScreen)
return FALSE;
pScreen->CreateScreenResources = RADEONCreateScreenResources_KMS;
+ if (!drmmode_set_desired_modes(pScrn, &info->drmmode))
+ return FALSE;
+
+ drmmode_uevent_init(pScrn, &info->drmmode);
+
if (info->r600_shadow_fb) {
pixmap = pScreen->GetScreenPixmap(pScreen);
@@ -865,9 +870,6 @@ Bool RADEONScreenInit_KMS(int scrnIndex, ScreenPtr pScreen,
}
pScrn->pScreen = pScreen;
- if (!drmmode_set_desired_modes(pScrn, &info->drmmode))
- return FALSE;
-
/* Provide SaveScreen & wrap BlockHandler and CloseScreen */
/* Wrap CloseScreen */
info->CloseScreen = pScreen->CloseScreen;
@@ -898,7 +900,6 @@ Bool RADEONScreenInit_KMS(int scrnIndex, ScreenPtr pScreen,
info->accel_state->XInited3D = FALSE;
info->accel_state->engineMode = EXA_ENGINEMODE_UNKNOWN;
- drmmode_uevent_init(pScrn, &info->drmmode);
return TRUE;
}
commit fdd8ecafd054f65842351aee6ee6fba7af6613b2
Author: Alex Deucher <alexdeucher at gmail.com>
Date: Wed Jun 16 19:02:10 2010 -0400
r6xx/r7xx: macro safety fixes
diff --git a/src/r600_state.h b/src/r600_state.h
index e9bfa10..43dc929 100644
--- a/src/r600_state.h
+++ b/src/r600_state.h
@@ -235,13 +235,13 @@ do { \
do { \
if ((reg) >= SET_CONFIG_REG_offset && (reg) < SET_CONFIG_REG_end) { \
PACK3((ib), IT_SET_CONFIG_REG, (num) + 1); \
- E32(ib, ((reg) - SET_CONFIG_REG_offset) >> 2); \
+ E32((ib), ((reg) - SET_CONFIG_REG_offset) >> 2); \
} else if ((reg) >= SET_CONTEXT_REG_offset && (reg) < SET_CONTEXT_REG_end) { \
PACK3((ib), IT_SET_CONTEXT_REG, (num) + 1); \
- E32(ib, ((reg) - SET_CONTEXT_REG_offset) >> 2); \
+ E32((ib), ((reg) - SET_CONTEXT_REG_offset) >> 2); \
} else if ((reg) >= SET_ALU_CONST_offset && (reg) < SET_ALU_CONST_end) { \
PACK3((ib), IT_SET_ALU_CONST, (num) + 1); \
- E32(ib, ((reg) - SET_ALU_CONST_offset) >> 2); \
+ E32((ib), ((reg) - SET_ALU_CONST_offset) >> 2); \
} else if ((reg) >= SET_RESOURCE_offset && (reg) < SET_RESOURCE_end) { \
PACK3((ib), IT_SET_RESOURCE, num + 1); \
E32((ib), ((reg) - SET_RESOURCE_offset) >> 2); \
commit 4651d77211b508cb6b76931807780e317f232220
Author: Alex Deucher <alexdeucher at gmail.com>
Date: Wed Jun 16 12:28:36 2010 -0400
radeon: fix depth 16 with ums
Fixes:
https://bugs.freedesktop.org/show_bug.cgi?id=28494
https://bugzilla.redhat.com/show_bug.cgi?id=554967
Signed-off-by: Alex Deucher <alexdeucher at gmail.com>
diff --git a/src/radeon_crtc.c b/src/radeon_crtc.c
index a4a3302..bc23ee5 100644
--- a/src/radeon_crtc.c
+++ b/src/radeon_crtc.c
@@ -564,28 +564,12 @@ radeon_crtc_gamma_set(xf86CrtcPtr crtc, uint16_t *red, uint16_t *green,
uint16_t *blue, int size)
{
RADEONCrtcPrivatePtr radeon_crtc = crtc->driver_private;
- ScrnInfoPtr pScrn = crtc->scrn;
- int i, j;
-
- if (pScrn->depth == 16) {
- for (i = 0; i < 64; i++) {
- if (i <= 31) {
- for (j = 0; j < 8; j++) {
- radeon_crtc->lut_r[i * 8 + j] = red[i] >> 6;
- radeon_crtc->lut_b[i * 8 + j] = blue[i] >> 6;
- }
- }
+ int i;
- for (j = 0; j < 4; j++) {
- radeon_crtc->lut_g[i * 4 + j] = green[i] >> 6;
- }
- }
- } else {
- for (i = 0; i < 256; i++) {
- radeon_crtc->lut_r[i] = red[i] >> 6;
- radeon_crtc->lut_g[i] = green[i] >> 6;
- radeon_crtc->lut_b[i] = blue[i] >> 6;
- }
+ for (i = 0; i < 256; i++) {
+ radeon_crtc->lut_r[i] = red[i] >> 6;
+ radeon_crtc->lut_g[i] = green[i] >> 6;
+ radeon_crtc->lut_b[i] = blue[i] >> 6;
}
radeon_crtc_load_lut(crtc);
commit 1e1d6a515428b6884fea586d180346fc74ef75a1
Author: Alex Deucher <alexdeucher at gmail.com>
Date: Wed Jun 16 12:20:03 2010 -0400
r3xx-r5xx Xv: disable bicubic filtering by default
- makes Xv more consistent with r1xx/r2xx/r6xx/r7xx
- Xv attributes like brightness, contrast, hue, etc. only work
when bicubic is disabled.
- avoids performance issues on some systems when sampling from textures
in GART with kms.
- It can be re-enabled with using xvattr
Signed-off-by: Alex Deucher <alexdeucher at gmail.com>
diff --git a/man/radeon.man b/man/radeon.man
index 05b7d16..673ab03 100644
--- a/man/radeon.man
+++ b/man/radeon.man
@@ -656,7 +656,7 @@ sizes are scaled to more than double to avoid blurred output. Bicubic
filtering is not currently compatible with other Xv attributes like hue,
contrast, and brightness, and must be disabled to use those attributes.
The default is
-.B 'auto'(2).
+.B 'off'(0).
.SH SEE ALSO
__xservername__(__appmansuffix__), __xconfigfile__(__filemansuffix__), Xserver(__appmansuffix__), X(__miscmansuffix__)
diff --git a/src/radeon_textured_video.c b/src/radeon_textured_video.c
index 1490ccb..5c52a5f 100644
--- a/src/radeon_textured_video.c
+++ b/src/radeon_textured_video.c
@@ -843,7 +843,7 @@ RADEONSetupImageTexturedVideo(ScreenPtr pScreen)
pPriv->videoStatus = 0;
pPriv->currentBuffer = 0;
pPriv->doubleBuffer = 0;
- pPriv->bicubic_state = BICUBIC_AUTO;
+ pPriv->bicubic_state = BICUBIC_OFF;
pPriv->vsync = TRUE;
pPriv->brightness = 0;
pPriv->contrast = 0;
commit c29157bbf5b0dd26857675282ab094082fbaed0d
Author: Alex Deucher <alexdeucher at gmail.com>
Date: Tue Jun 15 19:39:42 2010 -0400
r6xx/r7xx: remove unnecessary state emit
No need to emit state that doesn't impact that we use for EXA/Xv.
Signed-off-by: Alex Deucher <alexdeucher at gmail.com>
diff --git a/src/r6xx_accel.c b/src/r6xx_accel.c
index e996d9f..a0073ff 100644
--- a/src/r6xx_accel.c
+++ b/src/r6xx_accel.c
@@ -753,35 +753,6 @@ set_default_state(ScrnInfoPtr pScrn, drmBufPtr ib)
start_3d(pScrn, accel_state->ib);
- // ASIC specific setup, see drm
- BEGIN_BATCH(15);
- if (info->ChipFamily < CHIP_FAMILY_RV770) {
- EREG(ib, TA_CNTL_AUX, (( 3 << GRADIENT_CREDIT_shift) |
- (28 << TD_FIFO_CREDIT_shift)));
- EREG(ib, VC_ENHANCE, 0);
- EREG(ib, R7xx_SQ_DYN_GPR_CNTL_PS_FLUSH_REQ, 0);
- EREG(ib, DB_DEBUG, 0x82000000); /* ? */
- EREG(ib, DB_WATERMARKS, ((4 << DEPTH_FREE_shift) |
- (16 << DEPTH_FLUSH_shift) |
- (0 << FORCE_SUMMARIZE_shift) |
- (4 << DEPTH_PENDING_FREE_shift) |
- (16 << DEPTH_CACHELINE_FREE_shift) |
- 0));
- } else {
- EREG(ib, TA_CNTL_AUX, (( 2 << GRADIENT_CREDIT_shift) |
- (28 << TD_FIFO_CREDIT_shift)));
- EREG(ib, VC_ENHANCE, 0);
- EREG(ib, R7xx_SQ_DYN_GPR_CNTL_PS_FLUSH_REQ, VS_PC_LIMIT_ENABLE_bit);
- EREG(ib, DB_DEBUG, 0);
- EREG(ib, DB_WATERMARKS, ((4 << DEPTH_FREE_shift) |
- (16 << DEPTH_FLUSH_shift) |
- (0 << FORCE_SUMMARIZE_shift) |
- (4 << DEPTH_PENDING_FREE_shift) |
- (4 << DEPTH_CACHELINE_FREE_shift) |
- 0));
- }
- END_BATCH();
-
// SQ
sq_conf.ps_prio = 0;
sq_conf.vs_prio = 1;
@@ -906,34 +877,14 @@ set_default_state(ScrnInfoPtr pScrn, drmBufPtr ib)
sq_setup(pScrn, ib, &sq_conf);
- BEGIN_BATCH(47);
+ BEGIN_BATCH(41);
PACK0(ib, SQ_VTX_BASE_VTX_LOC, 2);
E32(ib, 0);
E32(ib, 0);
- PACK0(ib, SQ_ESGS_RING_ITEMSIZE, 9);
- E32(ib, 0); // SQ_ESGS_RING_ITEMSIZE
- E32(ib, 0); // SQ_GSVS_RING_ITEMSIZE
- E32(ib, 0); // SQ_ESTMP_RING_ITEMSIZE
- E32(ib, 0); // SQ_GSTMP_RING_ITEMSIZE
- E32(ib, 0); // SQ_VSTMP_RING_ITEMSIZE
- E32(ib, 0); // SQ_PSTMP_RING_ITEMSIZE
- E32(ib, 0); // SQ_FBUF_RING_ITEMSIZE
- E32(ib, 0); // SQ_REDUC_RING_ITEMSIZE
- E32(ib, 0); // SQ_GS_VERT_ITEMSIZE
-
// DB
EREG(ib, DB_DEPTH_INFO, 0);
- PACK0(ib, DB_STENCIL_CLEAR, 2);
- E32(ib, 0);
- E32(ib, 0);
-
- PACK0(ib, DB_STENCILREFMASK, 3);
- E32(ib, 0);
- E32(ib, 0);
- E32(ib, 0);
-
EREG(ib, DB_DEPTH_CONTROL, 0);
PACK0(ib, DB_RENDER_CONTROL, 2);
E32(ib, STENCIL_COMPRESS_DISABLE_bit | DEPTH_COMPRESS_DISABLE_bit);
@@ -948,29 +899,6 @@ set_default_state(ScrnInfoPtr pScrn, drmBufPtr ib)
EREG(ib, DB_SHADER_CONTROL, ((1 << Z_ORDER_shift) | /* EARLY_Z_THEN_LATE_Z */
DUAL_EXPORT_ENABLE_bit)); /* Only useful if no depth export */
- PACK0(ib, SX_ALPHA_TEST_CONTROL, 5);
- E32(ib, 0); // SX_ALPHA_TEST_CONTROL
- E32(ib, 0x00000000); //CB_BLEND_RED
- E32(ib, 0x00000000);
- E32(ib, 0x00000000);
- E32(ib, 0x00000000);
- END_BATCH();
-
- if (info->ChipFamily < CHIP_FAMILY_RV770) {
- BEGIN_BATCH(11);
- PACK0(ib, CB_FOG_RED, 3);
- E32(ib, 0x00000000);
- E32(ib, 0x00000000);
- E32(ib, 0x00000000);
- PACK0(ib, CB_CLEAR_RED, 4);
- EFLOAT(ib, 1.0); /* WTF? */
- EFLOAT(ib, 0.0);
- EFLOAT(ib, 1.0);
- EFLOAT(ib, 1.0);
- END_BATCH();
- }
-
- BEGIN_BATCH(21);
PACK0(ib, CB_CLRCMP_CONTROL, 4);
E32(ib, 1 << CLRCMP_FCN_SEL_shift); // CB_CLRCMP_CONTROL: use CLRCMP_FCN_SRC
E32(ib, 0); // CB_CLRCMP_SRC
@@ -996,16 +924,10 @@ set_default_state(ScrnInfoPtr pScrn, drmBufPtr ib)
for (i = 0; i < PA_SC_CLIPRECT_0_TL_num; i++)
set_clip_rect (pScrn, ib, i, 0, 0, 8192, 8192);
- for (i = 0; i < PA_SC_VPORT_SCISSOR_0_TL_num; i++) {
+ for (i = 0; i < PA_SC_VPORT_SCISSOR_0_TL_num; i++)
set_vport_scissor (pScrn, ib, i, 0, 0, 8192, 8192);
- BEGIN_BATCH(4);
- PACK0(ib, PA_SC_VPORT_ZMIN_0 + i * PA_SC_VPORT_ZMIN_0_offset, 2);
- EFLOAT(ib, 0.0);
- EFLOAT(ib, 1.0);
- END_BATCH();
- }
- BEGIN_BATCH(16);
+ BEGIN_BATCH(40);
PACK0(ib, PA_SC_MPASS_PS_CNTL, 2);
E32(ib, 0);
if (info->ChipFamily < CHIP_FAMILY_RV770)
@@ -1025,25 +947,6 @@ set_default_state(ScrnInfoPtr pScrn, drmBufPtr ib)
EFLOAT(ib, 1.0); // PA_CL_GB_HORZ_DISC_ADJ
EREG(ib, PA_SC_AA_MASK, 0xFFFFFFFF);
- END_BATCH();
-
- //XXX: double check this
- if (info->ChipFamily > CHIP_FAMILY_R600) {
- BEGIN_BATCH(6);
- EREG(ib, PA_SC_AA_SAMPLE_LOCS_MCTX, 0);
- EREG(ib, PA_SC_AA_SAMPLE_LOCS_8S_WD1_M, 0);
- END_BATCH();
- }
-
- BEGIN_BATCH(38);
- // CL
- PACK0(ib, PA_CL_VPORT_XSCALE_0, 6);
- EFLOAT(ib, 0.0f); // PA_CL_VPORT_XSCALE
- EFLOAT(ib, 0.0f); // PA_CL_VPORT_XOFFSET
- EFLOAT(ib, 0.0f); // PA_CL_VPORT_YSCALE
- EFLOAT(ib, 0.0f); // PA_CL_VPORT_YOFFSET
- EFLOAT(ib, 0.0f); // PA_CL_VPORT_ZSCALE
- EFLOAT(ib, 0.0f); // PA_CL_VPORT_ZOFFSET
PACK0(ib, PA_CL_CLIP_CNTL, 5);
E32(ib, CLIP_DISABLE_bit); // PA_CL_CLIP_CNTL
@@ -1052,12 +955,6 @@ set_default_state(ScrnInfoPtr pScrn, drmBufPtr ib)
E32(ib, 0); // PA_CL_VS_OUT_CNTL
E32(ib, 0); // PA_CL_NANINF_CNTL
- PACK0(ib, PA_SU_POINT_SIZE, 4);
- E32(ib, 0); // PA_SU_POINT_SIZE
- E32(ib, 0); // PA_SU_POINT_MINMAX
- E32(ib, (8 << PA_SU_LINE_CNTL__WIDTH_shift)); /* Line width 1 pixel */ // PA_SU_LINE_CNTL
- E32(ib, 0); // PA_SC_LINE_STIPPLE
-
PACK0(ib, PA_SU_POLY_OFFSET_DB_FMT_CNTL, 6);
E32(ib, 0); // PA_SU_POLY_OFFSET_DB_FMT_CNTL
E32(ib, 0); // PA_SU_POLY_OFFSET_CLAMP
commit 35280545fcfb911f189d7657bd1040a28450fe7b
Author: Alex Deucher <alexdeucher at gmail.com>
Date: Tue Jun 15 19:21:32 2010 -0400
r6xx/r7xx: reorg default and clipping state emit
Group ordered registers to save command buffer space.
Reduces the default and clipping state from 256 to 160 dwords.
Signed-off-by: Alex Deucher <alexdeucher at gmail.com>
diff --git a/src/r6xx_accel.c b/src/r6xx_accel.c
index 4445728..e996d9f 100644
--- a/src/r6xx_accel.c
+++ b/src/r6xx_accel.c
@@ -661,11 +661,12 @@ set_screen_scissor(ScrnInfoPtr pScrn, drmBufPtr ib, int x1, int y1, int x2, int
{
RADEONInfoPtr info = RADEONPTR(pScrn);
- BEGIN_BATCH(6);
- EREG(ib, PA_SC_SCREEN_SCISSOR_TL, ((x1 << PA_SC_SCREEN_SCISSOR_TL__TL_X_shift) |
- (y1 << PA_SC_SCREEN_SCISSOR_TL__TL_Y_shift)));
- EREG(ib, PA_SC_SCREEN_SCISSOR_BR, ((x2 << PA_SC_SCREEN_SCISSOR_BR__BR_X_shift) |
- (y2 << PA_SC_SCREEN_SCISSOR_BR__BR_Y_shift)));
+ BEGIN_BATCH(4);
+ PACK0(ib, PA_SC_SCREEN_SCISSOR_TL, 2);
+ E32(ib, ((x1 << PA_SC_SCREEN_SCISSOR_TL__TL_X_shift) |
+ (y1 << PA_SC_SCREEN_SCISSOR_TL__TL_Y_shift)));
+ E32(ib, ((x2 << PA_SC_SCREEN_SCISSOR_BR__BR_X_shift) |
+ (y2 << PA_SC_SCREEN_SCISSOR_BR__BR_Y_shift)));
END_BATCH();
}
@@ -674,14 +675,13 @@ set_vport_scissor(ScrnInfoPtr pScrn, drmBufPtr ib, int id, int x1, int y1, int x
{
RADEONInfoPtr info = RADEONPTR(pScrn);
- BEGIN_BATCH(6);
- EREG(ib, PA_SC_VPORT_SCISSOR_0_TL +
- id * PA_SC_VPORT_SCISSOR_0_TL_offset, ((x1 << PA_SC_VPORT_SCISSOR_0_TL__TL_X_shift) |
- (y1 << PA_SC_VPORT_SCISSOR_0_TL__TL_Y_shift) |
- WINDOW_OFFSET_DISABLE_bit));
- EREG(ib, PA_SC_VPORT_SCISSOR_0_BR +
- id * PA_SC_VPORT_SCISSOR_0_BR_offset, ((x2 << PA_SC_VPORT_SCISSOR_0_BR__BR_X_shift) |
- (y2 << PA_SC_VPORT_SCISSOR_0_BR__BR_Y_shift)));
+ BEGIN_BATCH(4);
+ PACK0(ib, PA_SC_VPORT_SCISSOR_0_TL + id * PA_SC_VPORT_SCISSOR_0_TL_offset, 2);
+ E32(ib, ((x1 << PA_SC_VPORT_SCISSOR_0_TL__TL_X_shift) |
+ (y1 << PA_SC_VPORT_SCISSOR_0_TL__TL_Y_shift) |
+ WINDOW_OFFSET_DISABLE_bit));
+ E32(ib, ((x2 << PA_SC_VPORT_SCISSOR_0_BR__BR_X_shift) |
+ (y2 << PA_SC_VPORT_SCISSOR_0_BR__BR_Y_shift)));
END_BATCH();
}
@@ -690,12 +690,13 @@ set_generic_scissor(ScrnInfoPtr pScrn, drmBufPtr ib, int x1, int y1, int x2, int
{
RADEONInfoPtr info = RADEONPTR(pScrn);
- BEGIN_BATCH(6);
- EREG(ib, PA_SC_GENERIC_SCISSOR_TL, ((x1 << PA_SC_GENERIC_SCISSOR_TL__TL_X_shift) |
- (y1 << PA_SC_GENERIC_SCISSOR_TL__TL_Y_shift) |
- WINDOW_OFFSET_DISABLE_bit));
- EREG(ib, PA_SC_GENERIC_SCISSOR_BR, ((x2 << PA_SC_GENERIC_SCISSOR_BR__BR_X_shift) |
- (y2 << PA_SC_GENERIC_SCISSOR_TL__TL_Y_shift)));
+ BEGIN_BATCH(4);
+ PACK0(ib, PA_SC_GENERIC_SCISSOR_TL, 2);
+ E32(ib, ((x1 << PA_SC_GENERIC_SCISSOR_TL__TL_X_shift) |
+ (y1 << PA_SC_GENERIC_SCISSOR_TL__TL_Y_shift) |
+ WINDOW_OFFSET_DISABLE_bit));
+ E32(ib, ((x2 << PA_SC_GENERIC_SCISSOR_BR__BR_X_shift) |
+ (y2 << PA_SC_GENERIC_SCISSOR_TL__TL_Y_shift)));
END_BATCH();
}
@@ -704,12 +705,13 @@ set_window_scissor(ScrnInfoPtr pScrn, drmBufPtr ib, int x1, int y1, int x2, int
{
RADEONInfoPtr info = RADEONPTR(pScrn);
- BEGIN_BATCH(6);
- EREG(ib, PA_SC_WINDOW_SCISSOR_TL, ((x1 << PA_SC_WINDOW_SCISSOR_TL__TL_X_shift) |
- (y1 << PA_SC_WINDOW_SCISSOR_TL__TL_Y_shift) |
- WINDOW_OFFSET_DISABLE_bit));
- EREG(ib, PA_SC_WINDOW_SCISSOR_BR, ((x2 << PA_SC_WINDOW_SCISSOR_BR__BR_X_shift) |
- (y2 << PA_SC_WINDOW_SCISSOR_BR__BR_Y_shift)));
+ BEGIN_BATCH(4);
+ PACK0(ib, PA_SC_WINDOW_SCISSOR_TL, 2);
+ E32(ib, ((x1 << PA_SC_WINDOW_SCISSOR_TL__TL_X_shift) |
+ (y1 << PA_SC_WINDOW_SCISSOR_TL__TL_Y_shift) |
+ WINDOW_OFFSET_DISABLE_bit));
+ E32(ib, ((x2 << PA_SC_WINDOW_SCISSOR_BR__BR_X_shift) |
+ (y2 << PA_SC_WINDOW_SCISSOR_BR__BR_Y_shift)));
END_BATCH();
}
@@ -718,13 +720,12 @@ set_clip_rect(ScrnInfoPtr pScrn, drmBufPtr ib, int id, int x1, int y1, int x2, i
{
RADEONInfoPtr info = RADEONPTR(pScrn);
- BEGIN_BATCH(6);
- EREG(ib, PA_SC_CLIPRECT_0_TL +
- id * PA_SC_CLIPRECT_0_TL_offset, ((x1 << PA_SC_CLIPRECT_0_TL__TL_X_shift) |
- (y1 << PA_SC_CLIPRECT_0_TL__TL_Y_shift)));
- EREG(ib, PA_SC_CLIPRECT_0_BR +
- id * PA_SC_CLIPRECT_0_BR_offset, ((x2 << PA_SC_CLIPRECT_0_BR__BR_X_shift) |
- (y2 << PA_SC_CLIPRECT_0_BR__BR_Y_shift)));
+ BEGIN_BATCH(4);
+ PACK0(ib, PA_SC_CLIPRECT_0_TL + id * PA_SC_CLIPRECT_0_TL_offset, 2);
+ E32(ib, ((x1 << PA_SC_CLIPRECT_0_TL__TL_X_shift) |
+ (y1 << PA_SC_CLIPRECT_0_TL__TL_Y_shift)));
+ E32(ib, ((x2 << PA_SC_CLIPRECT_0_BR__BR_X_shift) |
+ (y2 << PA_SC_CLIPRECT_0_BR__BR_Y_shift)));
END_BATCH();
}
@@ -905,9 +906,10 @@ set_default_state(ScrnInfoPtr pScrn, drmBufPtr ib)
sq_setup(pScrn, ib, &sq_conf);
- BEGIN_BATCH(59);
- EREG(ib, SQ_VTX_BASE_VTX_LOC, 0);
- EREG(ib, SQ_VTX_START_INST_LOC, 0);
+ BEGIN_BATCH(47);
+ PACK0(ib, SQ_VTX_BASE_VTX_LOC, 2);
+ E32(ib, 0);
+ E32(ib, 0);
PACK0(ib, SQ_ESGS_RING_ITEMSIZE, 9);
E32(ib, 0); // SQ_ESGS_RING_ITEMSIZE
@@ -922,33 +924,33 @@ set_default_state(ScrnInfoPtr pScrn, drmBufPtr ib)
// DB
EREG(ib, DB_DEPTH_INFO, 0);
- EREG(ib, DB_STENCIL_CLEAR, 0);
- EREG(ib, DB_DEPTH_CLEAR, 0);
- EREG(ib, DB_STENCILREFMASK, 0);
- EREG(ib, DB_STENCILREFMASK_BF, 0);
+
+ PACK0(ib, DB_STENCIL_CLEAR, 2);
+ E32(ib, 0);
+ E32(ib, 0);
+
+ PACK0(ib, DB_STENCILREFMASK, 3);
+ E32(ib, 0);
+ E32(ib, 0);
+ E32(ib, 0);
+
EREG(ib, DB_DEPTH_CONTROL, 0);
- EREG(ib, DB_RENDER_CONTROL, STENCIL_COMPRESS_DISABLE_bit | DEPTH_COMPRESS_DISABLE_bit);
+ PACK0(ib, DB_RENDER_CONTROL, 2);
+ E32(ib, STENCIL_COMPRESS_DISABLE_bit | DEPTH_COMPRESS_DISABLE_bit);
if (info->ChipFamily < CHIP_FAMILY_RV770)
- EREG(ib, DB_RENDER_OVERRIDE, FORCE_SHADER_Z_ORDER_bit);
+ E32(ib, FORCE_SHADER_Z_ORDER_bit);
else
- EREG(ib, DB_RENDER_OVERRIDE, 0);
+ E32(ib, 0);
EREG(ib, DB_ALPHA_TO_MASK, ((2 << ALPHA_TO_MASK_OFFSET0_shift) |
(2 << ALPHA_TO_MASK_OFFSET1_shift) |
(2 << ALPHA_TO_MASK_OFFSET2_shift) |
(2 << ALPHA_TO_MASK_OFFSET3_shift)));
-
-
EREG(ib, DB_SHADER_CONTROL, ((1 << Z_ORDER_shift) | /* EARLY_Z_THEN_LATE_Z */
DUAL_EXPORT_ENABLE_bit)); /* Only useful if no depth export */
-
- // SX
- EREG(ib, SX_ALPHA_TEST_CONTROL, 0);
- EREG(ib, SX_ALPHA_REF, 0);
-
- // CB
- PACK0(ib, CB_BLEND_RED, 4);
- E32(ib, 0x00000000);
+ PACK0(ib, SX_ALPHA_TEST_CONTROL, 5);
+ E32(ib, 0); // SX_ALPHA_TEST_CONTROL
+ E32(ib, 0x00000000); //CB_BLEND_RED
E32(ib, 0x00000000);
E32(ib, 0x00000000);
E32(ib, 0x00000000);
@@ -975,21 +977,19 @@ set_default_state(ScrnInfoPtr pScrn, drmBufPtr ib)
E32(ib, 0); // CB_CLRCMP_DST
E32(ib, 0); // CB_CLRCMP_MSK
- EREG(ib, CB_SHADER_MASK, (0xf << OUTPUT0_ENABLE_shift));
+ EREG(ib, CB_SHADER_MASK, OUTPUT0_ENABLE_mask);
EREG(ib, R7xx_CB_SHADER_CONTROL, (RT0_ENABLE_bit));
-
- // SC
EREG(ib, PA_SC_WINDOW_OFFSET, ((0 << WINDOW_X_OFFSET_shift) |
(0 << WINDOW_Y_OFFSET_shift)));
- EREG(ib, PA_SC_CLIPRECT_RULE, CLIP_RULE_mask);
-
if (info->ChipFamily < CHIP_FAMILY_RV770)
EREG(ib, R7xx_PA_SC_EDGERULE, 0x00000000);
else
EREG(ib, R7xx_PA_SC_EDGERULE, 0xAAAAAAAA);
+ EREG(ib, PA_SC_CLIPRECT_RULE, CLIP_RULE_mask);
+
END_BATCH();
/* clip boolean is set to always visible -> doesn't matter */
@@ -1005,15 +1005,25 @@ set_default_state(ScrnInfoPtr pScrn, drmBufPtr ib)
END_BATCH();
}
- BEGIN_BATCH(12);
+ BEGIN_BATCH(16);
+ PACK0(ib, PA_SC_MPASS_PS_CNTL, 2);
+ E32(ib, 0);
if (info->ChipFamily < CHIP_FAMILY_RV770)
- EREG(ib, PA_SC_MODE_CNTL, (WALK_ORDER_ENABLE_bit | FORCE_EOV_CNTDWN_ENABLE_bit));
+ E32(ib, (WALK_ORDER_ENABLE_bit | FORCE_EOV_CNTDWN_ENABLE_bit));
else
- EREG(ib, PA_SC_MODE_CNTL, (FORCE_EOV_CNTDWN_ENABLE_bit | FORCE_EOV_REZ_ENABLE_bit |
- 0x00500000)); /* ? */
+ E32(ib, (FORCE_EOV_CNTDWN_ENABLE_bit | FORCE_EOV_REZ_ENABLE_bit |
+ 0x00500000)); /* ? */
+
+ PACK0(ib, PA_SC_LINE_CNTL, 7);
+ E32(ib, 0); // PA_SC_LINE_CNTL
+ E32(ib, 0); // PA_SC_AA_CONFIG
+ E32(ib, ((2 << PA_SU_VTX_CNTL__ROUND_MODE_shift) | PIX_CENTER_bit | // PA_SU_VTX_CNTL
+ (5 << QUANT_MODE_shift))); /* Round to Even, fixed point 1/256 */
+ EFLOAT(ib, 1.0); // PA_CL_GB_VERT_CLIP_ADJ
+ EFLOAT(ib, 1.0); // PA_CL_GB_VERT_DISC_ADJ
+ EFLOAT(ib, 1.0); // PA_CL_GB_HORZ_CLIP_ADJ
+ EFLOAT(ib, 1.0); // PA_CL_GB_HORZ_DISC_ADJ
- EREG(ib, PA_SC_LINE_CNTL, 0);
- EREG(ib, PA_SC_AA_CONFIG, 0);
EREG(ib, PA_SC_AA_MASK, 0xFFFFFFFF);
END_BATCH();
@@ -1025,10 +1035,7 @@ set_default_state(ScrnInfoPtr pScrn, drmBufPtr ib)
END_BATCH();
}
- BEGIN_BATCH(80);
- EREG(ib, PA_SC_LINE_STIPPLE, 0);
- EREG(ib, PA_SC_MPASS_PS_CNTL, 0);
-
+ BEGIN_BATCH(38);
// CL
PACK0(ib, PA_CL_VPORT_XSCALE_0, 6);
EFLOAT(ib, 0.0f); // PA_CL_VPORT_XSCALE
@@ -1037,32 +1044,27 @@ set_default_state(ScrnInfoPtr pScrn, drmBufPtr ib)
EFLOAT(ib, 0.0f); // PA_CL_VPORT_YOFFSET
EFLOAT(ib, 0.0f); // PA_CL_VPORT_ZSCALE
EFLOAT(ib, 0.0f); // PA_CL_VPORT_ZOFFSET
- EREG(ib, PA_CL_VS_OUT_CNTL, 0);
- EREG(ib, PA_CL_NANINF_CNTL, 0);
- PACK0(ib, PA_CL_GB_VERT_CLIP_ADJ, 4);
- EFLOAT(ib, 1.0); // PA_CL_GB_VERT_CLIP_ADJ
- EFLOAT(ib, 1.0); // PA_CL_GB_VERT_DISC_ADJ
- EFLOAT(ib, 1.0); // PA_CL_GB_HORZ_CLIP_ADJ
- EFLOAT(ib, 1.0); // PA_CL_GB_HORZ_DISC_ADJ
- /* Scissor / viewport */
- EREG(ib, PA_CL_VTE_CNTL, VTX_XY_FMT_bit);
- EREG(ib, PA_CL_CLIP_CNTL, CLIP_DISABLE_bit);
-
- // SU
- EREG(ib, PA_SU_SC_MODE_CNTL, FACE_bit);
- EREG(ib, PA_SU_POINT_SIZE, 0);
- EREG(ib, PA_SU_POINT_MINMAX, 0);
- EREG(ib, PA_SU_POLY_OFFSET_DB_FMT_CNTL, 0);
- EREG(ib, PA_SU_POLY_OFFSET_BACK_SCALE, 0);
- EREG(ib, PA_SU_POLY_OFFSET_FRONT_SCALE, 0);
- EREG(ib, PA_SU_POLY_OFFSET_BACK_OFFSET, 0);
- EREG(ib, PA_SU_POLY_OFFSET_FRONT_OFFSET, 0);
-
- EREG(ib, PA_SU_LINE_CNTL, (8 << PA_SU_LINE_CNTL__WIDTH_shift)); /* Line width 1 pixel */
- EREG(ib, PA_SU_VTX_CNTL, ((2 << PA_SU_VTX_CNTL__ROUND_MODE_shift) | PIX_CENTER_bit |
- (5 << QUANT_MODE_shift))); /* Round to Even, fixed point 1/256 */
- EREG(ib, PA_SU_POLY_OFFSET_CLAMP, 0);
+ PACK0(ib, PA_CL_CLIP_CNTL, 5);
+ E32(ib, CLIP_DISABLE_bit); // PA_CL_CLIP_CNTL
+ E32(ib, FACE_bit); // PA_SU_SC_MODE_CNTL
+ E32(ib, VTX_XY_FMT_bit); // PA_CL_VTE_CNTL
+ E32(ib, 0); // PA_CL_VS_OUT_CNTL
+ E32(ib, 0); // PA_CL_NANINF_CNTL
+
+ PACK0(ib, PA_SU_POINT_SIZE, 4);
+ E32(ib, 0); // PA_SU_POINT_SIZE
+ E32(ib, 0); // PA_SU_POINT_MINMAX
+ E32(ib, (8 << PA_SU_LINE_CNTL__WIDTH_shift)); /* Line width 1 pixel */ // PA_SU_LINE_CNTL
+ E32(ib, 0); // PA_SC_LINE_STIPPLE
+
+ PACK0(ib, PA_SU_POLY_OFFSET_DB_FMT_CNTL, 6);
+ E32(ib, 0); // PA_SU_POLY_OFFSET_DB_FMT_CNTL
+ E32(ib, 0); // PA_SU_POLY_OFFSET_CLAMP
+ E32(ib, 0); // PA_SU_POLY_OFFSET_FRONT_SCALE
+ E32(ib, 0); // PA_SU_POLY_OFFSET_FRONT_OFFSET
+ E32(ib, 0); // PA_SU_POLY_OFFSET_BACK_SCALE
+ E32(ib, 0); // PA_SU_POLY_OFFSET_BACK_OFFSET
// SPI
if (info->ChipFamily < CHIP_FAMILY_RV770)
@@ -1070,10 +1072,12 @@ set_default_state(ScrnInfoPtr pScrn, drmBufPtr ib)
else
EREG(ib, R7xx_SPI_THREAD_GROUPING, (1 << PS_GROUPING_shift));
- EREG(ib, SPI_INPUT_Z, 0);
- EREG(ib, SPI_FOG_CNTL, 0);
- EREG(ib, SPI_FOG_FUNC_SCALE, 0);
- EREG(ib, SPI_FOG_FUNC_BIAS, 0);
+ PACK0(ib, SPI_INPUT_Z, 4);
+ E32(ib, 0); // SPI_INPUT_Z
+ E32(ib, 0); // SPI_FOG_CNTL
+ E32(ib, 0); // SPI_FOG_FUNC_SCALE
+ E32(ib, 0); // SPI_FOG_FUNC_BIAS
+
END_BATCH();
// clear FS
@@ -1081,31 +1085,40 @@ set_default_state(ScrnInfoPtr pScrn, drmBufPtr ib)
fs_setup(pScrn, ib, &fs_conf, RADEON_GEM_DOMAIN_VRAM);
// VGT
- BEGIN_BATCH(75);
- EREG(ib, VGT_MAX_VTX_INDX, 2048); /* XXX set to a reasonably large number of indices */
- EREG(ib, VGT_MIN_VTX_INDX, 0);
- EREG(ib, VGT_INDX_OFFSET, 0);
- EREG(ib, VGT_INSTANCE_STEP_RATE_0, 0);
- EREG(ib, VGT_INSTANCE_STEP_RATE_1, 0);
- EREG(ib, VGT_MULTI_PRIM_IB_RESET_INDX, 0);
- EREG(ib, VGT_OUTPUT_PATH_CNTL, 0);
- EREG(ib, VGT_GS_MODE, 0);
- EREG(ib, VGT_HOS_CNTL, 0);
- EREG(ib, VGT_HOS_MAX_TESS_LEVEL, 0);
- EREG(ib, VGT_HOS_MIN_TESS_LEVEL, 0);
- EREG(ib, VGT_HOS_REUSE_DEPTH, 0);
- EREG(ib, VGT_GROUP_PRIM_TYPE, 0);
- EREG(ib, VGT_GROUP_FIRST_DECR, 0);
- EREG(ib, VGT_GROUP_DECR, 0);
- EREG(ib, VGT_GROUP_VECT_0_CNTL, 0);
- EREG(ib, VGT_GROUP_VECT_1_CNTL, 0);
- EREG(ib, VGT_GROUP_VECT_0_FMT_CNTL, 0);
- EREG(ib, VGT_GROUP_VECT_1_FMT_CNTL, 0);
+ BEGIN_BATCH(39);
+ PACK0(ib, VGT_MAX_VTX_INDX, 4);
+ E32(ib, 2048); /* XXX set to a reasonably large number of indices */ // VGT_MAX_VTX_INDX
+ E32(ib, 0); // VGT_MIN_VTX_INDX
+ E32(ib, 0); // VGT_INDX_OFFSET
+ E32(ib, 0); // VGT_MULTI_PRIM_IB_RESET_INDX
+
EREG(ib, VGT_PRIMITIVEID_EN, 0);
EREG(ib, VGT_MULTI_PRIM_IB_RESET_EN, 0);
- EREG(ib, VGT_STRMOUT_EN, 0);
- EREG(ib, VGT_REUSE_OFF, 0);
- EREG(ib, VGT_VTX_CNT_EN, 0);
+
+ PACK0(ib, VGT_INSTANCE_STEP_RATE_0, 2);
+ E32(ib, 0); // VGT_INSTANCE_STEP_RATE_0
+ E32(ib, 0); // VGT_INSTANCE_STEP_RATE_1
+
+ PACK0(ib, VGT_OUTPUT_PATH_CNTL, 13);
+ E32(ib, 0); // VGT_OUTPUT_PATH_CNTL
+ E32(ib, 0); // VGT_HOS_CNTL
+ E32(ib, 0); // VGT_HOS_MAX_TESS_LEVEL
+ E32(ib, 0); // VGT_HOS_MIN_TESS_LEVEL
+ E32(ib, 0); // VGT_HOS_REUSE_DEPTH
+ E32(ib, 0); // VGT_GROUP_PRIM_TYPE
+ E32(ib, 0); // VGT_GROUP_FIRST_DECR
+ E32(ib, 0); // VGT_GROUP_DECR
+ E32(ib, 0); // VGT_GROUP_VECT_0_CNTL
+ E32(ib, 0); // VGT_GROUP_VECT_1_CNTL
+ E32(ib, 0); // VGT_GROUP_VECT_0_FMT_CNTL
+ E32(ib, 0); // VGT_GROUP_VECT_1_FMT_CNTL
+ E32(ib, 0); // VGT_GS_MODE
+
+ PACK0(ib, VGT_STRMOUT_EN, 3);
+ E32(ib, 0); // VGT_STRMOUT_EN
+ E32(ib, 0); // VGT_REUSE_OFF
+ E32(ib, 0); // VGT_VTX_CNT_EN
+
EREG(ib, VGT_STRMOUT_BUFFER_EN, 0);
END_BATCH();
}
commit a2528a734c1d4e8639c49e5d222e3630a93ffbfd
Author: Alex Deucher <alexdeucher at gmail.com>
Date: Tue Jun 15 17:00:34 2010 -0400
r6xx/r7xx accel: remove some duplicate emits and minor clean up
Signed-off-by: Alex Deucher <alexdeucher at gmail.com>
diff --git a/src/r6xx_accel.c b/src/r6xx_accel.c
index a835d71..4445728 100644
--- a/src/r6xx_accel.c
+++ b/src/r6xx_accel.c
@@ -968,7 +968,7 @@ set_default_state(ScrnInfoPtr pScrn, drmBufPtr ib)
END_BATCH();
}
- BEGIN_BATCH(18);
+ BEGIN_BATCH(21);
PACK0(ib, CB_CLRCMP_CONTROL, 4);
E32(ib, 1 << CLRCMP_FCN_SEL_shift); // CB_CLRCMP_CONTROL: use CLRCMP_FCN_SRC
E32(ib, 0); // CB_CLRCMP_SRC
@@ -984,19 +984,18 @@ set_default_state(ScrnInfoPtr pScrn, drmBufPtr ib)
(0 << WINDOW_Y_OFFSET_shift)));
EREG(ib, PA_SC_CLIPRECT_RULE, CLIP_RULE_mask);
- END_BATCH();
-
- /* clip boolean is set to always visible -> doesn't matter */
- for (i = 0; i < PA_SC_CLIPRECT_0_TL_num; i++)
- set_clip_rect (pScrn, ib, i, 0, 0, 8192, 8192);
- BEGIN_BATCH(3);
if (info->ChipFamily < CHIP_FAMILY_RV770)
EREG(ib, R7xx_PA_SC_EDGERULE, 0x00000000);
else
EREG(ib, R7xx_PA_SC_EDGERULE, 0xAAAAAAAA);
+
END_BATCH();
+ /* clip boolean is set to always visible -> doesn't matter */
+ for (i = 0; i < PA_SC_CLIPRECT_0_TL_num; i++)
+ set_clip_rect (pScrn, ib, i, 0, 0, 8192, 8192);
+
for (i = 0; i < PA_SC_VPORT_SCISSOR_0_TL_num; i++) {
set_vport_scissor (pScrn, ib, i, 0, 0, 8192, 8192);
BEGIN_BATCH(4);
@@ -1006,18 +1005,13 @@ set_default_state(ScrnInfoPtr pScrn, drmBufPtr ib)
END_BATCH();
}
- BEGIN_BATCH(15);
+ BEGIN_BATCH(12);
if (info->ChipFamily < CHIP_FAMILY_RV770)
EREG(ib, PA_SC_MODE_CNTL, (WALK_ORDER_ENABLE_bit | FORCE_EOV_CNTDWN_ENABLE_bit));
else
EREG(ib, PA_SC_MODE_CNTL, (FORCE_EOV_CNTDWN_ENABLE_bit | FORCE_EOV_REZ_ENABLE_bit |
0x00500000)); /* ? */
- EREG(ib, PA_SU_SC_MODE_CNTL, (FACE_bit |
- (POLYMODE_PTYPE__TRIANGLES << POLYMODE_FRONT_PTYPE_shift) |
- (POLYMODE_PTYPE__TRIANGLES << POLYMODE_BACK_PTYPE_shift)));
-
-
EREG(ib, PA_SC_LINE_CNTL, 0);
EREG(ib, PA_SC_AA_CONFIG, 0);
EREG(ib, PA_SC_AA_MASK, 0xFFFFFFFF);
@@ -1031,7 +1025,7 @@ set_default_state(ScrnInfoPtr pScrn, drmBufPtr ib)
END_BATCH();
}
- BEGIN_BATCH(83);
+ BEGIN_BATCH(80);
EREG(ib, PA_SC_LINE_STIPPLE, 0);
EREG(ib, PA_SC_MPASS_PS_CNTL, 0);
@@ -1043,7 +1037,6 @@ set_default_state(ScrnInfoPtr pScrn, drmBufPtr ib)
EFLOAT(ib, 0.0f); // PA_CL_VPORT_YOFFSET
EFLOAT(ib, 0.0f); // PA_CL_VPORT_ZSCALE
EFLOAT(ib, 0.0f); // PA_CL_VPORT_ZOFFSET
- EREG(ib, PA_CL_VTE_CNTL, 0);
EREG(ib, PA_CL_VS_OUT_CNTL, 0);
EREG(ib, PA_CL_NANINF_CNTL, 0);
PACK0(ib, PA_CL_GB_VERT_CLIP_ADJ, 4);
commit 5f093357f18eb9bea641394ab86a92a1766d8f2e
Author: Gaetan Nadon <memsize at videotron.ca>
Date: Sat Jun 12 15:11:46 2010 -0400
COPYING: replace stub file with actual copyright notices
Signed-off-by: Gaetan Nadon <memsize at videotron.ca>
diff --git a/COPYING b/COPYING
index 7f33cbf..529cbf2 100644
--- a/COPYING
+++ b/COPYING
@@ -1,12 +1,129 @@
-This is a stub file. This package has not yet had its complete licensing
-information compiled. Please see the individual source files for details on
-your rights to use and modify this software.
+Copyright 1997 through 2004 by Marc Aurele La France (TSI @ UQV), tsi at xfree86.org
-Please submit updated COPYING files to the Xorg bugzilla:
+Permission to use, copy, modify, distribute, and sell this software and its
+documentation for any purpose is hereby granted without fee, provided that
+the above copyright notice appear in all copies and that both that copyright
+notice and this permission notice appear in supporting documentation, and
+that the name of Marc Aurele La France not be used in advertising or
+publicity pertaining to distribution of the software without specific,
+written prior permission. Marc Aurele La France makes no representations
+about the suitability of this software for any purpose. It is provided
+"as-is" without express or implied warranty.
-https://bugs.freedesktop.org/enter_bug.cgi?product=xorg
+MARC AURELE LA FRANCE DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE,
+INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO
+EVENT SHALL MARC AURELE LA FRANCE BE LIABLE FOR ANY SPECIAL, INDIRECT OR
+CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE,
+DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
+TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
+PERFORMANCE OF THIS SOFTWARE.
-All licensing questions regarding this software should be directed at the
-Xorg mailing list:
+Copyright (C) 2005 Bogdan D. bogdand at users.sourceforge.net
+Copyright (c) 1995-2003 by The XFree86 Project, Inc.
+
+Permission is hereby granted, free of charge, to any person obtaining a
+copy of this software and associated documentation files (the "Software"),
+to deal in the Software without restriction, including without limitation
+the rights to use, copy, modify, merge, publish, distribute, sublicense,
+and/or sell copies of the Software, and to permit persons to whom the
+Software is furnished to do so, subject to the following conditions:
+
+The above copyright notice and this permission notice shall be included in
+all copies or substantial portions of the Software.
+
+THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+OTHER DEALINGS IN THE SOFTWARE.
+
+Except as contained in this notice, the name of the copyright holder(s)
+and author(s) shall not be used in advertising or otherwise to promote
+the sale, use or other dealings in this Software without prior written
+authorization from the copyright holder(s) and author(s).
+
+Copyright 2006-2007 Advanced Micro Devices, Inc.
+Copyright 2007 Egbert Eich <eich at novell.com>
+Copyright 2007 Matthias Hopf <mhopf at novell.com>
+Copyright (C) 1999-2001 Brian Paul All Rights Reserved.
+Copyright 2007 Luc Verhaegen <lverhaegen at novell.com>
+
+Permission is hereby granted, free of charge, to any person obtaining a
+copy of this software and associated documentation files (the "Software"),
+to deal in the Software without restriction, including without limitation
+the rights to use, copy, modify, merge, publish, distribute, sublicense,
+and/or sell copies of the Software, and to permit persons to whom the
+Software is furnished to do so, subject to the following conditions:
+
+The above copyright notice and this permission notice shall be included in
+all copies or substantial portions of the Software.
+
+THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+OTHER DEALINGS IN THE SOFTWARE.
+
+Copyright 2007 Advanced Micro Devices, Inc.
+Copyright (C) 2008-2009 Advanced Micro Devices, Inc.
+Copyright 2004 Eric Anholt
+Copyright 2005 Eric Anholt
+Copyright 2000 ATI Technologies Inc., Markham, Ontario, and
+Copyright 2004 ATI Technologies Inc., Markham, Ontario
+Copyright (C) 2008-2009 Alexander Deucher
+Copyright 2008 Jérôme Glisse
+Copyright 2005 Benjamin Herrenschmidt
+Copyright 2008 Kristian Høgsberg
+Copyright (C) 2008-2009 Matthias Hopf
+Copyright (c) 2006 Itronix Inc.
+Copyright 2000 Precision Insight, Inc., Cedar Park, Texas.
+Copyright © 2007 Red Hat, Inc.
+Copyright © 2009 Red Hat, Inc.
+Copyright 2007 George Sapountzis
+Copyright 2002 Tungsten Graphics, Inc., Cedar Park, Texas.
+Copyright 2006 Tungsten Graphics, Inc.
+Copyright 2000 VA Linux Systems, Inc., Fremont, California.
+
+Permission is hereby granted, free of charge, to any person obtaining a
+copy of this software and associated documentation files (the "Software"),
+to deal in the Software without restriction, including without limitation
+the rights to use, copy, modify, merge, publish, distribute, sublicense,
+and/or sell copies of the Software, and to permit persons to whom the
+Software is furnished to do so, subject to the following conditions:
+
+The above copyright notice and this permission notice (including the next
+paragraph) shall be included in all copies or substantial portions of the
+Software.
+
+THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+SOFTWARE.
+
+Copyright © 2006 Keith Packard
+
+Permission to use, copy, modify, distribute, and sell this software and its
+documentation for any purpose is hereby granted without fee, provided that
+the above copyright notice appear in all copies and that both that copyright
+notice and this permission notice appear in supporting documentation, and
+that the name of the copyright holders not be used in advertising or
+publicity pertaining to distribution of the software without specific,
+written prior permission. The copyright holders make no representations
+about the suitability of this software for any purpose. It is provided "as
+is" without express or implied warranty.
+
+THE COPYRIGHT HOLDERS DISCLAIM ALL WARRANTIES WITH REGARD TO THIS SOFTWARE,
+INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO
+EVENT SHALL THE COPYRIGHT HOLDERS BE LIABLE FOR ANY SPECIAL, INDIRECT OR
+CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE,
+DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
+TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE
+OF THIS SOFTWARE.
-http://lists.freedesktop.org/mailman/listinfo/xorg
commit 0c2118586d3edeecc2473b5d685472df4b5e70fa
Author: Dave Airlie <airlied at redhat.com>
Date: Fri Jun 11 15:53:18 2010 +1000
radeon: fixup last fix, use CURSOR_WIDTH not RADEON_CURSOR_WIDTH.
diff --git a/src/radeon_kms.c b/src/radeon_kms.c
index b2c4064..3f77207 100644
--- a/src/radeon_kms.c
+++ b/src/radeon_kms.c
@@ -1008,7 +1008,7 @@ static Bool radeon_setup_kernel_mem(ScreenPtr pScreen)
#if X_BYTE_ORDER == X_BIG_ENDIAN
radeon_bo_set_tiling(info->cursor_bo[c], RADEON_TILING_SWAP_32BIT |
- RADEON_TILING_SURFACE, RADEON_CURSOR_WIDTH);
+ RADEON_TILING_SURFACE, CURSOR_WIDTH);
#endif
if (radeon_bo_map(info->cursor_bo[c], 1)) {
commit 9a117f768cb8261327fd3c324da9c98875785cc1
Author: Dave Airlie <airlied at redhat.com>
Date: Fri Jun 11 14:28:24 2010 +1000
radeon: set proper stride for cursor in tiling flags.
definitely incorrect, but hope it doesn't break anything.
Signed-off-by: Dave Airlie <airlied at redhat.com>
diff --git a/src/radeon_kms.c b/src/radeon_kms.c
index 317dacb..b2c4064 100644
--- a/src/radeon_kms.c
+++ b/src/radeon_kms.c
@@ -1008,7 +1008,7 @@ static Bool radeon_setup_kernel_mem(ScreenPtr pScreen)
#if X_BYTE_ORDER == X_BIG_ENDIAN
radeon_bo_set_tiling(info->cursor_bo[c], RADEON_TILING_SWAP_32BIT |
- RADEON_TILING_SURFACE, stride);
+ RADEON_TILING_SURFACE, RADEON_CURSOR_WIDTH);
#endif
if (radeon_bo_map(info->cursor_bo[c], 1)) {
commit b6346ede94f0d0b11ee04770cf52508cb0a5e6c6
Author: Dave Airlie <airlied at redhat.com>
Date: Thu Jun 10 20:13:58 2010 -0400
drmmode: fix big endian issue with properties.
On a power machine with an rn50, this was causing load detection to be turned off after the first X run, subsequent X runs would find nothing connected.
Signed-off-by: Dave Airlie <airlied at redhat.com>
diff --git a/src/drmmode_display.c b/src/drmmode_display.c
index 686de5e..c427bf1 100644
--- a/src/drmmode_display.c
+++ b/src/drmmode_display.c
@@ -722,6 +722,7 @@ drmmode_output_create_resources(xf86OutputPtr output)
if (drmmode_prop->flags & DRM_MODE_PROP_RANGE) {
INT32 range[2];
+ INT32 value = p->value;
p->num_atoms = 1;
p->atoms = xcalloc(p->num_atoms, sizeof(Atom));
@@ -739,7 +740,7 @@ drmmode_output_create_resources(xf86OutputPtr output)
"RRConfigureOutputProperty error, %d\n", err);
}
err = RRChangeOutputProperty(output->randr_output, p->atoms[0],
- XA_INTEGER, 32, PropModeReplace, 1, &p->value, FALSE, TRUE);
+ XA_INTEGER, 32, PropModeReplace, 1, &value, FALSE, TRUE);
if (err != 0) {
xf86DrvMsg(output->scrn->scrnIndex, X_ERROR,
"RRChangeOutputProperty error, %d\n", err);
commit 1971dc6d758dea13b9fb6d1c8f516c165628b5e5
Author: Alex Deucher <alexdeucher at gmail.com>
Date: Tue Jun 8 11:18:28 2010 -0400
radeon: fix rn50 cloning with kms
Since they only have one crtc sometimes the xserver doesn't assign
a crtc to one of the outputs even though both outputs have common modes
which results in only one monitor being enabled. Assign a crtc in
preinit so that both outputs light up.
Signed-off-by: Alex Deucher <alexdeucher at gmail.com>
diff --git a/src/radeon_kms.c b/src/radeon_kms.c
index 3c832ca..317dacb 100644
--- a/src/radeon_kms.c
+++ b/src/radeon_kms.c
@@ -517,6 +517,26 @@ Bool RADEONPreInit_KMS(ScrnInfoPtr pScrn, int flags)
else
pRADEONEnt->HasCRTC2 = TRUE;
+
+ /* fix up cloning on rn50 cards
+ * since they only have one crtc sometimes the xserver doesn't assign
+ * a crtc to one of the outputs even though both outputs have common modes
+ * which results in only one monitor being enabled. Assign a crtc here so
+ * that both outputs light up.
+ */
+ if (info->ChipFamily == CHIP_FAMILY_RV100 && !pRADEONEnt->HasCRTC2) {
+ xf86CrtcConfigPtr xf86_config = XF86_CRTC_CONFIG_PTR(pScrn);
+ int i;
+
+ for (i = 0; i < xf86_config->num_output; i++) {
+ xf86OutputPtr output = xf86_config->output[i];
+
+ /* XXX: double check crtc mode */
+ if ((output->probed_modes != NULL) && (output->crtc == NULL))
+ output->crtc = xf86_config->crtc[0];
+ }
+ }
+
{
struct drm_radeon_gem_info mminfo;
commit 426114b4a99d37b394efe3336968bb0ab9b6e9ae
Author: Dave Airlie <airlied at redhat.com>
Date: Tue Jun 8 11:34:35 2010 +1000
xv: fix Xv on M6/RV100 under KMS.
pRADEONEnt->HasCRTC2 wasn't setup under KMS.
Signed-off-by: Dave Airlie <airlied at redhat.com>
diff --git a/src/radeon_kms.c b/src/radeon_kms.c
index c6a3df7..3c832ca 100644
--- a/src/radeon_kms.c
+++ b/src/radeon_kms.c
@@ -512,6 +512,10 @@ Bool RADEONPreInit_KMS(ScrnInfoPtr pScrn, int flags)
goto fail;
}
+ if (info->drmmode.mode_res->count_crtcs == 1)
+ pRADEONEnt->HasCRTC2 = FALSE;
+ else
+ pRADEONEnt->HasCRTC2 = TRUE;
{
struct drm_radeon_gem_info mminfo;
commit f64bf0de8e2de7c1bf9cc0c614603dd23c9060ad
Author: Alex Deucher <alexdeucher at gmail.com>
Date: Thu Jun 3 14:48:21 2010 -0400
evergreen: explicitly disable accel on evergreen
Previously we relied on the drm not having accel enabled
to make sure evergreen used shadowfb, now we when we enable
accel in the drm, we need to make sure the ddx doesn't try
and use it until it's implemented.
Signed-off-by: Alex Deucher <alexdeucher at gmail.com>
diff --git a/src/radeon_kms.c b/src/radeon_kms.c
index e4c1c0b..c6a3df7 100644
--- a/src/radeon_kms.c
+++ b/src/radeon_kms.c
@@ -228,6 +228,7 @@ static Bool RADEONPreInitAccel_KMS(ScrnInfoPtr pScrn)
}
if (xf86ReturnOptValBool(info->Options, OPTION_NOACCEL, FALSE) ||
+ (info->ChipFamily >= CHIP_FAMILY_CEDAR) ||
(!RADEONIsAccelWorking(pScrn))) {
xf86DrvMsg(pScrn->scrnIndex, X_INFO,
"GPU accel disabled or not working, using shadowfb for KMS\n");
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