xf86-video-ati: Branch 'master'
Dave Airlie
airlied at kemper.freedesktop.org
Sun Aug 1 00:03:19 PDT 2010
src/Makefile.am | 2
src/r600_exa.c | 111 ++++--------------------
src/r600_state.h | 6 -
src/r600_textured_videofuncs.c | 3
src/r6xx_accel.c | 109 ------------------------
src/radeon.h | 4
src/radeon_exa.c | 33 -------
src/radeon_exa_render.c | 8 -
src/radeon_exa_shared.c | 186 +++++++++++++++++++++++++++++++++++++++++
src/radeon_exa_shared.h | 79 +++++++++++++++++
src/radeon_kms.c | 3
src/radeon_vbo.h | 13 +-
12 files changed, 302 insertions(+), 255 deletions(-)
New commits:
commit c79ce215a01b45fc63b483da167ae37ec7aefad6
Author: Dave Airlie <airlied at redhat.com>
Date: Sun Aug 1 16:51:48 2010 +1000
radeon/r600: restructure exa + vbo to provide more sharing
This is a precursor for r300/500 vbo support.
Signed-off-by: Dave Airlie <airlied at redhat.com>
diff --git a/src/Makefile.am b/src/Makefile.am
index 5750770..f53f958 100644
--- a/src/Makefile.am
+++ b/src/Makefile.am
@@ -53,7 +53,7 @@ RADEON_KMS_SRCS=radeon_dri2.c radeon_kms.c drmmode_display.c radeon_vbo.c
endif
if USE_EXA
-RADEON_EXA_SOURCES = radeon_exa.c r600_exa.c r6xx_accel.c r600_textured_videofuncs.c r600_shader.c
+RADEON_EXA_SOURCES = radeon_exa.c r600_exa.c r6xx_accel.c r600_textured_videofuncs.c r600_shader.c radeon_exa_shared.c
endif
AM_CFLAGS = \
diff --git a/src/r600_exa.c b/src/r600_exa.c
index 72c4ff8..b16c40f 100644
--- a/src/r600_exa.c
+++ b/src/r600_exa.c
@@ -38,44 +38,11 @@
#include "r600_shader.h"
#include "r600_reg.h"
#include "r600_state.h"
+#include "radeon_exa_shared.h"
#include "radeon_vbo.h"
-#define RADEON_TRACE_FALL 0
-#define RADEON_TRACE_DRAW 0
-
-#if RADEON_TRACE_FALL
-#define RADEON_FALLBACK(x) \
-do { \
- ErrorF("%s: ", __FUNCTION__); \
- ErrorF x; \
- return FALSE; \
-} while (0)
-#else
-#define RADEON_FALLBACK(x) return FALSE
-#endif
-
-extern PixmapPtr
-RADEONGetDrawablePixmap(DrawablePtr pDrawable);
-
/* #define SHOW_VERTEXES */
-# define RADEON_ROP3_ZERO 0x00000000
-# define RADEON_ROP3_DSa 0x00880000
-# define RADEON_ROP3_SDna 0x00440000
-# define RADEON_ROP3_S 0x00cc0000
-# define RADEON_ROP3_DSna 0x00220000
-# define RADEON_ROP3_D 0x00aa0000
-# define RADEON_ROP3_DSx 0x00660000
-# define RADEON_ROP3_DSo 0x00ee0000
-# define RADEON_ROP3_DSon 0x00110000
-# define RADEON_ROP3_DSxn 0x00990000
-# define RADEON_ROP3_Dn 0x00550000
-# define RADEON_ROP3_SDno 0x00dd0000
-# define RADEON_ROP3_Sn 0x00330000
-# define RADEON_ROP3_DSno 0x00bb0000
-# define RADEON_ROP3_DSan 0x00770000
-# define RADEON_ROP3_ONE 0x00ff0000
-
uint32_t RADEON_ROP[16] = {
RADEON_ROP3_ZERO, /* GXclear */
RADEON_ROP3_DSa, /* Gxand */
@@ -95,29 +62,6 @@ uint32_t RADEON_ROP[16] = {
RADEON_ROP3_ONE, /* GXset */
};
-static void R600VlineHelperClear(ScrnInfoPtr pScrn)
-{
- RADEONInfoPtr info = RADEONPTR(pScrn);
- struct radeon_accel_state *accel_state = info->accel_state;
-
- accel_state->vline_crtc = NULL;
- accel_state->vline_y1 = -1;
- accel_state->vline_y2 = 0;
-}
-
-static void R600VlineHelperSet(ScrnInfoPtr pScrn, int x1, int y1, int x2, int y2)
-{
- RADEONInfoPtr info = RADEONPTR(pScrn);
- struct radeon_accel_state *accel_state = info->accel_state;
-
- accel_state->vline_crtc = radeon_pick_best_crtc(pScrn, x1, x2, y1, y2);
- if (accel_state->vline_y1 == -1)
- accel_state->vline_y1 = y1;
- if (y1 < accel_state->vline_y1)
- accel_state->vline_y1 = y1;
- if (y2 > accel_state->vline_y2)
- accel_state->vline_y2 = y2;
-}
static Bool R600ValidPM(uint32_t pm, int bpp)
{
@@ -265,22 +209,9 @@ R600SetAccelState(ScrnInfoPtr pScrn,
return TRUE;
}
-#if defined(XF86DRM_MODE)
-static inline void radeon_add_pixmap(struct radeon_cs *cs, PixmapPtr pPix, int read_domains, int write_domain)
-{
- struct radeon_exa_pixmap_priv *driver_priv = exaGetPixmapDriverPrivate(pPix);
-
- radeon_cs_space_add_persistent_bo(cs, driver_priv->bo, read_domains, write_domain);
-}
-#endif
-
static void
R600DoneSolid(PixmapPtr pPix);
-static void
-R600DoneComposite(PixmapPtr pDst);
-
-
static Bool
R600PrepareSolid(PixmapPtr pPix, int alu, Pixel pm, Pixel fg)
{
@@ -329,7 +260,7 @@ R600PrepareSolid(PixmapPtr pPix, int alu, Pixel pm, Pixel fg)
CLEAR (ps_conf);
radeon_vbo_check(pScrn, 16);
- r600_cp_start(pScrn);
+ radeon_cp_start(pScrn);
set_default_state(pScrn, accel_state->ib);
@@ -445,7 +376,7 @@ R600PrepareSolid(PixmapPtr pPix, int alu, Pixel pm, Pixel fg)
sizeof(ps_alu_consts) / SQ_ALU_CONSTANT_offset, ps_alu_consts);
if (accel_state->vsync)
- R600VlineHelperClear(pScrn);
+ RADEONVlineHelperClear(pScrn);
return TRUE;
}
@@ -460,7 +391,7 @@ R600Solid(PixmapPtr pPix, int x1, int y1, int x2, int y2)
float *vb;
if (accel_state->vsync)
- R600VlineHelperSet(pScrn, x1, y1, x2, y2);
+ RADEONVlineHelperSet(pScrn, x1, y1, x2, y2);
vb = radeon_vbo_space(pScrn, 8);
@@ -510,7 +441,7 @@ R600DoPrepareCopy(ScrnInfoPtr pScrn)
CLEAR (ps_conf);
radeon_vbo_check(pScrn, 16);
- r600_cp_start(pScrn);
+ radeon_cp_start(pScrn);
set_default_state(pScrn, accel_state->ib);
@@ -797,7 +728,7 @@ R600PrepareCopy(PixmapPtr pSrc, PixmapPtr pDst,
R600DoPrepareCopy(pScrn);
if (accel_state->vsync)
- R600VlineHelperClear(pScrn);
+ RADEONVlineHelperClear(pScrn);
return TRUE;
}
@@ -816,7 +747,7 @@ R600Copy(PixmapPtr pDst,
return;
if (accel_state->vsync)
- R600VlineHelperSet(pScrn, dstX, dstY, dstX + w, dstY + h);
+ RADEONVlineHelperSet(pScrn, dstX, dstY, dstX + w, dstY + h);
if (accel_state->same_surface && accel_state->copy_area) {
uint32_t orig_offset, tmp_offset;
@@ -1468,7 +1399,7 @@ static Bool R600PrepareComposite(int op, PicturePtr pSrcPicture,
else
radeon_vbo_check(pScrn, 16);
- r600_cp_start(pScrn);
+ radeon_cp_start(pScrn);
set_default_state(pScrn, accel_state->ib);
@@ -1478,14 +1409,14 @@ static Bool R600PrepareComposite(int op, PicturePtr pSrcPicture,
if (!R600TextureSetup(pSrcPicture, pSrc, 0)) {
R600IBDiscard(pScrn, accel_state->ib);
- r600_vb_discard(pScrn);
+ radeon_vb_discard(pScrn);
return FALSE;
}
if (pMask) {
if (!R600TextureSetup(pMaskPicture, pMask, 1)) {
R600IBDiscard(pScrn, accel_state->ib);
- r600_vb_discard(pScrn);
+ radeon_vb_discard(pScrn);
return FALSE;
}
} else
@@ -1615,7 +1546,7 @@ static Bool R600PrepareComposite(int op, PicturePtr pSrcPicture,
END_BATCH();
if (accel_state->vsync)
- R600VlineHelperClear(pScrn);
+ RADEONVlineHelperClear(pScrn);
return TRUE;
}
@@ -1635,7 +1566,7 @@ static void R600Composite(PixmapPtr pDst,
srcX, srcY, maskX, maskY,dstX, dstY, w, h); */
if (accel_state->vsync)
- R600VlineHelperSet(pScrn, dstX, dstY, dstX + w, dstY + h);
+ RADEONVlineHelperSet(pScrn, dstX, dstY, dstX + w, dstY + h);
if (accel_state->msk_pic) {
@@ -1697,10 +1628,10 @@ static void R600DoneComposite(PixmapPtr pDst)
int vtx_size;
if (accel_state->vsync)
- cp_wait_vline_sync(pScrn, accel_state->ib, pDst,
- accel_state->vline_crtc,
- accel_state->vline_y1,
- accel_state->vline_y2);
+ cp_wait_vline_sync(pScrn, accel_state->ib, pDst,
+ accel_state->vline_crtc,
+ accel_state->vline_y1,
+ accel_state->vline_y2);
vtx_size = accel_state->msk_pic ? 24 : 16;
@@ -1797,7 +1728,7 @@ R600CopyToVRAM(ScrnInfoPtr pScrn,
}
R600IBDiscard(pScrn, scratch);
- r600_vb_discard(pScrn);
+ radeon_vb_discard(pScrn);
return TRUE;
}
@@ -1911,7 +1842,7 @@ R600DownloadFromScreen(PixmapPtr pSrc, int x, int y, int w, int h,
}
R600IBDiscard(pScrn, scratch);
- r600_vb_discard(pScrn);
+ radeon_vb_discard(pScrn);
return TRUE;
@@ -1994,7 +1925,7 @@ R600UploadToScreenCS(PixmapPtr pDst, int x, int y, int w, int h,
radeon_bo_unmap(scratch);
if (info->accel_state->vsync)
- R600VlineHelperSet(pScrn, x, y, x + w, y + h);
+ RADEONVlineHelperSet(pScrn, x, y, x + w, y + h);
/* blit from gart to vram */
R600DoPrepareCopy(pScrn);
@@ -2380,7 +2311,9 @@ R600DrawInit(ScreenPtr pScreen)
info->accel_state->dst_obj.bo = NULL;
info->accel_state->copy_area_bo = NULL;
info->accel_state->vb_start_op = -1;
- R600VlineHelperClear(pScrn);
+ info->accel_state->finish_op = r600_finish_op;
+ info->accel_state->verts_per_op = 3;
+ RADEONVlineHelperClear(pScrn);
#ifdef XF86DRM_MODE
radeon_vbo_init_lists(pScrn);
diff --git a/src/r600_state.h b/src/r600_state.h
index 43dc929..710ec6d 100644
--- a/src/r600_state.h
+++ b/src/r600_state.h
@@ -320,12 +320,6 @@ draw_immd(ScrnInfoPtr pScrn, drmBufPtr ib, draw_config_t *draw_conf, uint32_t *i
void
draw_auto(ScrnInfoPtr pScrn, drmBufPtr ib, draw_config_t *draw_conf);
-Bool
-r600_vb_get(ScrnInfoPtr pScrn);
-void
-r600_vb_discard(ScrnInfoPtr pScrn);
-int
-r600_cp_start(ScrnInfoPtr pScrn);
void r600_finish_op(ScrnInfoPtr pScrn, int vtx_size);
Bool
diff --git a/src/r600_textured_videofuncs.c b/src/r600_textured_videofuncs.c
index e75d9fe..9f91f6e 100644
--- a/src/r600_textured_videofuncs.c
+++ b/src/r600_textured_videofuncs.c
@@ -45,6 +45,7 @@
#include "damage.h"
+#include "radeon_exa_shared.h"
#include "radeon_vbo.h"
/* Parameters for ITU-R BT.601 and ITU-R BT.709 colour spaces
@@ -206,7 +207,7 @@ R600DisplayTexturedVideo(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv)
#endif
radeon_vbo_check(pScrn, 16);
- r600_cp_start(pScrn);
+ radeon_cp_start(pScrn);
set_default_state(pScrn, accel_state->ib);
diff --git a/src/r6xx_accel.c b/src/r6xx_accel.c
index 73f9462..8e8c1bf 100644
--- a/src/r6xx_accel.c
+++ b/src/r6xx_accel.c
@@ -39,6 +39,7 @@
#include "radeon_drm.h"
#include "radeon_vbo.h"
+#include "radeon_exa_shared.h"
/* we try and batch operations together under KMS -
but it doesn't work yet without misrendering */
@@ -85,34 +86,9 @@ void R600CPFlushIndirect(ScrnInfoPtr pScrn, drmBufPtr ib)
void R600IBDiscard(ScrnInfoPtr pScrn, drmBufPtr ib)
{
#if defined(XF86DRM_MODE)
- int ret;
RADEONInfoPtr info = RADEONPTR(pScrn);
if (info->cs) {
- if (info->accel_state->ib_reset_op) {
- /* if we have data just reset the CS and ignore the operation */
- info->cs->cdw = info->accel_state->ib_reset_op;
- info->accel_state->ib_reset_op = 0;
- return;
- }
- if (info->accel_state->vb_ptr) {
- info->accel_state->vb_ptr = NULL;
- }
-
- info->accel_state->vb_offset = 0;
- info->accel_state->vb_start_op = -1;
-
- if (CS_FULL(info->cs)) {
- radeon_cs_flush_indirect(pScrn);
- return;
- }
- radeon_cs_erase(info->cs);
- ret = radeon_cs_space_check(info->cs);
- if (ret)
- ErrorF("space check failed in flush\n");
- if (info->dri2.enabled) {
- info->accel_state->XInited3D = FALSE;
- info->accel_state->engineMode = EXA_ENGINEMODE_UNKNOWN;
- }
+ radeon_ib_discard(pScrn);
}
#endif
if (!ib) return;
@@ -1138,57 +1114,6 @@ draw_auto(ScrnInfoPtr pScrn, drmBufPtr ib, draw_config_t *draw_conf)
END_BATCH();
}
-Bool
-r600_vb_get(ScrnInfoPtr pScrn)
-{
- RADEONInfoPtr info = RADEONPTR(pScrn);
- struct radeon_accel_state *accel_state = info->accel_state;
-
- accel_state->vb_mc_addr = info->gartLocation + info->dri->bufStart +
- (accel_state->ib->idx*accel_state->ib->total)+
- (accel_state->ib->total / 2);
- accel_state->vb_total = (accel_state->ib->total / 2);
- accel_state->vb_ptr = (pointer)((char*)accel_state->ib->address +
- (accel_state->ib->total / 2));
- accel_state->vb_offset = 0;
- return TRUE;
-}
-
-void
-r600_vb_discard(ScrnInfoPtr pScrn)
-{
- RADEONInfoPtr info = RADEONPTR(pScrn);
-
- info->accel_state->vb_start_op = -1;
-}
-
-
-
-int
-r600_cp_start(ScrnInfoPtr pScrn)
-{
- RADEONInfoPtr info = RADEONPTR(pScrn);
- struct radeon_accel_state *accel_state = info->accel_state;
-
-#if defined(XF86DRM_MODE)
- if (info->cs) {
- if (CS_FULL(info->cs)) {
- radeon_cs_flush_indirect(pScrn);
- }
- accel_state->ib_reset_op = info->cs->cdw;
- accel_state->vb_start_op = accel_state->vb_offset;
- } else
-#endif
- {
- accel_state->ib = RADEONCPGetBuffer(pScrn);
- if (!r600_vb_get(pScrn)) {
- return -1;
- }
- accel_state->vb_start_op = accel_state->vb_offset;
- }
- return 0;
-}
-
void r600_finish_op(ScrnInfoPtr pScrn, int vtx_size)
{
RADEONInfoPtr info = RADEONPTR(pScrn);
@@ -1204,7 +1129,7 @@ void r600_finish_op(ScrnInfoPtr pScrn, int vtx_size)
if (accel_state->vb_offset == accel_state->vb_start_op) {
R600IBDiscard(pScrn, accel_state->ib);
- r600_vb_discard(pScrn);
+ radeon_vb_discard(pScrn);
return;
}
@@ -1260,31 +1185,3 @@ void r600_finish_op(ScrnInfoPtr pScrn, int vtx_size)
R600CPFlushIndirect(pScrn, accel_state->ib);
}
-void r600_vb_no_space(ScrnInfoPtr pScrn, int vert_size)
-{
- RADEONInfoPtr info = RADEONPTR(pScrn);
- struct radeon_accel_state *accel_state = info->accel_state;
-#ifdef XF86DRM_MODE
-
- if (info->cs) {
- if (accel_state->vb_bo) {
- if (accel_state->vb_start_op != accel_state->vb_offset) {
- r600_finish_op(pScrn, vert_size);
- accel_state->ib_reset_op = info->cs->cdw;
- }
-
- /* release the current VBO */
- radeon_vbo_put(pScrn);
- }
-
- /* get a new one */
- radeon_vbo_get(pScrn);
- return;
- }
-#endif
-
- if (accel_state->vb_start_op != -1) {
- r600_finish_op(pScrn, vert_size);
- r600_cp_start(pScrn);
- }
-}
diff --git a/src/radeon.h b/src/radeon.h
index 61f07ba..55d673a 100644
--- a/src/radeon.h
+++ b/src/radeon.h
@@ -721,7 +721,7 @@ struct radeon_accel_state {
uint32_t *draw_header;
unsigned vtx_count;
unsigned num_vtx;
-
+ unsigned verts_per_op;
Bool vsync;
drmBufPtr ib;
@@ -741,7 +741,7 @@ struct radeon_accel_state {
struct radeon_dma_bo bo_reserved;
Bool use_vbos;
#endif
-
+ void (*finish_op)(ScrnInfoPtr, int);
// shader storage
ExaOffscreenArea *shaders;
struct radeon_bo *shaders_bo;
diff --git a/src/radeon_exa.c b/src/radeon_exa.c
index d7fba65..7dd792e 100644
--- a/src/radeon_exa.c
+++ b/src/radeon_exa.c
@@ -42,6 +42,7 @@
#include "radeon_macros.h"
#include "radeon_probe.h"
#include "radeon_version.h"
+#include "radeon_exa_shared.h"
#include "xf86.h"
@@ -50,26 +51,6 @@
#define RINFO_FROM_SCREEN(pScr) ScrnInfoPtr pScrn = xf86Screens[pScr->myNum]; \
RADEONInfoPtr info = RADEONPTR(pScrn)
-#define RADEON_TRACE_FALL 0
-#define RADEON_TRACE_DRAW 0
-
-#if RADEON_TRACE_FALL
-#define RADEON_FALLBACK(x) \
-do { \
- ErrorF("%s: ", __FUNCTION__); \
- ErrorF x; \
- return FALSE; \
-} while (0)
-#else
-#define RADEON_FALLBACK(x) return FALSE
-#endif
-
-#if RADEON_TRACE_DRAW
-#define TRACE do { ErrorF("TRACE: %s\n", __FUNCTION__); } while(0)
-#else
-#define TRACE
-#endif
-
static struct {
int rop;
int pattern;
@@ -121,18 +102,6 @@ static __inline__ uint32_t F_TO_DW(float val)
}
-#ifdef XF86DRM_MODE
-
-static inline void radeon_add_pixmap(struct radeon_cs *cs, PixmapPtr pPix, int read_domains, int write_domain)
-{
- struct radeon_exa_pixmap_priv *driver_priv = exaGetPixmapDriverPrivate(pPix);
-
- radeon_cs_space_add_persistent_bo(cs, driver_priv->bo, read_domains, write_domain);
-}
-
-#endif /* XF86DRM_MODE */
-
-
/* Assumes that depth 15 and 16 can be used as depth 16, which is okay since we
* require src and dest datatypes to be equal.
*/
diff --git a/src/radeon_exa_render.c b/src/radeon_exa_render.c
index cf773b0..da72416 100644
--- a/src/radeon_exa_render.c
+++ b/src/radeon_exa_render.c
@@ -496,14 +496,6 @@ static Bool FUNC_NAME(R100TextureSetup)(PicturePtr pPict, PixmapPtr pPix,
#ifdef ONLY_ONCE
-PixmapPtr
-RADEONGetDrawablePixmap(DrawablePtr pDrawable)
-{
- if (pDrawable->type == DRAWABLE_WINDOW)
- return pDrawable->pScreen->GetWindowPixmap((WindowPtr)pDrawable);
- else
- return (PixmapPtr)pDrawable;
-}
static Bool R100CheckComposite(int op, PicturePtr pSrcPicture,
PicturePtr pMaskPicture, PicturePtr pDstPicture)
diff --git a/src/radeon_exa_shared.c b/src/radeon_exa_shared.c
new file mode 100644
index 0000000..7489a3d
--- /dev/null
+++ b/src/radeon_exa_shared.c
@@ -0,0 +1,186 @@
+/*
+ * Copyright 2005 Eric Anholt
+ * Copyright 2005 Benjamin Herrenschmidt
+ * Copyright 2008 Advanced Micro Devices, Inc.
+ * All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+ * SOFTWARE.
+ *
+ * Authors:
+ * Eric Anholt <anholt at FreeBSD.org>
+ * Zack Rusin <zrusin at trolltech.com>
+ * Benjamin Herrenschmidt <benh at kernel.crashing.org>
+ * Alex Deucher <alexander.deucher at amd.com>
+ * Matthias Hopf <mhopf at suse.de>
+ */
+#ifdef HAVE_CONFIG_H
+#include "config.h"
+#endif
+
+#include "radeon.h"
+#include "radeon_reg.h"
+#include "r600_reg.h"
+#ifdef XF86DRI
+#include "radeon_drm.h"
+#endif
+#include "radeon_macros.h"
+#include "radeon_probe.h"
+#include "radeon_version.h"
+#include "radeon_vbo.h"
+
+PixmapPtr
+RADEONGetDrawablePixmap(DrawablePtr pDrawable)
+{
+ if (pDrawable->type == DRAWABLE_WINDOW)
+ return pDrawable->pScreen->GetWindowPixmap((WindowPtr)pDrawable);
+ else
+ return (PixmapPtr)pDrawable;
+}
+
+void RADEONVlineHelperClear(ScrnInfoPtr pScrn)
+{
+ RADEONInfoPtr info = RADEONPTR(pScrn);
+ struct radeon_accel_state *accel_state = info->accel_state;
+
+ accel_state->vline_crtc = NULL;
+ accel_state->vline_y1 = -1;
+ accel_state->vline_y2 = 0;
+}
+
+void RADEONVlineHelperSet(ScrnInfoPtr pScrn, int x1, int y1, int x2, int y2)
+{
+ RADEONInfoPtr info = RADEONPTR(pScrn);
+ struct radeon_accel_state *accel_state = info->accel_state;
+
+ accel_state->vline_crtc = radeon_pick_best_crtc(pScrn, x1, x2, y1, y2);
+ if (accel_state->vline_y1 == -1)
+ accel_state->vline_y1 = y1;
+ if (y1 < accel_state->vline_y1)
+ accel_state->vline_y1 = y1;
+ if (y2 > accel_state->vline_y2)
+ accel_state->vline_y2 = y2;
+}
+
+static Bool radeon_vb_get(ScrnInfoPtr pScrn)
+{
+ RADEONInfoPtr info = RADEONPTR(pScrn);
+ struct radeon_accel_state *accel_state = info->accel_state;
+
+ accel_state->vb_mc_addr = info->gartLocation + info->dri->bufStart +
+ (accel_state->ib->idx*accel_state->ib->total)+
+ (accel_state->ib->total / 2);
+ accel_state->vb_total = (accel_state->ib->total / 2);
+ accel_state->vb_ptr = (pointer)((char*)accel_state->ib->address +
+ (accel_state->ib->total / 2));
+ accel_state->vb_offset = 0;
+ return TRUE;
+}
+
+void radeon_vb_discard(ScrnInfoPtr pScrn)
+{
+ RADEONInfoPtr info = RADEONPTR(pScrn);
+
+ info->accel_state->vb_start_op = -1;
+}
+
+int radeon_cp_start(ScrnInfoPtr pScrn)
+{
+ RADEONInfoPtr info = RADEONPTR(pScrn);
+ struct radeon_accel_state *accel_state = info->accel_state;
+
+#if defined(XF86DRM_MODE)
+ if (info->cs) {
+ if (CS_FULL(info->cs)) {
+ radeon_cs_flush_indirect(pScrn);
+ }
+ accel_state->ib_reset_op = info->cs->cdw;
+ accel_state->vb_start_op = accel_state->vb_offset;
+ } else
+#endif
+ {
+ accel_state->ib = RADEONCPGetBuffer(pScrn);
+ if (!radeon_vb_get(pScrn)) {
+ return -1;
+ }
+ accel_state->vb_start_op = accel_state->vb_offset;
+ }
+ return 0;
+}
+
+void radeon_vb_no_space(ScrnInfoPtr pScrn, int vert_size)
+{
+ RADEONInfoPtr info = RADEONPTR(pScrn);
+ struct radeon_accel_state *accel_state = info->accel_state;
+
+ if (info->cs) {
+ if (accel_state->vb_bo) {
+ if (accel_state->vb_start_op != accel_state->vb_offset) {
+ accel_state->finish_op(pScrn, vert_size);
+ accel_state->ib_reset_op = info->cs->cdw;
+ }
+
+ /* release the current VBO */
+ radeon_vbo_put(pScrn);
+ }
+ /* get a new one */
+ radeon_vbo_get(pScrn);
+ return;
+ }
+
+ if (accel_state->vb_start_op != -1) {
+ accel_state->finish_op(pScrn, vert_size);
+ radeon_cp_start(pScrn);
+ }
+ return;
+}
+
+void radeon_ib_discard(ScrnInfoPtr pScrn)
+{
+ RADEONInfoPtr info = RADEONPTR(pScrn);
+ int ret;
+
+ if (info->accel_state->ib_reset_op) {
+ /* if we have data just reset the CS and ignore the operation */
+ info->cs->cdw = info->accel_state->ib_reset_op;
+ info->accel_state->ib_reset_op = 0;
+ goto out;
+ }
+
+ info->accel_state->vb_offset = 0;
+ info->accel_state->vb_start_op = -1;
+
+ if (CS_FULL(info->cs)) {
+ radeon_cs_flush_indirect(pScrn);
+ return;
+ }
+ radeon_cs_erase(info->cs);
+ ret = radeon_cs_space_check_with_bo(info->cs,
+ info->accel_state->vb_bo,
+ RADEON_GEM_DOMAIN_GTT, 0);
+ if (ret)
+ ErrorF("space check failed in flush\n");
+
+ out:
+ if (info->dri2.enabled) {
+ info->accel_state->XInited3D = FALSE;
+ info->accel_state->engineMode = EXA_ENGINEMODE_UNKNOWN;
+ }
+
+}
diff --git a/src/radeon_exa_shared.h b/src/radeon_exa_shared.h
new file mode 100644
index 0000000..286886d
--- /dev/null
+++ b/src/radeon_exa_shared.h
@@ -0,0 +1,79 @@
+/*
+ * Copyright 2005 Eric Anholt
+ * Copyright 2005 Benjamin Herrenschmidt
+ * Copyright 2008 Advanced Micro Devices, Inc.
+ * All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+ * SOFTWARE.
+ *
+ * Authors:
+ * Eric Anholt <anholt at FreeBSD.org>
+ * Zack Rusin <zrusin at trolltech.com>
+ * Benjamin Herrenschmidt <benh at kernel.crashing.org>
+ * Alex Deucher <alexander.deucher at amd.com>
+ * Matthias Hopf <mhopf at suse.de>
+ */
+#ifndef RADEON_EXA_SHARED_H
+
+#define RADEON_EXA_SHARED_H
+
+extern PixmapPtr RADEONGetDrawablePixmap(DrawablePtr pDrawable);
+
+extern void RADEONVlineHelperClear(ScrnInfoPtr pScrn);
+extern void RADEONVlineHelperSet(ScrnInfoPtr pScrn, int x1, int y1, int x2, int y2);
+
+
+#define RADEON_TRACE_FALL 0
+#define RADEON_TRACE_DRAW 0
+
+#if RADEON_TRACE_FALL
+#define RADEON_FALLBACK(x) \
+do { \
+ ErrorF("%s: ", __FUNCTION__); \
+ ErrorF x; \
+ return FALSE; \
+} while (0)
+#else
+#define RADEON_FALLBACK(x) return FALSE
+#endif
+
+#if RADEON_TRACE_DRAW
+#define TRACE do { ErrorF("TRACE: %s\n", __FUNCTION__); } while(0)
+#else
+#define TRACE
+#endif
+
+#ifdef XF86DRM_MODE
+static inline void radeon_add_pixmap(struct radeon_cs *cs, PixmapPtr pPix, int read_domains, int write_domain)
+{
+ struct radeon_exa_pixmap_priv *driver_priv = exaGetPixmapDriverPrivate(pPix);
+
+ radeon_cs_space_add_persistent_bo(cs, driver_priv->bo, read_domains, write_domain);
+}
+
+#endif /* XF86DRM_MODE */
+
+extern void radeon_vb_discard(ScrnInfoPtr pScrn);
+extern int radeon_cp_start(ScrnInfoPtr pScrn);
+extern void radeon_vb_no_space(ScrnInfoPtr pScrn, int vert_size);
+extern void radeon_vbo_done_composite(PixmapPtr pDst);
+
+extern void radeon_ib_discard(ScrnInfoPtr pScrn);
+#endif
diff --git a/src/radeon_kms.c b/src/radeon_kms.c
index c0d2ae6..772be8f 100644
--- a/src/radeon_kms.c
+++ b/src/radeon_kms.c
@@ -82,9 +82,6 @@ void radeon_cs_flush_indirect(ScrnInfoPtr pScrn)
if (!info->cs->cdw)
return;
- if (info->accel_state->vb_ptr)
- info->accel_state->vb_ptr = NULL;
-
/* release the current VBO so we don't block on mapping it later */
if (info->accel_state->vb_offset && info->accel_state->vb_bo) {
radeon_vbo_put(pScrn);
diff --git a/src/radeon_vbo.h b/src/radeon_vbo.h
index a8c70b3..b505f66 100644
--- a/src/radeon_vbo.h
+++ b/src/radeon_vbo.h
@@ -2,7 +2,7 @@
#ifndef RADEON_VBO_H
#define RADEON_VBO_H
-extern void r600_vb_no_space(ScrnInfoPtr pScrn, int vert_size);
+extern void radeon_vb_no_space(ScrnInfoPtr pScrn, int vert_size);
extern void radeon_vbo_init_lists(ScrnInfoPtr pScrn);
extern void radeon_vbo_free_lists(ScrnInfoPtr pScrn);
extern void radeon_vbo_flush_bos(ScrnInfoPtr pScrn);
@@ -14,8 +14,8 @@ static inline void radeon_vbo_check(ScrnInfoPtr pScrn, int vert_size)
RADEONInfoPtr info = RADEONPTR(pScrn);
struct radeon_accel_state *accel_state = info->accel_state;
- if ((accel_state->vb_offset + (3 * vert_size)) > accel_state->vb_total) {
- r600_vb_no_space(pScrn, vert_size);
+ if ((accel_state->vb_offset + (accel_state->verts_per_op * vert_size)) > accel_state->vb_total) {
+ radeon_vb_no_space(pScrn, vert_size);
}
}
@@ -28,9 +28,8 @@ radeon_vbo_space(ScrnInfoPtr pScrn, int vert_size)
/* we've ran out of space in the vertex buffer - need to get a
new one */
- if ((accel_state->vb_offset + (3 * vert_size)) > accel_state->vb_total) {
- r600_vb_no_space(pScrn, vert_size);
- }
+ radeon_vbo_check(pScrn, vert_size);
+
accel_state->vb_op_vert_size = vert_size;
#if defined(XF86DRM_MODE)
if (info->cs) {
@@ -56,7 +55,7 @@ static inline void radeon_vbo_commit(ScrnInfoPtr pScrn)
RADEONInfoPtr info = RADEONPTR(pScrn);
struct radeon_accel_state *accel_state = info->accel_state;
- accel_state->vb_offset += 3 * accel_state->vb_op_vert_size;
+ accel_state->vb_offset += accel_state->verts_per_op * accel_state->vb_op_vert_size;
}
#endif
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