[Mesa-dev] [PATCH 1/3] amd/addrlib: add support for VegaM

Marek Olšák maraeo at gmail.com
Tue Apr 17 22:14:51 UTC 2018


From: Marek Olšák <marek.olsak at amd.com>

---
 src/amd/addrlib/amdgpu_asic_addr.h |  2 ++
 src/amd/addrlib/r800/ciaddrlib.cpp |  5 +++++
 src/amd/addrlib/r800/siaddrlib.cpp | 33 ++++++++++++++++++++++++++++++
 src/amd/addrlib/r800/siaddrlib.h   |  1 +
 4 files changed, 41 insertions(+)

diff --git a/src/amd/addrlib/amdgpu_asic_addr.h b/src/amd/addrlib/amdgpu_asic_addr.h
index d7232ba14a2..b4b8aecd42d 100644
--- a/src/amd/addrlib/amdgpu_asic_addr.h
+++ b/src/amd/addrlib/amdgpu_asic_addr.h
@@ -72,20 +72,21 @@
 #define AMDGPU_KALINDI_RANGE    0x81, 0xA1
 #define AMDGPU_GODAVARI_RANGE   0xA1, 0xFF
 
 #define AMDGPU_ICELAND_RANGE    0x01, 0x14
 #define AMDGPU_TONGA_RANGE      0x14, 0x28
 #define AMDGPU_FIJI_RANGE       0x3C, 0x50
 
 #define AMDGPU_POLARIS10_RANGE  0x50, 0x5A
 #define AMDGPU_POLARIS11_RANGE  0x5A, 0x64
 #define AMDGPU_POLARIS12_RANGE  0x64, 0x6E
+#define AMDGPU_VEGAM_RANGE      0x6E, 0xFF
 
 #define AMDGPU_CARRIZO_RANGE    0x01, 0x21
 #define AMDGPU_BRISTOL_RANGE    0x10, 0x21
 #define AMDGPU_STONEY_RANGE     0x61, 0xFF
 
 #define AMDGPU_VEGA10_RANGE     0x01, 0x14
 #define AMDGPU_VEGA12_RANGE     0x14, 0x28
 
 #define AMDGPU_RAVEN_RANGE      0x01, 0x81
 
@@ -110,20 +111,21 @@
 #define ASICREV_IS_KALINDI(r)          ASICREV_IS(r, KALINDI)
 #define ASICREV_IS_KALINDI_GODAVARI(r) ASICREV_IS(r, GODAVARI)
 
 #define ASICREV_IS_ICELAND_M(r)        ASICREV_IS(r, ICELAND)
 #define ASICREV_IS_TONGA_P(r)          ASICREV_IS(r, TONGA)
 #define ASICREV_IS_FIJI_P(r)           ASICREV_IS(r, FIJI)
 
 #define ASICREV_IS_POLARIS10_P(r)      ASICREV_IS(r, POLARIS10)
 #define ASICREV_IS_POLARIS11_M(r)      ASICREV_IS(r, POLARIS11)
 #define ASICREV_IS_POLARIS12_V(r)      ASICREV_IS(r, POLARIS12)
+#define ASICREV_IS_VEGAM_P(r)          ASICREV_IS(r, VEGAM)
 
 #define ASICREV_IS_CARRIZO(r)          ASICREV_IS(r, CARRIZO)
 #define ASICREV_IS_CARRIZO_BRISTOL(r)  ASICREV_IS(r, BRISTOL)
 #define ASICREV_IS_STONEY(r)           ASICREV_IS(r, STONEY)
 
 #define ASICREV_IS_VEGA10_M(r)         ASICREV_IS(r, VEGA10)
 #define ASICREV_IS_VEGA10_P(r)         ASICREV_IS(r, VEGA10)
 #define ASICREV_IS_VEGA12_P(r)         ASICREV_IS(r, VEGA12)
 #define ASICREV_IS_VEGA12_p(r)         ASICREV_IS(r, VEGA12)
 
diff --git a/src/amd/addrlib/r800/ciaddrlib.cpp b/src/amd/addrlib/r800/ciaddrlib.cpp
index 1b982c5c08b..3c5e29f8695 100644
--- a/src/amd/addrlib/r800/ciaddrlib.cpp
+++ b/src/amd/addrlib/r800/ciaddrlib.cpp
@@ -394,20 +394,21 @@ ChipFamily CiLib::HwlConvertChipFamily(
             m_settings.isKalindi    = ASICREV_IS_KALINDI(uChipRevision);
             break;
         case FAMILY_VI:
             m_settings.isVolcanicIslands = 1;
             m_settings.isIceland         = ASICREV_IS_ICELAND_M(uChipRevision);
             m_settings.isTonga           = ASICREV_IS_TONGA_P(uChipRevision);
             m_settings.isFiji            = ASICREV_IS_FIJI_P(uChipRevision);
             m_settings.isPolaris10       = ASICREV_IS_POLARIS10_P(uChipRevision);
             m_settings.isPolaris11       = ASICREV_IS_POLARIS11_M(uChipRevision);
             m_settings.isPolaris12       = ASICREV_IS_POLARIS12_V(uChipRevision);
+            m_settings.isVegaM           = ASICREV_IS_VEGAM_P(uChipRevision);
             family = ADDR_CHIP_FAMILY_VI;
             break;
         case FAMILY_CZ:
             m_settings.isCarrizo         = 1;
             m_settings.isVolcanicIslands = 1;
             family = ADDR_CHIP_FAMILY_VI;
             break;
         default:
             ADDR_ASSERT(!"This should be a unexpected Fusion");
             break;
@@ -463,20 +464,24 @@ BOOL_32 CiLib::HwlInitGlobalParams(
         m_pipes = 2;
     }
     else if (m_settings.isFiji)
     {
         m_pipes = 16;
     }
     else if (m_settings.isPolaris11 || m_settings.isPolaris12)
     {
         m_pipes = 4;
     }
+    else if (m_settings.isVegaM)
+    {
+        m_pipes = 16;
+    }
 
     if (valid)
     {
         valid = InitTileSettingTable(pRegValue->pTileConfig, pRegValue->noOfEntries);
     }
     if (valid)
     {
         valid = InitMacroTileCfgTable(pRegValue->pMacroTileConfig, pRegValue->noOfMacroEntries);
     }
 
diff --git a/src/amd/addrlib/r800/siaddrlib.cpp b/src/amd/addrlib/r800/siaddrlib.cpp
index 3c17a7aa8d7..bc009f5aff0 100644
--- a/src/amd/addrlib/r800/siaddrlib.cpp
+++ b/src/amd/addrlib/r800/siaddrlib.cpp
@@ -604,20 +604,43 @@ ADDR_E_RETURNCODE SiLib::ComputePipeEquation(
             pXor1[3] = y5;
             pEquation->numBits = 4;
             break;
         default:
             ADDR_UNHANDLED_CASE();
             pEquation->numBits = 0;
             retCode = ADDR_NOTSUPPORTED;
             break;
     }
 
+    if (m_settings.isVegaM && (pEquation->numBits == 4))
+    {
+        ADDR_CHANNEL_SETTING addeMsb = pAddr[0];
+        ADDR_CHANNEL_SETTING xor1Msb = pXor1[0];
+        ADDR_CHANNEL_SETTING xor2Msb = pXor2[0];
+
+        pAddr[0] = pAddr[1];
+        pXor1[0] = pXor1[1];
+        pXor2[0] = pXor2[1];
+
+        pAddr[1] = pAddr[2];
+        pXor1[1] = pXor1[2];
+        pXor2[1] = pXor2[2];
+
+        pAddr[2] = pAddr[3];
+        pXor1[2] = pXor1[3];
+        pXor2[2] = pXor2[3];
+
+        pAddr[3] = addeMsb;
+        pXor1[3] = xor1Msb;
+        pXor2[3] = xor2Msb;
+    }
+
     for (UINT_32 i = 0; i < pEquation->numBits; i++)
     {
         if (pAddr[i].value == 0)
         {
             if (pXor1[i].value == 0)
             {
                 pAddr[i].value = pXor2[i].value;
             }
             else
             {
@@ -747,20 +770,30 @@ UINT_32 SiLib::ComputePipeFromCoord(
             pipeBit0 = x3 ^ y3 ^ x4;
             pipeBit1 = x4 ^ y4;
             pipeBit2 = x5 ^ y6;
             pipeBit3 = x6 ^ y5;
             numPipes = 16;
             break;
         default:
             ADDR_UNHANDLED_CASE();
             break;
     }
+
+    if (m_settings.isVegaM && (numPipes == 16))
+    {
+        UINT_32 pipeMsb = pipeBit0;
+        pipeBit0 = pipeBit1;
+        pipeBit1 = pipeBit2;
+        pipeBit2 = pipeBit3;
+        pipeBit3 = pipeMsb;
+    }
+
     pipe = pipeBit0 | (pipeBit1 << 1) | (pipeBit2 << 2) | (pipeBit3 << 3);
 
     UINT_32 microTileThickness = Thickness(tileMode);
 
     //
     // Apply pipe rotation for the slice.
     //
     switch (tileMode)
     {
         case ADDR_TM_3D_TILED_THIN1:    //fall through thin
diff --git a/src/amd/addrlib/r800/siaddrlib.h b/src/amd/addrlib/r800/siaddrlib.h
index 9c879fe6c36..d363df8d641 100644
--- a/src/amd/addrlib/r800/siaddrlib.h
+++ b/src/amd/addrlib/r800/siaddrlib.h
@@ -80,20 +80,21 @@ struct SiChipSettings
     UINT_32 isHawaii          : 1;
 
     // VI
     UINT_32 isVolcanicIslands : 1;
     UINT_32 isIceland         : 1;
     UINT_32 isTonga           : 1;
     UINT_32 isFiji            : 1;
     UINT_32 isPolaris10       : 1;
     UINT_32 isPolaris11       : 1;
     UINT_32 isPolaris12       : 1;
+    UINT_32 isVegaM           : 1;
     // VI fusion
     UINT_32 isCarrizo         : 1;
 };
 
 /**
 ****************************************************************************************************
 * @brief This class is the SI specific address library
 *        function set.
 ****************************************************************************************************
 */
-- 
2.17.0



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