[Mesa-dev] [PATCH v3 042/104] i965: Move nir_lower_deref_instrs to right before locals_to_regs

[Jason Ekstrand]

---
 src/intel/compiler/brw_nir.c            | 2 ++
 src/mesa/drivers/dri/i965/brw_program.c | 5 ++---
 2 files changed, 4 insertions(+), 3 deletions(-)

diff --git a/src/intel/compiler/brw_nir.c b/src/intel/compiler/brw_nir.c
index cf994ac..4fc6cae 100644
--- a/src/intel/compiler/brw_nir.c
+++ b/src/intel/compiler/brw_nir.c
@@ -740,6 +740,8 @@ brw_postprocess_nir(nir_shader *nir, const struct brw_compiler *compiler,
    OPT(nir_opt_dce);
    OPT(nir_opt_move_comparisons);
 
+   OPT(nir_lower_deref_instrs, ~0);
+
    OPT(nir_lower_locals_to_regs);
 
    if (unlikely(debug_enabled)) {
diff --git a/src/mesa/drivers/dri/i965/brw_program.c b/src/mesa/drivers/dri/i965/brw_program.c
index 8159bb7..06172c4 100644
--- a/src/mesa/drivers/dri/i965/brw_program.c
+++ b/src/mesa/drivers/dri/i965/brw_program.c
@@ -79,10 +79,10 @@ brw_create_nir(struct brw_context *brw,
    if (shader_prog) {
       if (shader_prog->_LinkedShaders[stage]->spirv_data) {
          nir = _mesa_spirv_to_nir(ctx, shader_prog, stage, options);
-         nir_lower_deref_instrs(nir, ~0);
+         nir_lower_deref_instrs(nir, nir_lower_texture_derefs);
       } else {
          nir = glsl_to_nir(shader_prog, stage, options);
-         nir_lower_deref_instrs(nir, ~0);
+         nir_lower_deref_instrs(nir, nir_lower_texture_derefs);
       }
       assert (nir);
 
@@ -93,7 +93,6 @@ brw_create_nir(struct brw_context *brw,
                  nir_shader_get_entrypoint(nir), true, false);
    } else {
       nir = prog_to_nir(prog, options);
-      nir_lower_deref_instrs(nir, ~0);
       NIR_PASS_V(nir, nir_lower_regs_to_ssa); /* turn registers into SSA */
    }
    nir_validate_shader(nir);
-- 
2.5.0.400.gff86faf