[Mesa-dev] [PATCH 1/3] i965: Check the INTEL_USE_NIR environment variable once at context creation

[Jordan Justen]

On 2015-04-02 20:56:15, Jason Ekstrand wrote:
> ---
>  src/mesa/drivers/dri/i965/brw_context.c | 10 +++++++++-
>  src/mesa/drivers/dri/i965/brw_fs.cpp    |  4 ++--
>  src/mesa/drivers/dri/i965/brw_vec4.cpp  |  4 +++-
>  3 files changed, 14 insertions(+), 4 deletions(-)
> 
> diff --git a/src/mesa/drivers/dri/i965/brw_context.c b/src/mesa/drivers/dri/i965/brw_context.c
> index 84818f0..f0de711 100644
> --- a/src/mesa/drivers/dri/i965/brw_context.c
> +++ b/src/mesa/drivers/dri/i965/brw_context.c
> @@ -560,6 +560,12 @@ brw_initialize_context_constants(struct brw_context *brw)
>        .lower_ffma = true,
>     };
>  
> +   bool use_nir_default[MESA_SHADER_STAGES];
> +   use_nir_default[MESA_SHADER_VERTEX] = false;
> +   use_nir_default[MESA_SHADER_GEOMETRY] = false;
> +   use_nir_default[MESA_SHADER_FRAGMENT] = false;
> +   use_nir_default[MESA_SHADER_COMPUTE] = false;

How about memset to 0 for now to make sure all stages are set? We can
add use_nir_default[MESA_SHADER_FOO] = true; after the memset to
update the default for the shader stage.

> +
>     /* We want the GLSL compiler to emit code that uses condition codes */
>     for (int i = 0; i < MESA_SHADER_STAGES; i++) {
>        ctx->Const.ShaderCompilerOptions[i].MaxIfDepth = brw->gen < 6 ? 16 : UINT_MAX;
> @@ -573,7 +579,9 @@ brw_initialize_context_constants(struct brw_context *brw)
>          (i == MESA_SHADER_FRAGMENT);
>        ctx->Const.ShaderCompilerOptions[i].EmitNoIndirectUniform = false;
>        ctx->Const.ShaderCompilerOptions[i].LowerClipDistance = true;
> -      ctx->Const.ShaderCompilerOptions[i].NirOptions = &nir_options;
> +
> +      if (brw_env_var_as_boolean("INTEL_USE_NIR", use_nir_default[i]))

This will read the var more once per shader type, right? Maybe read
INTEL_USE_NIR once before the loop?

Series Reviewed-by: Jordan Justen <jordan.l.justen at intel.com>

> +         ctx->Const.ShaderCompilerOptions[i].NirOptions = &nir_options;
>     }
>  
>     ctx->Const.ShaderCompilerOptions[MESA_SHADER_VERTEX].OptimizeForAOS = true;
> diff --git a/src/mesa/drivers/dri/i965/brw_fs.cpp b/src/mesa/drivers/dri/i965/brw_fs.cpp
> index 9c2ccce..1db2d3b 100644
> --- a/src/mesa/drivers/dri/i965/brw_fs.cpp
> +++ b/src/mesa/drivers/dri/i965/brw_fs.cpp
> @@ -3861,7 +3861,7 @@ fs_visitor::run_vs()
>     if (INTEL_DEBUG & DEBUG_SHADER_TIME)
>        emit_shader_time_begin();
>  
> -   if (brw_env_var_as_boolean("INTEL_USE_NIR", false)) {
> +   if (brw->ctx.Const.ShaderCompilerOptions[MESA_SHADER_VERTEX].NirOptions) {
>        emit_nir_code();
>     } else {
>        foreach_in_list(ir_instruction, ir, shader->base.ir) {
> @@ -3934,7 +3934,7 @@ fs_visitor::run_fs()
>        /* Generate FS IR for main().  (the visitor only descends into
>         * functions called "main").
>         */
> -      if (brw_env_var_as_boolean("INTEL_USE_NIR", false)) {
> +      if (brw->ctx.Const.ShaderCompilerOptions[MESA_SHADER_FRAGMENT].NirOptions) {
>           emit_nir_code();
>        } else if (shader) {
>           foreach_in_list(ir_instruction, ir, shader->base.ir) {
> diff --git a/src/mesa/drivers/dri/i965/brw_vec4.cpp b/src/mesa/drivers/dri/i965/brw_vec4.cpp
> index 480e50c..ef2fd40 100644
> --- a/src/mesa/drivers/dri/i965/brw_vec4.cpp
> +++ b/src/mesa/drivers/dri/i965/brw_vec4.cpp
> @@ -1823,7 +1823,9 @@ brw_vs_emit(struct brw_context *brw,
>     if (unlikely(INTEL_DEBUG & DEBUG_VS))
>        brw_dump_ir("vertex", prog, &shader->base, &c->vp->program.Base);
>  
> -   if (brw->scalar_vs && (prog || brw_env_var_as_boolean("INTEL_USE_NIR", false))) {
> +   if (brw->scalar_vs &&
> +       (prog ||
> +        brw->ctx.Const.ShaderCompilerOptions[MESA_SHADER_VERTEX].NirOptions)) {
>        fs_visitor v(brw, mem_ctx, &c->key, prog_data, prog, &c->vp->program, 8);
>        if (!v.run_vs()) {
>           if (prog) {
> -- 
> 2.3.4
> 
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