Tiling on i915-class hardware

[Eric Anholt]

On Thu, 2009-03-05 at 23:33 +0200, Vasily Khoruzhick wrote:
> On Thursday 05 March 2009 10:12:11 you wrote:
> > Hi, I've just tested i915 tiling in 2 ram configurations:
> >
> > 512mb, single channel: tiling works perfectly, no performance issues with
> > tiling enabled
> > 512mb + 512mb dual channel interleaved: When tiling is enabled it
> > introduces performance regression, when I enable tiling 3D performance is
> > low. With tiling disabled I hit this bug:
> > http://bugs.freedesktop.org/show_bug.cgi?id=19738
> >
> > So, the problem exists at least for configurations with 2 memory modules in
> > dual channel interleaved mode, and it doesn't exist in single channel mode.
> >
> > I can provide any additional info if you need.
> >
> > Regards
> > Vasily
> 
> Ok, I've traced a little bit i915_gem_detect_bit_6_swizzle() and found out 
> that my memory controller configuration is one with bit 17 XORed in; cite from 
> i915_gem_tiling.c comments:
> 
>   * When bit 17 is XORed in, we simply refuse to tile at all.  Bit
>   * 17 is not just a page offset, so as we page an objet out and back in,
>   * individual pages in it will have different bit 17 addresses, resulting in
>   * each 64 bytes being swapped with its neighbor!
> 
> So as far as I understand it's a reason why tiling is not working on my 
> hardware (945gm, with 2 memory modules, each one is 512mb). Is there any way 
> to disable XORing/do anything to get full 3D performance?

No, your BIOS sets it up, and it's a property of your northbridge.
We've got a plan for a workaround, but it's a bit complicated and not
done yet.

-- 
Eric Anholt
eric at anholt.net                         eric.anholt at intel.com


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