[PATCH 2/5] handle extenion for detail timing block

[Adam Jackson]

On Mon, 2008-11-17 at 16:39 +0800, ling.ma at intel.com wrote:

> @@ -72,30 +76,6 @@ xf86MonitorSupportsReducedBlanking(xf86MonPtr DDC)
>   * Quirks to work around broken EDID data from various monitors.
>   */
>  
> -typedef enum {
> -    DDC_QUIRK_NONE = 0,
> -    /* First detailed mode is bogus, prefer largest mode at 60hz */
> -    DDC_QUIRK_PREFER_LARGE_60 = 1 << 0,
> -    /* 135MHz clock is too high, drop a bit */
> -    DDC_QUIRK_135_CLOCK_TOO_HIGH = 1 << 1,
> -    /* Prefer the largest mode at 75 Hz */
> -    DDC_QUIRK_PREFER_LARGE_75 = 1 << 2,
> -    /* Convert detailed timing's horizontal from units of cm to mm */
> -    DDC_QUIRK_DETAILED_H_IN_CM = 1 << 3,
> -    /* Convert detailed timing's vertical from units of cm to mm */
> -    DDC_QUIRK_DETAILED_V_IN_CM = 1 << 4,
> -    /* Detailed timing descriptors have bogus size values, so just take the
> -     * maximum size and use that.
> -     */
> -    DDC_QUIRK_DETAILED_USE_MAXIMUM_SIZE = 1 << 5,
> -    /* Monitor forgot to set the first detailed is preferred bit. */
> -    DDC_QUIRK_FIRST_DETAILED_PREFERRED = 1 << 6,
> -    /* use +hsync +vsync for detailed mode */
> -    DDC_QUIRK_DETAILED_SYNC_PP = 1 << 7,
> -    /* Force single-link DVI bandwidth limit */
> -    DDC_QUIRK_DVI_SINGLE_LINK = 1 << 8,
> -} ddc_quirk_t;
> -
>  static Bool quirk_prefer_large_60 (int scrnIndex, xf86MonPtr DDC)
>  {
>      /* Belinea 10 15 55 */

This hunk should be part of the previous patch, I suspect.

- ajax
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