i915 backlight failure on resume with 2.6.27

James Bottomley James.Bottomley at HansenPartnership.com
Tue Dec 2 11:28:50 PST 2008

On Mon, 2008-12-01 at 11:42 -0600, James Bottomley wrote:
> You probably remember the system, it's my fujitsu P7120 lifebook with
> the funny backlight wiring.
> Previously, suspend/resume was made to work by saving the PCI state
> including the legacy backlight register setting (and worked just fine
> when invoked with a hal quirk).
> On FC9, with the 2.6.26 fedora kernels, hal no longer does anything and
> relies on the i915 kernel driver.  This was perfectly fine, except that
> the backlight was now being restored to full brightness on resume rather
> than the setting on resume.  The other annoyance was that VT consoles
> were now lost on resume (switching to them produces a black screen,
> although switching back to vt7 where X is running is fine).
> As of the 2.6.27 fedora kernels, the backlight is now off on resume,
> which is even more annoying.  It can be turned on by doing a VT switch,
> although all the console VTs are still blank, so there looks to be some
> bug in the i915 driver that crept in between 2.6.26 and 2.6.27.

Jesse asked for the reg dump from xf86-video-intel-2.4.3, so here it is:

(II): DumpRegsBegin
(II):    VCLK_DIVISOR_VGA0: 0x00031108 (n = 3, m1 = 17, m2 = 8)
(II):    VCLK_DIVISOR_VGA1: 0x00031406 (n = 3, m1 = 20, m2 = 6)
(II):        VCLK_POST_DIV: 0x00800080 (vga0 p1 = 2, p2 = 4, vga1 p1 = 2, p2 = 2)
(II):            DPLL_TEST: 0x00010001 ()
(II):         CACHE_MODE_0: 0x00006820
(II):              D_STATE: 0x00000000
(II):        DSPCLK_GATE_D: 0x00001000 (clock gates disabled: DPLUNIT)
(II):       RENCLK_GATE_D1: 0x00000000
(II):       RENCLK_GATE_D2: 0x00000000
(II):                SDVOB: 0x00300000 (disabled, pipe A, stall disabled, not detected, SDVO mult 1)
(II):                SDVOC: 0x00300000 (disabled, pipe A, stall disabled, not detected, SDVO mult 1)
(II):              SDVOUDI: 0x000000ff
(II):               DSPARB: 0x00001d9c
(II):               DSPFW1: 0x00000000
(II):               DSPFW2: 0x00000000
(II):               DSPFW3: 0x00000000
(II):                 ADPA: 0x40008c18 (disabled, pipe B, +hsync, +vsync)
(II):                 LVDS: 0xc0200300 (enabled, pipe B, 18 bit, 1 channel)
(II):                 DVOA: 0x00000000 (disabled, pipe A, no stall, -hsync, -vsync)
(II):                 DVOB: 0x00300000 (disabled, pipe A, no stall, -hsync, -vsync)
(II):                 DVOC: 0x00300000 (disabled, pipe A, no stall, -hsync, -vsync)
(II):          DVOA_SRCDIM: 0x00000000
(II):          DVOB_SRCDIM: 0x00000000
(II):          DVOC_SRCDIM: 0x00000000
(II):           PP_CONTROL: 0x00000001 (power target: on)
(II):            PP_STATUS: 0xc0000008 (on, ready, sequencing idle)
(II):         PFIT_CONTROL: 0x00000008
(II):      PFIT_PGM_RATIOS: 0x00000000
(II):      PORT_HOTPLUG_EN: 0x00000000
(II):    PORT_HOTPLUG_STAT: 0x00000000
(II):             DSPACNTR: 0xd9000000 (enabled, pipe B)
(II):           DSPASTRIDE: 0x00002000 (8192 bytes)
(II):              DSPAPOS: 0x00000000 (0, 0)
(II):             DSPASIZE: 0x02ff04ff (1280, 768)
(II):             DSPABASE: 0x01000000
(II):             DSPASURF: 0x00000000
(II):          DSPATILEOFF: 0x00000000
(II):            PIPEACONF: 0x00000000 (disabled, single-wide)
(II):             PIPEASRC: 0x027f01df (640, 480)
(II):            PIPEASTAT: 0x00000000 (status:)
(II):                 FPA0: 0x00031108 (n = 3, m1 = 17, m2 = 8)
(II):                 FPA1: 0x00031108 (n = 3, m1 = 17, m2 = 8)
(II):               DPLL_A: 0x04800000 (disabled, non-dvo, VGA, default clock, DAC/serial mode, p1 = 8, p2 = 10)
(II):            DPLL_A_MD: 0x00000000
(II):             HTOTAL_A: 0x031f027f (640 active, 800 total)
(II):             HBLANK_A: 0x03170287 (648 start, 792 end)
(II):              HSYNC_A: 0x02ef028f (656 start, 752 end)
(II):             VTOTAL_A: 0x020c01df (480 active, 525 total)
(II):             VBLANK_A: 0x020401e7 (488 start, 517 end)
(II):              VSYNC_A: 0x01eb01e9 (490 start, 492 end)
(II):            BCLRPAT_A: 0x00000000
(II):         VSYNCSHIFT_A: 0x00000000
(II):             DSPBCNTR: 0x49000000 (disabled, pipe B)
(II):           DSPBSTRIDE: 0x00000400 (1024 bytes)
(II):              DSPBPOS: 0x00000000 (0, 0)
(II):             DSPBSIZE: 0x018f02cf (720, 400)
(II):             DSPBBASE: 0x00000000
(II):             DSPBSURF: 0x00000000
(II):          DSPBTILEOFF: 0x00000000
(II):            PIPEBCONF: 0x80000000 (enabled, single-wide)
(II):             PIPEBSRC: 0x04ff02ff (1280, 768)
(II):                 FPB0: 0x00021006 (n = 2, m1 = 16, m2 = 6)
(II):                 FPB1: 0x00031108 (n = 3, m1 = 17, m2 = 8)
(II):               DPLL_B: 0x98020000 (enabled, non-dvo, default clock, LVDS mode, p1 = 2, p2 = 14)
(II):            DPLL_B_MD: 0x00000000
(II):             HTOTAL_B: 0x069704ff (1280 active, 1688 total)
(II):             HBLANK_B: 0x069704ff (1280 start, 1688 end)
(II):              HSYNC_B: 0x059f052f (1328 start, 1440 end)
(II):             VTOTAL_B: 0x032102ff (768 active, 802 total)
(II):             VBLANK_B: 0x032102ff (768 start, 802 end)
(II):              VSYNC_B: 0x03080302 (771 start, 777 end)
(II):            BCLRPAT_B: 0x00000000
(II):         VSYNCSHIFT_B: 0x00000000
(II):    VCLK_DIVISOR_VGA0: 0x00031108
(II):    VCLK_DIVISOR_VGA1: 0x00031406
(II):        VCLK_POST_DIV: 0x00800080
(II):             VGACNTRL: 0x80000000 (disabled)
(II):               TV_CTL: 0x00000000
(II):               TV_DAC: 0x00000000
(II):             TV_CSC_Y: 0x00000000
(II):            TV_CSC_Y2: 0x00000000
(II):             TV_CSC_U: 0x00000000
(II):            TV_CSC_U2: 0x00000000
(II):             TV_CSC_V: 0x00000000
(II):            TV_CSC_V2: 0x00000000
(II):         TV_CLR_KNOBS: 0x00000000
(II):         TV_CLR_LEVEL: 0x00000000
(II):           TV_H_CTL_1: 0x00000000
(II):           TV_H_CTL_2: 0x00000000
(II):           TV_H_CTL_3: 0x00000000
(II):           TV_V_CTL_1: 0x00000000
(II):           TV_V_CTL_2: 0x00000000
(II):           TV_V_CTL_3: 0x00000000
(II):           TV_V_CTL_4: 0x00000000
(II):           TV_V_CTL_5: 0x00000000
(II):           TV_V_CTL_6: 0x00000000
(II):           TV_V_CTL_7: 0x00000000
(II):          TV_SC_CTL_1: 0x00000000
(II):          TV_SC_CTL_2: 0x00000000
(II):          TV_SC_CTL_3: 0x00000000
(II):           TV_WIN_POS: 0x00000000
(II):          TV_WIN_SIZE: 0x00000000
(II):      TV_FILTER_CTL_1: 0x00000000
(II):      TV_FILTER_CTL_2: 0x00000000
(II):      TV_FILTER_CTL_3: 0x00000000
(II):        TV_CC_CONTROL: 0x00000000
(II):           TV_CC_DATA: 0x00000000
(II):          TV_H_LUMA_0: 0x00000000
(II):         TV_H_LUMA_59: 0x00000000
(II):        TV_H_CHROMA_0: 0x00000000
(II):       TV_H_CHROMA_59: 0x00000000
(II):         FBC_CFB_BASE: 0x00000000
(II):          FBC_LL_BASE: 0x00000000
(II):          FBC_CONTROL: 0x00000000
(II):          FBC_COMMAND: 0x00000000
(II):           FBC_STATUS: 0x20000000
(II):         FBC_CONTROL2: 0x00000000
(II):        FBC_FENCE_OFF: 0x00000000
(II):          FBC_MOD_NUM: 0x00000000
(II):              MI_MODE: 0x00000200
(II):         MI_ARB_STATE: 0x00000040
(II):       MI_RDRET_STATE: 0x00000000
(II):              ECOSKPD: 0x00000307
(II):                 DP_B: 0x00000000
(II):       DPB_AUX_CH_CTL: 0x00000000
(II):     DPB_AUX_CH_DATA1: 0x00000000
(II):     DPB_AUX_CH_DATA2: 0x00000000
(II):     DPB_AUX_CH_DATA3: 0x00000000
(II):     DPB_AUX_CH_DATA4: 0x00000000
(II):     DPB_AUX_CH_DATA5: 0x00000000
(II):                 DP_C: 0x00000000
(II):       DPC_AUX_CH_CTL: 0x00000000
(II):     DPC_AUX_CH_DATA1: 0x00000000
(II):     DPC_AUX_CH_DATA2: 0x00000000
(II):     DPC_AUX_CH_DATA3: 0x00000000
(II):     DPC_AUX_CH_DATA4: 0x00000000
(II):     DPC_AUX_CH_DATA5: 0x00000000
(II):                 DP_D: 0x00000000
(II):       DPD_AUX_CH_CTL: 0x00000000
(II):     DPD_AUX_CH_DATA1: 0x00000000
(II):     DPD_AUX_CH_DATA2: 0x00000000
(II):     DPD_AUX_CH_DATA3: 0x00000000
(II):     DPD_AUX_CH_DATA4: 0x00000000
(II):     DPD_AUX_CH_DATA5: 0x00000000
(II): pipe A dot 25200 n 3 m1 17 m2 8 p1 8 p2 10
(II): pipe B dot 84000 n 2 m1 16 m2 6 p1 2 p2 14
(II): DumpRegsEnd


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