915gm/945gm/XAA lockup with gray blocks when switching video mode
Peter Clifton
pcjc2 at cam.ac.uk
Fri Oct 12 12:27:41 PDT 2007
On Fri, 2007-10-12 at 05:58 -0700, Jesse Barnes wrote:
> On Thursday, October 11, 2007 9:43 pm Bryce Harrington wrote:
> > I tried adding a usleep(20) inside the loops, but the issue still
> > came up (seemed like it took more attempts than normal to trigger,
> > but that is hard to judge).
> >
> > I'll also try replacing the pallet restore loops.
> >
> > Could you also explain a bit more about what this pallet is?
>
> Err, I meant palette. :) It's just a guess, but it seems like banging
> on those registers causes problems for some people, but only some of
> the time. This may be because you just happen to hit the issue during
> those PIOs or because the PIOs themselves are causing a problem
> somehow. The latter might be due to the associated pipe being off,
> which would disable the registers, possibly causing a GPU crash when
> you wrote them (the fact that your crashes go away 100% points to this
> possibility). The former would be some other problem probably caused
> by earlier code that we just happen to hit when doing the palette
> restoration... putting delays before palette restore might confirm or
> deny that theory.
Incidentally, I note there are no posting reads in the hardware restore
path. I have a patch which adds these for the various regs which are
posted elsewhere in the driver. It didn't help fix any of the crashes,
so I dropped it from the patch I was playing with for Ubuntu.
This might not apply (as I hacked it out of a more messy debug patch),
but this was along the lines of what I tried. (NB. the posting reads and
sleep when programming the VCLK were just a test I added):
Index: xserver-xorg-video-intel-2.1.1/src/i830_driver.c
===================================================================
--- xserver-xorg-video-intel-2.1.1.orig/src/i830_driver.c 2007-10-12 08:39:48.000000000 +0100
+++ xserver-xorg-video-intel-2.1.1/src/i830_driver.c 2007-10-12 08:41:13.000000000 +0100
@@ -1892,8 +1904,10 @@
}
i830WaitForVblank(pScrn);
- if (IS_MOBILE(pI830) && !IS_I830(pI830))
+ if (IS_MOBILE(pI830) && !IS_I830(pI830)) {
OUTREG(LVDS, pI830->saveLVDS);
+ POSTING_READ(LVDS);
+ }
if (!IS_I830(pI830) && !IS_845G(pI830))
OUTREG(PFIT_CONTROL, pI830->savePFIT_CONTROL);
@@ -1901,16 +1915,21 @@
if (pI830->saveDPLL_A & DPLL_VCO_ENABLE)
{
OUTREG(DPLL_A, pI830->saveDPLL_A & ~DPLL_VCO_ENABLE);
+ POSTING_READ(DPLL_A);
usleep(150);
}
OUTREG(FPA0, pI830->saveFPA0);
OUTREG(FPA1, pI830->saveFPA1);
OUTREG(DPLL_A, pI830->saveDPLL_A);
+ POSTING_READ(DPLL_A);
usleep(150);
- if (IS_I965G(pI830))
+ if (IS_I965G(pI830)) {
OUTREG(DPLL_A_MD, pI830->saveDPLL_A_MD);
- else
+ POSTING_READ(DPLL_A_MD);
+ } else {
OUTREG(DPLL_A, pI830->saveDPLL_A);
+ POSTING_READ(DPLL_A);
+ }
usleep(150);
OUTREG(HTOTAL_A, pI830->saveHTOTAL_A);
@@ -1926,12 +1945,17 @@
OUTREG(DSPAPOS, pI830->saveDSPAPOS);
OUTREG(PIPEASRC, pI830->savePIPEASRC);
OUTREG(DSPABASE, pI830->saveDSPABASE);
- if (IS_I965G(pI830))
+ POSTING_READ(DSPABASE);
+ if (IS_I965G(pI830)) {
OUTREG(DSPASURF, pI830->saveDSPASURF);
+ POSTING_READ(DSPASURF);
+ }
OUTREG(PIPEACONF, pI830->savePIPEACONF);
+ POSTING_READ(PIPEACONF);
i830WaitForVblank(pScrn);
OUTREG(DSPACNTR, pI830->saveDSPACNTR);
OUTREG(DSPABASE, INREG(DSPABASE));
+ POSTING_READ(DSPABASE);
i830WaitForVblank(pScrn);
if(xf86_config->num_crtc == 2)
@@ -1939,16 +1963,21 @@
if (pI830->saveDPLL_B & DPLL_VCO_ENABLE)
{
OUTREG(DPLL_B, pI830->saveDPLL_B & ~DPLL_VCO_ENABLE);
+ POSTING_READ(DPLL_B);
usleep(150);
}
OUTREG(FPB0, pI830->saveFPB0);
OUTREG(FPB1, pI830->saveFPB1);
OUTREG(DPLL_B, pI830->saveDPLL_B);
+ POSTING_READ(DPLL_B);
usleep(150);
- if (IS_I965G(pI830))
+ if (IS_I965G(pI830)) {
OUTREG(DPLL_B_MD, pI830->saveDPLL_B_MD);
- else
+ POSTING_READ(DPLL_B_MD);
+ } else {
OUTREG(DPLL_B, pI830->saveDPLL_B);
+ POSTING_READ(DPLL_B);
+ }
usleep(150);
OUTREG(HTOTAL_B, pI830->saveHTOTAL_B);
@@ -1963,12 +1992,17 @@
OUTREG(DSPBPOS, pI830->saveDSPBPOS);
OUTREG(PIPEBSRC, pI830->savePIPEBSRC);
OUTREG(DSPBBASE, pI830->saveDSPBBASE);
- if (IS_I965G(pI830))
+ POSTING_READ(DSPBBASE);
+ if (IS_I965G(pI830)) {
OUTREG(DSPBSURF, pI830->saveDSPBSURF);
+ POSTING_READ(DSPBSURF);
+ }
OUTREG(PIPEBCONF, pI830->savePIPEBCONF);
+ POSTING_READ(PIPEBCONF);
i830WaitForVblank(pScrn);
OUTREG(DSPBCNTR, pI830->saveDSPBCNTR);
OUTREG(DSPBBASE, INREG(DSPBBASE));
+ POSTING_READ(DSPBBASE);
i830WaitForVblank(pScrn);
}
@@ -1981,8 +2015,14 @@
OUTREG(VGACNTRL, pI830->saveVGACNTRL);
+ /* For good measure, POSTING_READ THESE TOO */
OUTREG(VCLK_DIVISOR_VGA0, pI830->saveVCLK_DIVISOR_VGA0);
+ POSTING_READ(VCLK_DIVISOR_VGA0);
OUTREG(VCLK_DIVISOR_VGA1, pI830->saveVCLK_DIVISOR_VGA1);
+ POSTING_READ(VCLK_DIVISOR_VGA1);
OUTREG(VCLK_POST_DIV, pI830->saveVCLK_POST_DIV);
+ POSTING_READ(VCLK_POST_DIV);
+ /* For good measure, sleep a little here */
+ usleep(150);
for(i = 0; i < 256; i++) {
Best wishes,
--
Peter Clifton
Electrical Engineering Division,
Engineering Department,
University of Cambridge,
9, JJ Thomson Avenue,
Cambridge
CB3 0FA
Tel: +44 (0)7729 980173 - (No signal in the lab!)
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