Intel GMA 900 (915G) - interlaced modes?
keithp at keithp.com
Wed Jan 3 18:02:12 PST 2007
On Thu, 2007-01-04 at 02:00 +0100, Krzysztof Halasa wrote:
> I just want to move from old EPIA-M which has problems with TV field
> parity and can't do VGA->SCART RGB due to lack of interlaced modes.
> I'm thinking about buying something cheap like MSI Hetis with GMA900
> but it would have to do interlaced modes (I assume with 2x pixel
> clock, something like PAL 1440x576i with hardware scaling from
> 720x576 YUV etc).
Note that 915GM/945GM have built-in TV encoders that can do component
video up to 1080p, so you might look for something like that.
Alternatively, desktop boxes with PCIE slots can use a chrontel-based
SDVO TV out card.
The advantage of the built-in encoder is that the register definitions
are already fairly completely described in the driver header files,
while the SDVO ones remain locked up in unpublished documentation.
> I know there are specialized TV (S-VIDEO) encoders but SCART RGB
> would be much better in terms of quality (tested with Radeon+RGB
> vs. EPIA with "noscale") and stability.
I don't know what the quality differences would be, although it's hard
to imagine component not losing something over pure RGB.
> Back to the headers...
> grep -ir interlace .|grep h shows something like:
> #define SDVO_DTD_DTD_FLAG_INTERLACED (1 << 7)
> #define SDVO_PREFERRED_INPUT_TIMING_FLAGS_INTERLACED (1 << 0)
That's just for SDVO cards, which you aren't looking at using I assume.
Interlacing is a function of the pipe (crtc), not the output, but it
looks like we didn't put the interlace definitions into the header file:
#define PIPECONF_PROGRESSIVE (0 << 21)
#define PIPECONF_INTERLACE_W_FIELD_INDICATION (6 << 21)
#define PIPECONF_INTERLACE_FIELD_0_ONLY (7 << 21)
The only other mention of interlaced modes is that the vertical timing
values count lines per field, not lines per frame and ignore the two
half lines in interlaced modes that use half lines. You can set
interlaced mode on either pipe using the same value in the pipe
configuration register (PIPEACONF or PIPEBCONF).
> Perhaps I'm missing something?
Yes, the definitions for enabling interlacing were missing from the
header file. We're trying to make those complete, but there are a lot of
> Of course I can try to set 1024x768 32 bpp 87Hz(I) mode with BIOS
> and look for register values but will the BIOS let me set it?
It depends on your BIOS. You might want to give it a try as that will
make the precise vertical timing values clear.
keith.packard at intel.com
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