i915 interlaced (PAL TV) VGA output

[Krzysztof Halasa]

Hi,

Just updated to recent git, I'm using the attached patch to enable
interlaced VGA output on i915 (hand-edited, tabs dropped, two first
"chunks" probably not needed).

ModeLine "PAL" 27  1440 1467 1583 1728  576 580 600 622 \
	-hsync -vsync interlace # visible lines 16 - 540

The 13.5 MHz pixclock isn't possible here, I just double clock and
X resolution.

Problems:
a) 3D overlay doesn't sync to vertical retrace -> unusable for video,
   heavy distortion
b) 2D overlay seems to sync to vertical retrace. However, it also
   does something to the video stream (lines), reducing vertical
   resolution. It seems I'm getting 288 lines (pairs) out of 576.
   Obviously I'm trying to do full PAL 720x576 -> 1440x576 (or to
   720x576, same effect).
   Is the reduced vertical resolution caused by interlaced CRTC
   settings?
c) Normal X11 output (1440x576) - no vertical retrace sync, fields
   change slowly because of small clock differences (almost usable).

Can the 2D (non-textured) overlay be programmed for 1:1
(or rather 2(X):1(Y)) scaling, to avoid reducing Y resolution?

And/or: can the X11 output (application) be synchronized to
vertical retrace? Something like double buffering inside the X
server and swapping buffers on IRQ would work.

--- a/src/i830_crt.c
+++ b/src/i830_crt.c
@@ -426,7 +433,7 @@ i830_crt_init(ScrnInfoPtr pScrn)
                               (1 << I830_OUTPUT_DVO_TMDS));
     
     output->driver_private = i830_output;
-    output->interlaceAllowed = FALSE;
+    output->interlaceAllowed = TRUE;
     output->doubleScanAllowed = FALSE;
 
     /* Set up the DDC bus. */
--- a/src/i830_display.c
+++ b/src/i830_display.c
@@ -481,7 +519,7 @@ i830_pipe_a_require_activate (ScrnInfoPtr scrn)
        return FALSE;
     if (crtc->enabled)
        return FALSE;
-    xf86SetModeCrtc (&mode, INTERLACE_HALVE_V);
+    xf86SetModeCrtc (&mode, 0);
     crtc->funcs->mode_set (crtc, &mode, &mode, 0, 0);
     crtc->funcs->dpms (crtc, DPMSModeOn);
     return TRUE;
@@ -848,8 +887,16 @@ i830_output_commit (xf86OutputPtr output)
 
 static Bool
 i830_crtc_mode_fixup(xf86CrtcPtr crtc, DisplayModePtr mode,
-                    DisplayModePtr adjusted_mode)
+                    DisplayModePtr ajd_mode)
 {
+    if (mode->Flags & V_INTERLACE) {
+       mode->CrtcVDisplay = ajd_mode->CrtcVDisplay = mode->VDisplay;
+       mode->CrtcVSyncStart = ajd_mode->CrtcVSyncStart = mode->VSyncStart;
+       mode->CrtcVSyncEnd = ajd_mode->CrtcVSyncEnd = mode->VSyncEnd;
+       mode->CrtcVBlankStart = ajd_mode->CrtcVBlankStart = mode->CrtcVDisplay;
+       mode->CrtcVBlankEnd = ajd_mode->CrtcVBlankEnd = mode->VTotal;
+       mode->CrtcVTotal = ajd_mode->CrtcVTotal = mode->VTotal;
+    }
     return TRUE;
 }
 
@@ -1206,6 +1283,12 @@ i830_crtc_mode_set(xf86CrtcPtr crtc, DisplayModePtr mode,
     /* Wait for the clocks to stabilize. */
     usleep(150);
 
+    if (adjusted_mode->Flags & V_INTERLACE) {
+       pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
+       xf86DrvMsg(pScrn->scrnIndex, X_WARNING, "khc PIPECONF_INTERLACE\n");
+    } else
+       pipeconf &= ~PIPECONF_INTERLACE_W_FIELD_INDICATION;
+
     OUTREG(htot_reg, (adjusted_mode->CrtcHDisplay - 1) |
        ((adjusted_mode->CrtcHTotal - 1) << 16));
     OUTREG(hblank_reg, (adjusted_mode->CrtcHBlankStart - 1) |
-- 
Krzysztof Halasa