More advanced power savings (rev. the DPMS extension).

Jay Cotton Jay.Cotton at Sun.COM
Wed Jul 26 12:54:06 PDT 2006

Jim Gettys wrote:

>Problem statement
>We have a display that is new: it is possible the chip driving
>the panel to take over panel update from the processor.  We can save
>significant power if, while displaying an idle screen, we power down the
>processor's video driver logic, and even more power if we power down the
>graphics processor itself.  To resynchronize the display will take a
>couple frame times, so for highly interactive scenes, this behavior is
>not desirable; but when the screen is idle for any significant length of
>time, it is.
>Hard-wiring these values into the X server seems like a poor plan; the
>latencies of powering up a GPU will vary (it can take time to stabilize
>clocks and another power domain on graphics chips), and it will likely
>usually take of order 2 frame times (and hardware interrupt driver
>support) to transfer control of screen refresh back to the processor,
>and such transitions may vary, depending on the hardware.
>I expect it is likely such displays and power controllable GPU's will
>become much more common in the future.
Odd coincidence.  I just got email from our EStar rep.  He says the new MOU
v 4 will be requiring some kind of FBPM code to achieve compliance. 

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