radeon, apertures & memory mapping

[Benjamin Herrenschmidt]

> > That shouldn't matter the page brought in would be for a speculative
> > read and never accessed. It should just fall out of the cache and not
> > be written back. There is only one cachable mapping. In this model
> > writes are always followed by a flush before telling the GPU to access
> > the memory that has just been written.
> 
> What about this scenario?
> 
> Speculative read -> AGP master writes new data -> CPU has invalid data in 
> cache :(

First, we must be very careful with AGP master writes. I don't know if
we do a lot of them currently, but I know a collection of north bridges
that do not support them.

(Which is interesting, that means that if we want to copy something out
of video memory, we can't write it to AGP memory and then read it, we
need to actually do the blit from the CPU, good to know for our memory
manager. That also means that we have a problem if the video memory
isn't entirely accessible by the CPU ...)

That's something we should probably think about doing properly: Have a
list of AGP "issues" (errata ?) bits that are communicated by the AGP
host driver to the DRM.

At least all the early Apple AGP bridges don't do writes, and I remember
we have trouble with a few x86 ones as well. There are also issues when
a single AGP burst crosses a page boundary, and other things like that.

Ben.