[Xorg] The big multiconsole nasty

Jesse Barnes jbarnes at engr.sgi.com
Mon Jul 12 06:51:41 PDT 2004

On Monday, July 12, 2004 5:30 am, Egbert Eich wrote:
> Jesse Barnes writes:
>  > On Tuesday, July 6, 2004 9:36 am, Jon Smirl wrote:
>  > > --- John Dennis <jdennis at redhat.com> wrote:
>  > > > bus topology and that VGA routing is correct. Unlike the current
>  > >
>  > > You can't make the assumptions about VGA routing. When secondary video
>  > > cards are reset by running their ROM, at the very least they enable
>  > > their VGA support. Sometimes they remap the bridges too.
>  > >
>  > > We need kernel support for:
>  > > 1) disabling all VGA devices
>  > > 2) setting one VGA device active and get the bus routed to it
>  >
>  > This is possible, but also points out a deficiency in the current X
>  > server's idea of I/O ports.  I spoke with John Dennis about this a few
>  > weeks ago, but it seems to me that we should either:
>  >
>  >   o make the in/out routines take full pointers for the port address
>  > value
> This is already done. All addresses in the code are already constructed
> by using  base+offset.

In the arch specific in/out routines you mean?  I see lots of lines like 
inb(0x3c8) in various drivers and other code...

>  >     - or -
>  >   o pass a PCI tag to them so that the platform code can figure out
>  > where to route the I/O
> I also had a similar idea years ago. However I dropped it again:
> How about the latencies introduced when each IO operation has to
> verify that it is routed correctly?

in/out is pretty slow already, and is only used at startup time, afaict.  Most 
code just does memory reads/writes to register space doesn't it?

>  > As it stands, the X server's platform code has to assume one, global,
>  > I/O port base address...
> Not true any more. Take a look at the AXP and PPC code. Possibly also the
> IA64 code.

Yeah, I'm looking at the ia64 stuff, it's still missing the necessary support.  
It looks like ppc is still limited to doing legacy I/O (like the above inb) 
to one bus.

> On these platforms PIO is 'redirected' to MMIO and each bus has its
> distinct range in the MMIO address space.

Right, I just wanted to make that more explicit.


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