Write combining for PowerPC processors?

[Kendall Bennett]

Benjamin Herrenschmidt <benh at kernel.crashing.org> wrote:

> On Fri, 2004-12-10 at 14:12 -0800, Kendall Bennett wrote:
> 
> > Which would work if we flushed the CPU cache after we have compeleted all 
> > software rendering, right? We have to support that anyway as a lot of 
> > modern cards have write buffers that need to be flushed after software 
> > rendering is done, so we could put that the same place in the code.
> 
> You can't easily "flush the CPU cache". You have to flush the cache
> lines you have written....

Right, I forgot about that. Makes flushing the cache just a tad too 
expensive ;-(.

> > How do we enable caching? Is that something that needs to be done in the 
> > northbridge also? 
> 
> No, that is done via the page tables attributes on the MMU, I
> suspect you can control that with mprotect, but I'm not too sure. 

Would mprotect() also support enabling write combining on PPC systems? 
Does X.org doe something similar to the MTRR stuff on PPC systems or is 
it supposed to be entirely up to the kernel.

> > I assume either caching or write combining would be something for the 
> > platform specific code in the Linux kernel, right?
> 
> Yes.

Cool. Time to dig into the north bridge specs again. Michal already 
figured out how to get the VGA resources working on the Sandpoint, so now 
we can run native VGA text modes on that box ;-)

Regards,

---
Kendall Bennett
Chief Executive Officer
SciTech Software, Inc.
Phone: (530) 894 8400
http://www.scitechsoft.com

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