[PATCH xf86-video-r128 5/5] Move R128InitPLL2Registers to r128_crtc.c
Kevin Brace
kevinbrace at gmx.com
Sat Jun 16 15:24:37 UTC 2018
It does not make sense for this function to be inside r128_driver.c
since it is only called from a function inside r128_crtc.c.
Signed-off-by: Kevin Brace <kevinbrace at gmx.com>
---
src/r128.h | 1 -
src/r128_crtc.c | 55 +++++++++++++++++++++++++++++++++++++++++++++++++++++++
src/r128_driver.c | 55 -------------------------------------------------------
3 files changed, 55 insertions(+), 56 deletions(-)
diff --git a/src/r128.h b/src/r128.h
index cde5f40..4043ec7 100644
--- a/src/r128.h
+++ b/src/r128.h
@@ -528,7 +528,6 @@ extern void R128InitRMXRegisters(R128SavePtr orig, R128SavePtr save, xf86
extern void R128InitFPRegisters(R128SavePtr orig, R128SavePtr save, xf86OutputPtr output);
extern void R128InitLVDSRegisters(R128SavePtr orig, R128SavePtr save, xf86OutputPtr output);
extern Bool R128InitDDARegisters(xf86CrtcPtr crtc, R128SavePtr save, R128PLLPtr pll, DisplayModePtr mode);
-extern void R128InitPLL2Registers(xf86CrtcPtr crtc, R128SavePtr save, R128PLLPtr pll, double dot_clock);
extern Bool R128InitDDA2Registers(xf86CrtcPtr crtc, R128SavePtr save, R128PLLPtr pll, DisplayModePtr mode);
extern void R128RestoreCommonRegisters(ScrnInfoPtr pScrn, R128SavePtr restore);
extern void R128RestoreDACRegisters(ScrnInfoPtr pScrn, R128SavePtr restore);
diff --git a/src/r128_crtc.c b/src/r128_crtc.c
index 0ca0adb..d65c5b7 100644
--- a/src/r128_crtc.c
+++ b/src/r128_crtc.c
@@ -350,6 +350,61 @@ static void R128InitPLLRegisters(xf86CrtcPtr crtc, R128SavePtr save,
}
+/* Define PLL2 registers for requested video mode. */
+void R128InitPLL2Registers(xf86CrtcPtr crtc, R128SavePtr save,
+ R128PLLPtr pll, double dot_clock)
+{
+#if R128_DEBUG
+ ScrnInfoPtr pScrn = crtc->scrn;
+#endif
+ unsigned long freq = dot_clock * 100;
+ struct {
+ int divider;
+ int bitvalue;
+ } *post_div,
+ post_divs[] = {
+ /* From RAGE 128 VR/RAGE 128 GL Register
+ Reference Manual (Technical Reference
+ Manual P/N RRG-G04100-C Rev. 0.04), page
+ 3-17 (PLL_DIV_[3:0]). */
+ { 1, 0 }, /* VCLK_SRC */
+ { 2, 1 }, /* VCLK_SRC/2 */
+ { 4, 2 }, /* VCLK_SRC/4 */
+ { 8, 3 }, /* VCLK_SRC/8 */
+
+ { 3, 4 }, /* VCLK_SRC/3 */
+ /* bitvalue = 5 is reserved */
+ { 6, 6 }, /* VCLK_SRC/6 */
+ { 12, 7 }, /* VCLK_SRC/12 */
+ { 0, 0 }
+ };
+
+ if (freq > pll->max_pll_freq) freq = pll->max_pll_freq;
+ if (freq * 12 < pll->min_pll_freq) freq = pll->min_pll_freq / 12;
+
+ for (post_div = &post_divs[0]; post_div->divider; ++post_div) {
+ save->pll_output_freq_2 = post_div->divider * freq;
+ if (save->pll_output_freq_2 >= pll->min_pll_freq
+ && save->pll_output_freq_2 <= pll->max_pll_freq) break;
+ }
+
+ save->dot_clock_freq_2 = freq;
+ save->feedback_div_2 = R128Div(pll->reference_div
+ * save->pll_output_freq_2,
+ pll->reference_freq);
+ save->post_div_2 = post_div->divider;
+
+ R128TRACE(("dc=%d, of=%d, fd=%d, pd=%d\n",
+ save->dot_clock_freq_2,
+ save->pll_output_freq_2,
+ save->feedback_div_2,
+ save->post_div_2));
+
+ save->p2pll_ref_div = pll->reference_div;
+ save->p2pll_div_0 = (save->feedback_div_2 | (post_div->bitvalue<<16));
+ save->htotal_cntl2 = 0;
+}
+
static void r128_crtc_load_lut(xf86CrtcPtr crtc);
diff --git a/src/r128_driver.c b/src/r128_driver.c
index 1875a8c..312353d 100644
--- a/src/r128_driver.c
+++ b/src/r128_driver.c
@@ -2854,61 +2854,6 @@ void R128InitLVDSRegisters(R128SavePtr orig, R128SavePtr save, xf86OutputPtr out
save->lvds_gen_cntl &= ~R128_LVDS_SEL_CRTC2;
}
-/* Define PLL2 registers for requested video mode. */
-void R128InitPLL2Registers(xf86CrtcPtr crtc, R128SavePtr save,
- R128PLLPtr pll, double dot_clock)
-{
-#if R128_DEBUG
- ScrnInfoPtr pScrn = crtc->scrn;
-#endif
- unsigned long freq = dot_clock * 100;
- struct {
- int divider;
- int bitvalue;
- } *post_div,
- post_divs[] = {
- /* From RAGE 128 VR/RAGE 128 GL Register
- Reference Manual (Technical Reference
- Manual P/N RRG-G04100-C Rev. 0.04), page
- 3-17 (PLL_DIV_[3:0]). */
- { 1, 0 }, /* VCLK_SRC */
- { 2, 1 }, /* VCLK_SRC/2 */
- { 4, 2 }, /* VCLK_SRC/4 */
- { 8, 3 }, /* VCLK_SRC/8 */
-
- { 3, 4 }, /* VCLK_SRC/3 */
- /* bitvalue = 5 is reserved */
- { 6, 6 }, /* VCLK_SRC/6 */
- { 12, 7 }, /* VCLK_SRC/12 */
- { 0, 0 }
- };
-
- if (freq > pll->max_pll_freq) freq = pll->max_pll_freq;
- if (freq * 12 < pll->min_pll_freq) freq = pll->min_pll_freq / 12;
-
- for (post_div = &post_divs[0]; post_div->divider; ++post_div) {
- save->pll_output_freq_2 = post_div->divider * freq;
- if (save->pll_output_freq_2 >= pll->min_pll_freq
- && save->pll_output_freq_2 <= pll->max_pll_freq) break;
- }
-
- save->dot_clock_freq_2 = freq;
- save->feedback_div_2 = R128Div(pll->reference_div
- * save->pll_output_freq_2,
- pll->reference_freq);
- save->post_div_2 = post_div->divider;
-
- R128TRACE(("dc=%d, of=%d, fd=%d, pd=%d\n",
- save->dot_clock_freq_2,
- save->pll_output_freq_2,
- save->feedback_div_2,
- save->post_div_2));
-
- save->p2pll_ref_div = pll->reference_div;
- save->p2pll_div_0 = (save->feedback_div_2 | (post_div->bitvalue<<16));
- save->htotal_cntl2 = 0;
-}
-
/* Define DDA registers for requested video mode. */
Bool R128InitDDARegisters(xf86CrtcPtr crtc, R128SavePtr save,
R128PLLPtr pll, DisplayModePtr mode)
--
2.7.4
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