[PATCH xf86-video-amdgpu 09/13] Add support for SYNC extension fences
Michel Dänzer
michel at daenzer.net
Tue Jun 2 02:21:27 PDT 2015
From: Michel Dänzer <michel.daenzer at amd.com>
(Cherry picked from radeon commits 8fc9a241ab59ffbcdc178d6415332c88a54e85fe,
af1862a37570fa512a525ab47d72b30400d2e2d6,
aa7825eb29cdf6ac9d7b28ad18186807ff384687,
af6076241c0d322b295a4e898407ae2472bd8eb4 and
d64a13ebe0ecd241ee3260dbffd8f4a01e254183)
Signed-off-by: Michel Dänzer <michel.daenzer at amd.com>
---
configure.ac | 6 +++
src/Makefile.am | 2 +-
src/amdgpu_drv.h | 9 ++++
src/amdgpu_kms.c | 4 ++
src/amdgpu_sync.c | 147 ++++++++++++++++++++++++++++++++++++++++++++++++++++++
5 files changed, 167 insertions(+), 1 deletion(-)
create mode 100644 src/amdgpu_sync.c
diff --git a/configure.ac b/configure.ac
index ff0979e..2d6d4c7 100644
--- a/configure.ac
+++ b/configure.ac
@@ -156,6 +156,12 @@ AC_CHECK_DECL(GBM_BO_USE_LINEAR,
[#include <stdlib.h>
#include <gbm.h>])
+AC_CHECK_HEADERS([misyncshm.h], [], [],
+ [#include <X11/Xdefs.h>
+ #include <X11/Xfuncproto.h>
+ #include <xorg-server.h>
+ #include <screenint.h>])
+
CPPFLAGS="$SAVE_CPPFLAGS"
PKG_CHECK_MODULES([PCIACCESS], [pciaccess >= 0.8.0])
diff --git a/src/Makefile.am b/src/Makefile.am
index 8e91472..fa3be5c 100644
--- a/src/Makefile.am
+++ b/src/Makefile.am
@@ -29,7 +29,7 @@
amdgpu_drv_la_LIBADD = $(PCIACCESS_LIBS) $(LIBDRM_AMDGPU_LIBS) $(GBM_LIBS)
AMDGPU_KMS_SRCS=amdgpu_bo_helper.c amdgpu_dri2.c amdgpu_drm_queue.c amdgpu_kms.c \
- drmmode_display.c
+ amdgpu_sync.c drmmode_display.c
AM_CFLAGS = \
@GBM_CFLAGS@ \
diff --git a/src/amdgpu_drv.h b/src/amdgpu_drv.h
index 4b87e6e..ad51c86 100644
--- a/src/amdgpu_drv.h
+++ b/src/amdgpu_drv.h
@@ -88,6 +88,8 @@
#include "simple_list.h"
#include "amdpciids.h"
+struct _SyncFence;
+
#ifndef MAX
#define MAX(a,b) ((a)>(b)?(a):(b))
#endif
@@ -185,6 +187,9 @@ typedef struct {
void (*BlockHandler) (BLOCKHANDLER_ARGS_DECL);
+ void (*CreateFence) (ScreenPtr pScreen, struct _SyncFence *pFence,
+ Bool initially_triggered);
+
int pix24bpp; /* Depth of pixmap for 24bpp fb */
Bool dac6bits; /* Use 6 bit DAC? */
@@ -228,6 +233,10 @@ typedef struct {
} AMDGPUInfoRec, *AMDGPUInfoPtr;
+/* amdgpu_sync.c */
+extern Bool amdgpu_sync_init(ScreenPtr screen);
+extern void amdgpu_sync_close(ScreenPtr screen);
+
/* amdgpu_video.c */
extern void AMDGPUInitVideo(ScreenPtr pScreen);
extern void AMDGPUResetVideo(ScrnInfoPtr pScrn);
diff --git a/src/amdgpu_kms.c b/src/amdgpu_kms.c
index 71a4aa7..28d9305 100644
--- a/src/amdgpu_kms.c
+++ b/src/amdgpu_kms.c
@@ -703,6 +703,8 @@ static Bool AMDGPUCloseScreen_KMS(CLOSE_SCREEN_ARGS_DECL)
DeleteCallback(&FlushCallback, amdgpu_flush_callback, pScrn);
+ amdgpu_sync_close(pScreen);
+
drmDropMaster(info->dri2.drm_fd);
drmmode_fini(pScrn, &info->drmmode);
@@ -825,6 +827,8 @@ Bool AMDGPUScreenInit_KMS(SCREEN_INIT_ARGS_DECL)
}
#endif
+ amdgpu_sync_init(pScreen);
+
pScrn->vtSema = TRUE;
xf86SetBackingStore(pScreen);
diff --git a/src/amdgpu_sync.c b/src/amdgpu_sync.c
new file mode 100644
index 0000000..baade0e
--- /dev/null
+++ b/src/amdgpu_sync.c
@@ -0,0 +1,147 @@
+/*
+ * Copyright © 2013-2014 Intel Corporation
+ * Copyright © 2015 Advanced Micro Devices, Inc.
+ *
+ * Permission to use, copy, modify, distribute, and sell this software and its
+ * documentation for any purpose is hereby granted without fee, provided that
+ * the above copyright notice appear in all copies and that both that copyright
+ * notice and this permission notice appear in supporting documentation, and
+ * that the name of the copyright holders not be used in advertising or
+ * publicity pertaining to distribution of the software without specific,
+ * written prior permission. The copyright holders make no representations
+ * about the suitability of this software for any purpose. It is provided "as
+ * is" without express or implied warranty.
+ *
+ * THE COPYRIGHT HOLDERS DISCLAIM ALL WARRANTIES WITH REGARD TO THIS SOFTWARE,
+ * INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO
+ * EVENT SHALL THE COPYRIGHT HOLDERS BE LIABLE FOR ANY SPECIAL, INDIRECT OR
+ * CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE,
+ * DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
+ * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE
+ * OF THIS SOFTWARE.
+ */
+
+#include "amdgpu_drv.h"
+
+#ifdef HAVE_MISYNCSHM_H
+
+#include "misync.h"
+#include "misyncshm.h"
+#include "misyncstr.h"
+
+#include "amdgpu_glamor.h"
+
+/*
+ * This whole file exists to wrap a sync fence trigger operation
+ * so that we can flush the batch buffer to provide serialization
+ * between the server and the shm fence client
+ */
+
+static DevPrivateKeyRec amdgpu_sync_fence_private_key;
+
+typedef struct _amdgpu_sync_fence_private {
+ SyncFenceSetTriggeredFunc set_triggered;
+} amdgpu_sync_fence_private;
+
+#define SYNC_FENCE_PRIV(pFence) \
+ (amdgpu_sync_fence_private *) dixLookupPrivate(&pFence->devPrivates, &amdgpu_sync_fence_private_key)
+
+static void
+amdgpu_sync_fence_set_triggered (SyncFence *fence)
+{
+ ScreenPtr screen = fence->pScreen;
+ amdgpu_sync_fence_private *private = SYNC_FENCE_PRIV(fence);
+
+ /* Flush pending rendering operations */
+ amdgpu_glamor_flush(xf86ScreenToScrn(screen));
+
+ fence->funcs.SetTriggered = private->set_triggered;
+ fence->funcs.SetTriggered(fence);
+ private->set_triggered = fence->funcs.SetTriggered;
+ fence->funcs.SetTriggered = amdgpu_sync_fence_set_triggered;
+}
+
+static void
+amdgpu_sync_create_fence(ScreenPtr screen,
+ SyncFence *fence,
+ Bool initially_triggered)
+{
+ ScrnInfoPtr scrn = xf86ScreenToScrn(screen);
+ AMDGPUInfoPtr info = AMDGPUPTR(scrn);
+ SyncScreenFuncsPtr screen_funcs = miSyncGetScreenFuncs(screen);
+ amdgpu_sync_fence_private *private = SYNC_FENCE_PRIV(fence);
+
+ screen_funcs->CreateFence = info->CreateFence;
+ screen_funcs->CreateFence(screen, fence, initially_triggered);
+ info->CreateFence = screen_funcs->CreateFence;
+ screen_funcs->CreateFence = amdgpu_sync_create_fence;
+
+ private->set_triggered = fence->funcs.SetTriggered;
+ fence->funcs.SetTriggered = amdgpu_sync_fence_set_triggered;
+}
+
+Bool
+amdgpu_sync_init(ScreenPtr screen)
+{
+ ScrnInfoPtr scrn = xf86ScreenToScrn(screen);
+ AMDGPUInfoPtr info = AMDGPUPTR(scrn);
+ SyncScreenFuncsPtr screen_funcs;
+
+ if (!miSyncShmScreenInit(screen)) {
+ xf86DrvMsg(scrn->scrnIndex, X_WARNING,
+ "SYNC extension fences disabled because "
+ "miSyncShmScreenInit failed\n");
+ return FALSE;
+ }
+
+ if (!dixPrivateKeyRegistered(&amdgpu_sync_fence_private_key)) {
+ if (!dixRegisterPrivateKey(&amdgpu_sync_fence_private_key,
+ PRIVATE_SYNC_FENCE,
+ sizeof (amdgpu_sync_fence_private))) {
+ xf86DrvMsg(scrn->scrnIndex, X_WARNING,
+ "SYNC extension fences disabled because "
+ "dixRegisterPrivateKey failed\n");
+ return FALSE;
+ }
+ }
+
+ xf86DrvMsg(xf86ScreenToScrn(screen)->scrnIndex, X_INFO,
+ "SYNC extension fences enabled\n");
+
+ screen_funcs = miSyncGetScreenFuncs(screen);
+ info->CreateFence = screen_funcs->CreateFence;
+ screen_funcs->CreateFence = amdgpu_sync_create_fence;
+ return TRUE;
+}
+
+void
+amdgpu_sync_close(ScreenPtr screen)
+{
+ ScrnInfoPtr scrn = xf86ScreenToScrn(screen);
+ AMDGPUInfoPtr info = AMDGPUPTR(scrn);
+ SyncScreenFuncsPtr screen_funcs = miSyncGetScreenFuncs(screen);
+
+ if (screen_funcs && info->CreateFence)
+ screen_funcs->CreateFence = info->CreateFence;
+
+ info->CreateFence = NULL;
+}
+
+#else /* !HAVE_MISYNCSHM_H */
+
+Bool
+amdgpu_sync_init(ScreenPtr screen)
+{
+ xf86DrvMsg(xf86ScreenToScrn(screen)->scrnIndex, X_INFO,
+ "SYNC extension fences disabled because misyncshm.h not "
+ "available at build time\n");
+
+ return FALSE;
+}
+
+void
+amdgpu_sync_close(ScreenPtr screen)
+{
+}
+
+#endif
--
2.1.4
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