[PATCH] EXA/evergreen: Paranoia around linear tiling.

[Alex Deucher]

On Fri, Sep 20, 2013 at 11:41 AM, Christopher James Halse Rogers
<raof at ubuntu.com> wrote:
> The last two bytes of tiling_mode contain the actual tiling mode; the rest are
> extra tiling configuration bits. These configuration bits are not necessarily
> zero for a linear buffer, so mask them out before checking for linearity

Looks good.  Can you fix up evergreen_textured_videofuncs.c too?

Alex

>
> Signed-off-by: Christopher James Halse Rogers <raof at ubuntu.com>
> ---
>  src/evergreen_exa.c | 15 ++++++++++-----
>  src/radeon_drm.h    |  2 ++
>  2 files changed, 12 insertions(+), 5 deletions(-)
>
> diff --git a/src/evergreen_exa.c b/src/evergreen_exa.c
> index ccd102d..a838757 100644
> --- a/src/evergreen_exa.c
> +++ b/src/evergreen_exa.c
> @@ -156,7 +156,8 @@ EVERGREENPrepareSolid(PixmapPtr pPix, int alu, Pixel pm, Pixel fg)
>      if (accel_state->planemask & 0xff000000)
>         cb_conf.pmask |= 8; /* A */
>      cb_conf.rop = accel_state->rop;
> -    if (accel_state->dst_obj.tiling_flags == 0) {
> +    if ((accel_state->dst_obj.tiling_flags & RADEON_TILING_MASK) ==
> +       RADEON_TILING_LINEAR) {
>         cb_conf.array_mode = 0;
>         cb_conf.non_disp_tiling = 1;
>      }
> @@ -335,7 +336,8 @@ EVERGREENDoPrepareCopy(ScrnInfoPtr pScrn)
>      tex_res.base_level          = 0;
>      tex_res.last_level          = 0;
>      tex_res.perf_modulation     = 0;
> -    if (accel_state->src_obj[0].tiling_flags == 0)
> +    if ((accel_state->src_obj[0].tiling_flags & RADEON_TILING_MASK) ==
> +       RADEON_TILING_LINEAR)
>         tex_res.array_mode          = 0;
>      evergreen_set_tex_resource(pScrn, &tex_res, accel_state->src_obj[0].domain);
>
> @@ -378,7 +380,8 @@ EVERGREENDoPrepareCopy(ScrnInfoPtr pScrn)
>      if (accel_state->planemask & 0xff000000)
>         cb_conf.pmask |= 8; /* A */
>      cb_conf.rop = accel_state->rop;
> -    if (accel_state->dst_obj.tiling_flags == 0) {
> +    if ((accel_state->dst_obj.tiling_flags & RADEON_TILING_MASK) ==
> +       RADEON_TILING_LINEAR) {
>         cb_conf.array_mode = 0;
>         cb_conf.non_disp_tiling = 1;
>      }
> @@ -1001,7 +1004,8 @@ static Bool EVERGREENTextureSetup(PicturePtr pPict, PixmapPtr pPix,
>      tex_res.base_level          = 0;
>      tex_res.last_level          = 0;
>      tex_res.perf_modulation     = 0;
> -    if (accel_state->src_obj[unit].tiling_flags == 0)
> +    if ((accel_state->src_obj[unit].tiling_flags & RADEON_TILING_MASK) ==
> +       RADEON_TILING_LINEAR)
>         tex_res.array_mode          = 0;
>      evergreen_set_tex_resource  (pScrn, &tex_res, accel_state->src_obj[unit].domain);
>
> @@ -1449,7 +1453,8 @@ static Bool EVERGREENPrepareComposite(int op, PicturePtr pSrcPicture,
>      cb_conf.blendcntl |= CB_BLEND0_CONTROL__ENABLE_bit;
>      cb_conf.rop = 3;
>      cb_conf.pmask = 0xf;
> -    if (accel_state->dst_obj.tiling_flags == 0) {
> +    if ((accel_state->dst_obj.tiling_flags & RADEON_TILING_MASK) ==
> +       RADEON_TILING_LINEAR) {
>         cb_conf.array_mode = 0;
>         cb_conf.non_disp_tiling = 1;
>      }
> diff --git a/src/radeon_drm.h b/src/radeon_drm.h
> index 042e822..2bbd8fa 100644
> --- a/src/radeon_drm.h
> +++ b/src/radeon_drm.h
> @@ -800,6 +800,8 @@ struct drm_radeon_gem_create {
>         uint32_t        flags;
>  };
>
> +#define RADEON_TILING_MASK                             0xff
> +#define RADEON_TILING_LINEAR                           0x0
>  #define RADEON_TILING_MACRO                            0x1
>  #define RADEON_TILING_MICRO                            0x2
>  #define RADEON_TILING_SWAP_16BIT                       0x4
> --
> 1.8.3.2
>
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