[Bug 43191] Radeons needs 2D (MACRO) color tiling for optimal performance

[bugzilla-daemon at freedesktop.org]

https://bugs.freedesktop.org/show_bug.cgi?id=43191

--- Comment #19 from Jerome Glisse <glisse at freedesktop.org> 2011-11-28 16:18:20 PST ---
What you need to print is what is the last fence the hw signaled each time you
emit a fence. Once you know that you know which cs is guilty, then it could be
any instruction inside the cs. Thought there are some additional reg to get a
clue on which dword inside ib is the last one cp parsed, which not necessarily
means its the one causing trouble given how deep is the whole pipeline.

so if you have:
emit fence 17, last fence 13
emit fence 18, last fence 16
emit fence 19, last fence 17
emit fence 20, last fence 17
...          , last fence 17

It means that it's the cs after fence 17 is emited that is guilty.

Note that lockup is not due by a packet but by the outcome of the packet. For
rendering it could be the vertex are leading to degenerate case or the memory
is invalid or the shader program is wrong or there is some cache issue that
lead the gpu to use wrong/invalida data/shader program ...

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