[Bug 43191] Radeons needs 2D (MACRO) color tiling for optimal performance

[bugzilla-daemon at freedesktop.org]

https://bugs.freedesktop.org/show_bug.cgi?id=43191

--- Comment #23 from Simon Farnsworth <simon.farnsworth at onelan.co.uk> 2011-12-05 10:32:59 PST ---
I had the kernel print the size and gpu_offset of each BO assigned to
CB_COLOR0_BASE:

$ git diff
diff --git a/drivers/gpu/drm/radeon/evergreen.c
b/drivers/gpu/drm/radeon/evergreen.c
index 5e00d16..0794987 100644
--- a/drivers/gpu/drm/radeon/evergreen.c
+++ b/drivers/gpu/drm/radeon/evergreen.c
@@ -84,6 +84,7 @@ u32 evergreen_page_flip(struct radeon_device *rdev, int
crtc_id, u64 crtc_base)
        u32 tmp = RREG32(EVERGREEN_GRPH_UPDATE + radeon_crtc->crtc_offset);
        int i;

+        printk( KERN_INFO "Setting CRTC %d to 0x%llx\n", crtc_id, crtc_base);
        /* Lock the graphics update lock */
        tmp |= EVERGREEN_GRPH_UPDATE_LOCK;
        WREG32(EVERGREEN_GRPH_UPDATE + radeon_crtc->crtc_offset, tmp);
diff --git a/drivers/gpu/drm/radeon/evergreen_cs.c
b/drivers/gpu/drm/radeon/evergreen_cs.c
index b53d1c6..8cd9446 100644
--- a/drivers/gpu/drm/radeon/evergreen_cs.c
+++ b/drivers/gpu/drm/radeon/evergreen_cs.c
@@ -833,6 +833,7 @@ static int evergreen_cs_check_reg(struct radeon_cs_parser
*p, u32 reg, u32 idx)
                tmp = (reg - CB_COLOR0_BASE) / 0x3c;
                track->cb_color_bo_offset[tmp] = radeon_get_ib_value(p, idx);
                ib[idx] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff);
+                printk(KERN_INFO "Setting COLOR_BASE register 0x%x to 0x%x
size 0x%x\n", reg, ib[idx], radeon_bo_size(reloc->robj));
                track->cb_color_base_last[tmp] = ib[idx];
                track->cb_color_bo[tmp] = reloc->robj;
                break;

This showed me that when the back buffer drawing appears in the front buffer,
my front buffer is immediately before the back buffer in GPU memory:

[   81.319704] Setting COLOR_BASE register 0x28c60 to 0x21f00 size 0xe10000
[   82.338498] Setting CRTC 0 to 21f0000
[   84.337323] Setting COLOR_BASE register 0x28c60 to 0x13e00 size 0xe10000
[   85.363962] Setting CRTC 0 to 13e0000
[   87.354612] Setting COLOR_BASE register 0x28c60 to 0x21f00 size 0xe10000
[   88.372710] Setting CRTC 0 to 21f0000
[   90.371962] Setting COLOR_BASE register 0x28c60 to 0x13e00 size 0xe10000
[   91.398175] Setting CRTC 0 to 13e0000
[   93.389461] Setting COLOR_BASE register 0x28c60 to 0x21f00 size 0xe10000
[   94.406925] Setting CRTC 0 to 21f0000
[   95.444609] Setting COLOR_BASE register 0x28c60 to 0x21f00 size 0xe10000

I therefore hacked around with the DDX, and made drmmode_get_base_align always
return 0x100000 for 2D tiled surfaces. This appears to fix the misrendering and
the crash bugs, with the following output from the kernel:


[  118.863087] Setting COLOR_BASE register 0x28c60 to 0x23000 size 0xe10000
[  119.886856] Setting CRTC 0 to 2300000
[  121.880499] Setting COLOR_BASE register 0x28c60 to 0x14800 size 0xe10000
[  122.895613] Setting CRTC 0 to 1480000
[  124.897752] Setting COLOR_BASE register 0x28c60 to 0x23000 size 0xe10000
[  125.921075] Setting CRTC 0 to 2300000
[  127.914984] Setting COLOR_BASE register 0x28c60 to 0x14800 size 0xe10000
[  128.946542] Setting CRTC 0 to 1480000
[  130.932377] Setting COLOR_BASE register 0x28c60 to 0x23000 size 0xe10000
[  131.955295] Setting CRTC 0 to 2300000
[  132.987772] Setting COLOR_BASE register 0x28c60 to 0x23000 size 0xe10000

I now have no idea what's going on - visually, it looks like the rendering
engine writes to parts of the color buffer *before* the gpu_offset set in
CB_COLOR0_BASE.

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