[Bug 40221] NI / Cayman: Frequent pixmap corruption on >=3.0 kernels
bugzilla-daemon at freedesktop.org
bugzilla-daemon at freedesktop.org
Thu Aug 25 01:00:21 PDT 2011
https://bugs.freedesktop.org/show_bug.cgi?id=40221
--- Comment #18 from Harald Judt <h.judt at gmx.at> 2011-08-25 01:00:19 PDT ---
I have the same problem (see bug #38022), and confirm that the possible fix
doesn't help (3.1-rc3).
> Most likely, the fix is to find out what state registers the 3D driver
> is emitting that are not getting properly re-emitted in the drm blit
> code. If not, basically compare the registers emitted in
> cayman_default_state[] in cayman_blit_shaders.c in the drm with
> the cayman_context_reg_list[] in evergreen_hw_context.c in mesa and
> see what's different.
I don't know if this helps, but here are some comparisons:
1) I took cayman_default_state[] (your possible fix patch not applied) and
removed all the lines not having any comments, as I don't know what to do with
them.
2) Then I marked lines that also appear in mesa cayman_context_reg_list[] with
an 'y'.
3) Lines that appear in cayman_default_state[] but not in mesa
cayman_context_reg_list[] are marked with an 'n'.
4) I simply copied all the lines that appear in mesa cayman_context_reg_list[]
but not in cayman_default_state[] where I think they would appear.
Again, I don't know how useful this is.
const u32 cayman_default_state[] =
{
y 0x00000060, /* DB_RENDER_CONTROL */
y 0x00000000, /* DB_COUNT_CONTROL */
y 0x00000000, /* DB_DEPTH_VIEW */
y 0x0000002a, /* DB_RENDER_OVERRIDE */
y 0x00000000, /* DB_RENDER_OVERRIDE2 */
y 0x00000000, /* DB_HTILE_DATA_BASE */
y 0x00000000, /* DB_STENCIL_CLEAR */
y 0x00000000, /* DB_DEPTH_CLEAR */
{R_028030_PA_SC_SCREEN_SCISSOR_TL, 0, 0, 0},
{R_028034_PA_SC_SCREEN_SCISSOR_BR, 0, 0, 0},
y 0x00000000, /* DB_DEPTH_INFO */
y 0x00000000, /* DB_Z_INFO */
n 0x00000000, /* DB_STENCIL_INFO */
{R_028048_DB_Z_READ_BASE, REG_FLAG_NEED_BO, 0, 0},
{R_02804C_DB_STENCIL_READ_BASE, REG_FLAG_NEED_BO, 0, 0},
{R_028050_DB_Z_WRITE_BASE, REG_FLAG_NEED_BO, 0, 0},
{R_028054_DB_STENCIL_WRITE_BASE, REG_FLAG_NEED_BO, 0, 0},
{R_028058_DB_DEPTH_SIZE, 0, 0, 0},
{R_02805C_DB_DEPTH_SLICE, 0, 0, 0},
{R_028140_ALU_CONST_BUFFER_SIZE_PS_0, REG_FLAG_DIRTY_ALWAYS, 0, 0},
{R_028180_ALU_CONST_BUFFER_SIZE_VS_0, REG_FLAG_DIRTY_ALWAYS, 0, 0},
y 0x00000000, /* PA_SC_WINDOW_OFFSET */
{R_028204_PA_SC_WINDOW_SCISSOR_TL, 0, 0, 0},
{R_028208_PA_SC_WINDOW_SCISSOR_BR, 0, 0, 0},
y 0x0000ffff, /* PA_SC_CLIPRECT_RULE */
y 0x00000000, /* PA_SC_CLIPRECT_0_TL */
y 0x20002000, /* PA_SC_CLIPRECT_0_BR */
{R_028218_PA_SC_CLIPRECT_1_TL, 0, 0, 0},
{R_02821C_PA_SC_CLIPRECT_1_BR, 0, 0, 0},
{R_028220_PA_SC_CLIPRECT_2_TL, 0, 0, 0},
{R_028224_PA_SC_CLIPRECT_2_BR, 0, 0, 0},
{R_028228_PA_SC_CLIPRECT_3_TL, 0, 0, 0},
{R_02822C_PA_SC_CLIPRECT_3_BR, 0, 0, 0},
y 0xaaaaaaaa, /* PA_SC_EDGERULE */
y 0x00000000, /* PA_SU_HARDWARE_SCREEN_OFFSET */
y 0x0000000f, /* CB_TARGET_MASK */
y 0x0000000f, /* CB_SHADER_MASK */
{R_028240_PA_SC_GENERIC_SCISSOR_TL, 0, 0, 0},
{R_028244_PA_SC_GENERIC_SCISSOR_BR, 0, 0, 0},
y 0x80000000, /* PA_SC_VPORT_SCISSOR_0_TL */
y 0x20002000, /* PA_SC_VPORT_SCISSOR_0_BR */
y 0x00000000, /* PA_SC_VPORT_ZMIN_0 */
y 0x3f800000, /* PA_SC_VPORT_ZMAX_0 */
y 0x00000000, /* SX_MISC */
{R_028380_SQ_VTX_SEMANTIC_0, 0, 0, 0},
{R_028384_SQ_VTX_SEMANTIC_1, 0, 0, 0},
{R_028388_SQ_VTX_SEMANTIC_2, 0, 0, 0},
{R_02838C_SQ_VTX_SEMANTIC_3, 0, 0, 0},
{R_028390_SQ_VTX_SEMANTIC_4, 0, 0, 0},
{R_028394_SQ_VTX_SEMANTIC_5, 0, 0, 0},
{R_028398_SQ_VTX_SEMANTIC_6, 0, 0, 0},
{R_02839C_SQ_VTX_SEMANTIC_7, 0, 0, 0},
{R_0283A0_SQ_VTX_SEMANTIC_8, 0, 0, 0},
{R_0283A4_SQ_VTX_SEMANTIC_9, 0, 0, 0},
{R_0283A8_SQ_VTX_SEMANTIC_10, 0, 0, 0},
{R_0283AC_SQ_VTX_SEMANTIC_11, 0, 0, 0},
{R_0283B0_SQ_VTX_SEMANTIC_12, 0, 0, 0},
{R_0283B4_SQ_VTX_SEMANTIC_13, 0, 0, 0},
{R_0283B8_SQ_VTX_SEMANTIC_14, 0, 0, 0},
{R_0283BC_SQ_VTX_SEMANTIC_15, 0, 0, 0},
{R_0283C0_SQ_VTX_SEMANTIC_16, 0, 0, 0},
{R_0283C4_SQ_VTX_SEMANTIC_17, 0, 0, 0},
{R_0283C8_SQ_VTX_SEMANTIC_18, 0, 0, 0},
{R_0283CC_SQ_VTX_SEMANTIC_19, 0, 0, 0},
{R_0283D0_SQ_VTX_SEMANTIC_20, 0, 0, 0},
{R_0283D4_SQ_VTX_SEMANTIC_21, 0, 0, 0},
{R_0283D8_SQ_VTX_SEMANTIC_22, 0, 0, 0},
{R_0283DC_SQ_VTX_SEMANTIC_23, 0, 0, 0},
{R_0283E0_SQ_VTX_SEMANTIC_24, 0, 0, 0},
{R_0283E4_SQ_VTX_SEMANTIC_25, 0, 0, 0},
{R_0283E8_SQ_VTX_SEMANTIC_26, 0, 0, 0},
{R_0283EC_SQ_VTX_SEMANTIC_27, 0, 0, 0},
{R_0283F0_SQ_VTX_SEMANTIC_28, 0, 0, 0},
{R_0283F4_SQ_VTX_SEMANTIC_29, 0, 0, 0},
{R_0283F8_SQ_VTX_SEMANTIC_30, 0, 0, 0},
{R_0283FC_SQ_VTX_SEMANTIC_31, 0, 0, 0},
n 0x00000000, /* CP_RINGID */
n 0x00000000, /* CP_VMID */
y 0x00ffffff, /* VGT_MAX_VTX_INDX */
y 0x00000000, /* VGT_MIN_VTX_INDX */
y 0x00000000, /* VGT_INDX_OFFSET */
y 0x00000000, /* VGT_MULTI_PRIM_IB_RESET_INDX */
{R_028A94_VGT_MULTI_PRIM_IB_RESET_EN, 0, 0, 0},
y 0x00000000, /* SX_ALPHA_TEST_CONTROL */
y 0x00000000, /* CB_BLEND_RED */
y 0x00000000, /* CB_BLEND_GREEN */
y 0x00000000, /* CB_BLEND_BLUE */
y 0x00000000, /* CB_BLEND_ALPHA */
{R_028430_DB_STENCILREFMASK, 0, 0, 0},
{R_028434_DB_STENCILREFMASK_BF, 0, 0, 0},
{R_028438_SX_ALPHA_REF, 0, 0, 0},
{R_02843C_PA_CL_VPORT_XSCALE_0, 0, 0, 0},
{R_028440_PA_CL_VPORT_XOFFSET_0, 0, 0, 0},
{R_028444_PA_CL_VPORT_YSCALE_0, 0, 0, 0},
{R_028448_PA_CL_VPORT_YOFFSET_0, 0, 0, 0},
{R_02844C_PA_CL_VPORT_ZSCALE_0, 0, 0, 0},
{R_028450_PA_CL_VPORT_ZOFFSET_0, 0, 0, 0},
{R_0285BC_PA_CL_UCP0_X, 0, 0, 0},
{R_0285C0_PA_CL_UCP0_Y, 0, 0, 0},
{R_0285C4_PA_CL_UCP0_Z, 0, 0, 0},
{R_0285C8_PA_CL_UCP0_W, 0, 0, 0},
{R_0285CC_PA_CL_UCP1_X, 0, 0, 0},
{R_0285D0_PA_CL_UCP1_Y, 0, 0, 0},
{R_0285D4_PA_CL_UCP1_Z, 0, 0, 0},
{R_0285D8_PA_CL_UCP1_W, 0, 0, 0},
{R_0285DC_PA_CL_UCP2_X, 0, 0, 0},
{R_0285E0_PA_CL_UCP2_Y, 0, 0, 0},
{R_0285E4_PA_CL_UCP2_Z, 0, 0, 0},
{R_0285E8_PA_CL_UCP2_W, 0, 0, 0},
{R_0285EC_PA_CL_UCP3_X, 0, 0, 0},
{R_0285F0_PA_CL_UCP3_Y, 0, 0, 0},
{R_0285F4_PA_CL_UCP3_Z, 0, 0, 0},
{R_0285F8_PA_CL_UCP3_W, 0, 0, 0},
{R_0285FC_PA_CL_UCP4_X, 0, 0, 0},
{R_028600_PA_CL_UCP4_Y, 0, 0, 0},
{R_028604_PA_CL_UCP4_Z, 0, 0, 0},
{R_028608_PA_CL_UCP4_W, 0, 0, 0},
{R_02860C_PA_CL_UCP5_X, 0, 0, 0},
{R_028610_PA_CL_UCP5_Y, 0, 0, 0},
{R_028614_PA_CL_UCP5_Z, 0, 0, 0},
{R_028618_PA_CL_UCP5_W, 0, 0, 0},
y 0x00000100, /* SPI_VS_OUT_ID_0 */
{R_028438_SX_ALPHA_REF, 0, 0, 0},
{R_02843C_PA_CL_VPORT_XSCALE_0, 0, 0, 0},
{R_028440_PA_CL_VPORT_XOFFSET_0, 0, 0, 0},
{R_028444_PA_CL_VPORT_YSCALE_0, 0, 0, 0},
{R_028448_PA_CL_VPORT_YOFFSET_0, 0, 0, 0},
{R_02844C_PA_CL_VPORT_ZSCALE_0, 0, 0, 0},
{R_028450_PA_CL_VPORT_ZOFFSET_0, 0, 0, 0},
{R_0285BC_PA_CL_UCP0_X, 0, 0, 0},
{R_0285C0_PA_CL_UCP0_Y, 0, 0, 0},
{R_0285C4_PA_CL_UCP0_Z, 0, 0, 0},
{R_0285C8_PA_CL_UCP0_W, 0, 0, 0},
{R_0285CC_PA_CL_UCP1_X, 0, 0, 0},
{R_0285D0_PA_CL_UCP1_Y, 0, 0, 0},
{R_0285D4_PA_CL_UCP1_Z, 0, 0, 0},
{R_0285D8_PA_CL_UCP1_W, 0, 0, 0},
{R_0285DC_PA_CL_UCP2_X, 0, 0, 0},
{R_0285E0_PA_CL_UCP2_Y, 0, 0, 0},
{R_0285E4_PA_CL_UCP2_Z, 0, 0, 0},
{R_0285E8_PA_CL_UCP2_W, 0, 0, 0},
{R_0285EC_PA_CL_UCP3_X, 0, 0, 0},
{R_0285F0_PA_CL_UCP3_Y, 0, 0, 0},
{R_0285F4_PA_CL_UCP3_Z, 0, 0, 0},
{R_0285F8_PA_CL_UCP3_W, 0, 0, 0},
{R_0285FC_PA_CL_UCP4_X, 0, 0, 0},
{R_028600_PA_CL_UCP4_Y, 0, 0, 0},
{R_028604_PA_CL_UCP4_Z, 0, 0, 0},
{R_028608_PA_CL_UCP4_W, 0, 0, 0},
{R_02860C_PA_CL_UCP5_X, 0, 0, 0},
{R_028610_PA_CL_UCP5_Y, 0, 0, 0},
{R_028614_PA_CL_UCP5_Z, 0, 0, 0},
{R_028618_PA_CL_UCP5_W, 0, 0, 0},
{R_028620_SPI_VS_OUT_ID_1, 0, 0, 0},
{R_028624_SPI_VS_OUT_ID_2, 0, 0, 0},
{R_028628_SPI_VS_OUT_ID_3, 0, 0, 0},
{R_02862C_SPI_VS_OUT_ID_4, 0, 0, 0},
{R_028630_SPI_VS_OUT_ID_5, 0, 0, 0},
{R_028634_SPI_VS_OUT_ID_6, 0, 0, 0},
{R_028638_SPI_VS_OUT_ID_7, 0, 0, 0},
{R_02863C_SPI_VS_OUT_ID_8, 0, 0, 0},
{R_028640_SPI_VS_OUT_ID_9, 0, 0, 0},
y 0x00000100, /* SPI_PS_INPUT_CNTL_0 */
y 0x00000101, /* SPI_PS_INPUT_CNTL_1 */
{R_02864C_SPI_PS_INPUT_CNTL_2, 0, 0, 0},
{R_028650_SPI_PS_INPUT_CNTL_3, 0, 0, 0},
{R_028654_SPI_PS_INPUT_CNTL_4, 0, 0, 0},
{R_028658_SPI_PS_INPUT_CNTL_5, 0, 0, 0},
{R_02865C_SPI_PS_INPUT_CNTL_6, 0, 0, 0},
{R_028660_SPI_PS_INPUT_CNTL_7, 0, 0, 0},
{R_028664_SPI_PS_INPUT_CNTL_8, 0, 0, 0},
{R_028668_SPI_PS_INPUT_CNTL_9, 0, 0, 0},
{R_02866C_SPI_PS_INPUT_CNTL_10, 0, 0, 0},
{R_028670_SPI_PS_INPUT_CNTL_11, 0, 0, 0},
{R_028674_SPI_PS_INPUT_CNTL_12, 0, 0, 0},
{R_028678_SPI_PS_INPUT_CNTL_13, 0, 0, 0},
{R_02867C_SPI_PS_INPUT_CNTL_14, 0, 0, 0},
{R_028680_SPI_PS_INPUT_CNTL_15, 0, 0, 0},
{R_028684_SPI_PS_INPUT_CNTL_16, 0, 0, 0},
{R_028688_SPI_PS_INPUT_CNTL_17, 0, 0, 0},
{R_02868C_SPI_PS_INPUT_CNTL_18, 0, 0, 0},
{R_028690_SPI_PS_INPUT_CNTL_19, 0, 0, 0},
{R_028694_SPI_PS_INPUT_CNTL_20, 0, 0, 0},
{R_028698_SPI_PS_INPUT_CNTL_21, 0, 0, 0},
{R_02869C_SPI_PS_INPUT_CNTL_22, 0, 0, 0},
{R_0286A0_SPI_PS_INPUT_CNTL_23, 0, 0, 0},
{R_0286A4_SPI_PS_INPUT_CNTL_24, 0, 0, 0},
{R_0286A8_SPI_PS_INPUT_CNTL_25, 0, 0, 0},
{R_0286AC_SPI_PS_INPUT_CNTL_26, 0, 0, 0},
{R_0286B0_SPI_PS_INPUT_CNTL_27, 0, 0, 0},
{R_0286B4_SPI_PS_INPUT_CNTL_28, 0, 0, 0},
{R_0286B8_SPI_PS_INPUT_CNTL_29, 0, 0, 0},
{R_0286BC_SPI_PS_INPUT_CNTL_30, 0, 0, 0},
{R_0286C0_SPI_PS_INPUT_CNTL_31, 0, 0, 0},
y 0x00000000, /* SPI_VS_OUT_CONFIG */
{R_0286C8_SPI_THREAD_GROUPING, 0, 0, 0},
y 0x20000001, /* SPI_PS_IN_CONTROL_0 */
y 0x00000000, /* SPI_PS_IN_CONTROL_1 */
y 0x00000000, /* SPI_INTERP_CONTROL_0 */
y 0x00000000, /* SPI_INPUT_Z */
y 0x00000000, /* SPI_FOG_CNTL */
y 0x00100000, /* SPI_BARYC_CNTL */
y 0x00000000, /* SPI_PS_IN_CONTROL_2 */
y 0x00000000, /* SPI_COMPUTE_INPUT_CNTL */
n 0x00000000, /* SPI_COMPUTE_NUM_THREAD_X */
n 0x00000000, /* SPI_COMPUTE_NUM_THREAD_Y */
n 0x00000000, /* SPI_COMPUTE_NUM_THREAD_Z */
n 0x00000000, /* SPI_GPR_MGMT */
n 0x00000000, /* SPI_LDS_MGMT */
n 0x00000000, /* SPI_STACK_MGMT */
n 0x00000000, /* SPI_WAVE_MGMT_1 */
n 0x00000000, /* SPI_WAVE_MGMT_2 */
y 0x00000000, /* CB_BLEND0_CONTROL */
{R_028784_CB_BLEND1_CONTROL, 0, 0, 0},
{R_028788_CB_BLEND2_CONTROL, 0, 0, 0},
{R_02878C_CB_BLEND3_CONTROL, 0, 0, 0},
{R_028790_CB_BLEND4_CONTROL, 0, 0, 0},
{R_028794_CB_BLEND5_CONTROL, 0, 0, 0},
{R_028798_CB_BLEND6_CONTROL, 0, 0, 0},
{R_02879C_CB_BLEND7_CONTROL, 0, 0, 0},
y 0x00000000, /* DB_DEPTH_CONTROL */
y 0x00000000, /* DB_EQAA */
y 0x00cc0010, /* CB_COLOR_CONTROL */
y 0x00000210, /* DB_SHADER_CONTROL */
y 0x00010000, /* PA_CL_CLIP_CNTL */
y 0x00000004, /* PA_SU_SC_MODE_CNTL */
y 0x00000100, /* PA_CL_VTE_CNTL */
y 0x00000000, /* PA_CL_VS_OUT_CNTL */
y 0x00000000, /* PA_CL_NANINF_CNTL */
n 0x00000000, /* PA_SU_LINE_STIPPLE_CNTL */
n 0x00000000, /* PA_SU_LINE_STIPPLE_SCALE */
n 0x00000000, /* PA_SU_PRIM_FILTER_CNTL */
{R_028838_SQ_DYN_GPR_RESOURCE_LIMIT_1, 0, 0, 0},
{R_028840_SQ_PGM_START_PS, REG_FLAG_NEED_BO, S_0085F0_SH_ACTION_ENA(1),
0xFFFFFFFF},
{R_028844_SQ_PGM_RESOURCES_PS, 0, 0, 0},
{R_028848_SQ_PGM_RESOURCES_2_PS, 0, 0, 0},
{R_02884C_SQ_PGM_EXPORTS_PS, 0, 0, 0},
{R_02885C_SQ_PGM_START_VS, REG_FLAG_NEED_BO, S_0085F0_SH_ACTION_ENA(1),
0xFFFFFFFF},
{R_028860_SQ_PGM_RESOURCES_VS, 0, 0, 0},
{R_028864_SQ_PGM_RESOURCES_2_VS, 0, 0, 0},
y 0x00000000, /* SQ_PGM_START_FS */
{R_0288A8_SQ_PGM_RESOURCES_FS, 0, 0, 0},
y 0x00000000, /* SQ_LDS_ALLOC_PS */
y 0x00000000, /* SQ_ESGS_RING_ITEMSIZE */
{R_028904_SQ_GSVS_RING_ITEMSIZE, 0, 0, 0},
{R_028908_SQ_ESTMP_RING_ITEMSIZE, 0, 0, 0},
{R_02890C_SQ_GSTMP_RING_ITEMSIZE, 0, 0, 0},
{R_028910_SQ_VSTMP_RING_ITEMSIZE, 0, 0, 0},
{R_028914_SQ_PSTMP_RING_ITEMSIZE, 0, 0, 0},
y 0x00000000, /* SQ_GS_VERT_ITEMSIZE */
{R_028920_SQ_GS_VERT_ITEMSIZE_1, 0, 0, 0},
{R_028924_SQ_GS_VERT_ITEMSIZE_2, 0, 0, 0},
{R_028928_SQ_GS_VERT_ITEMSIZE_3, 0, 0, 0},
{R_028940_ALU_CONST_CACHE_PS_0, REG_FLAG_NEED_BO,
S_0085F0_SH_ACTION_ENA(1), 0xFFFFFFFF},
{R_028980_ALU_CONST_CACHE_VS_0, REG_FLAG_NEED_BO,
S_0085F0_SH_ACTION_ENA(1), 0xFFFFFFFF},
y 0x00000000, /* PA_SU_POINT_SIZE */
y 0x00000000, /* PA_SU_POINT_MINMAX */
y 0x00000008, /* PA_SU_LINE_CNTL */
n 0x00000000, /* PA_SC_LINE_STIPPLE */
y 0x00000000, /* VGT_OUTPUT_PATH_CNTL */
y 0x00000000, /* VGT_HOS_CNTL */
{R_028A18_VGT_HOS_MAX_TESS_LEVEL, 0, 0, 0},
{R_028A1C_VGT_HOS_MIN_TESS_LEVEL, 0, 0, 0},
{R_028A20_VGT_HOS_REUSE_DEPTH, 0, 0, 0},
{R_028A24_VGT_GROUP_PRIM_TYPE, 0, 0, 0},
{R_028A28_VGT_GROUP_FIRST_DECR, 0, 0, 0},
{R_028A2C_VGT_GROUP_DECR, 0, 0, 0},
{R_028A30_VGT_GROUP_VECT_0_CNTL, 0, 0, 0},
{R_028A34_VGT_GROUP_VECT_1_CNTL, 0, 0, 0},
{R_028A38_VGT_GROUP_VECT_0_FMT_CNTL, 0, 0, 0},
{R_028A3C_VGT_GROUP_VECT_1_FMT_CNTL, 0, 0, 0},
y 0x00000000, /* VGT_GS_MODE */
y 0x00000000, /* PA_SC_MODE_CNTL_0 */
y 0x00000000, /* PA_SC_MODE_CNTL_1 */
n 0x00000000, /* VGT_PRIMITIVEID_EN */
n 0x00000000, /* VGT_MULTI_PRIM_IB_RESET_EN */
n 0x00000000, /* VGT_INSTANCE_STEP_RATE_0 */
y 0x00000000, /* VGT_REUSE_OFF */
{R_028ABC_DB_HTILE_SURFACE, 0, 0, 0},
{R_028AC0_DB_SRESULTS_COMPARE_STATE0, 0, 0, 0},
{R_028AC4_DB_SRESULTS_COMPARE_STATE1, 0, 0, 0},
{R_028AC8_DB_PRELOAD_CONTROL, 0, 0, 0},
y 0x00000000, /* VGT_SHADER_STAGES_EN */
y 0x0000aa00, /* DB_ALPHA_TO_MASK */
y 0x00000000, /* PA_SU_POLY_OFFSET_DB_FMT_CNTL */
{R_028B7C_PA_SU_POLY_OFFSET_CLAMP, 0, 0, 0},
{R_028B80_PA_SU_POLY_OFFSET_FRONT_SCALE, 0, 0, 0},
{R_028B84_PA_SU_POLY_OFFSET_FRONT_OFFSET, 0, 0, 0},
{R_028B88_PA_SU_POLY_OFFSET_BACK_SCALE, 0, 0, 0},
{R_028B8C_PA_SU_POLY_OFFSET_BACK_OFFSET, 0, 0, 0},
y 0x00000000, /* VGT_STRMOUT_CONFIG */
{R_028B98_VGT_STRMOUT_BUFFER_CONFIG, 0, 0, 0},
y 0x76543210, /* PA_SC_CENTROID_PRIORITY_0 */
y 0xfedcba98, /* PA_SC_CENTROID_PRIORITY_1 */
y 0x00000000, /* PA_SC_LINE_CNTL */
y 0x00000000, /* PA_SC_AA_CONFIG */
y 0x00000005, /* PA_SU_VTX_CNTL */
y 0x3f800000, /* PA_CL_GB_VERT_CLIP_ADJ */
y 0x3f800000, /* PA_CL_GB_VERT_DISC_ADJ */
y 0x3f800000, /* PA_CL_GB_HORZ_CLIP_ADJ */
y 0x3f800000, /* PA_CL_GB_HORZ_DISC_ADJ */
y 0x00000000, /* PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0 */
y 0xffffffff, /* PA_SC_AA_MASK_X0Y0_X1Y0 */
{R_028C60_CB_COLOR0_BASE, REG_FLAG_NEED_BO, 0, 0},
{R_028C64_CB_COLOR0_PITCH, 0, 0, 0},
{R_028C68_CB_COLOR0_SLICE, 0, 0, 0},
{R_028C6C_CB_COLOR0_VIEW, 0, 0, 0},
{R_028C70_CB_COLOR0_INFO, REG_FLAG_NEED_BO, 0, 0xFFFFFFFF},
{R_028C74_CB_COLOR0_ATTRIB, REG_FLAG_NEED_BO, 0, 0},
{R_028C78_CB_COLOR0_DIM, 0, 0, 0},
{GROUP_FORCE_NEW_BLOCK, 0, 0, 0},
{R_028C9C_CB_COLOR1_BASE, REG_FLAG_NEED_BO, 0, 0},
{R_028CA0_CB_COLOR1_PITCH, 0, 0, 0},
{R_028CA4_CB_COLOR1_SLICE, 0, 0, 0},
{R_028CA8_CB_COLOR1_VIEW, 0, 0, 0},
{R_028CAC_CB_COLOR1_INFO, REG_FLAG_NEED_BO, 0, 0xFFFFFFFF},
{R_028CB0_CB_COLOR1_ATTRIB, REG_FLAG_NEED_BO, 0, 0},
{R_028CB4_CB_COLOR1_DIM, 0, 0, 0},
{GROUP_FORCE_NEW_BLOCK, 0, 0, 0},
{R_028CD8_CB_COLOR2_BASE, REG_FLAG_NEED_BO, 0, 0},
{R_028CDC_CB_COLOR2_PITCH, 0, 0, 0},
{R_028CE0_CB_COLOR2_SLICE, 0, 0, 0},
{R_028CE4_CB_COLOR2_VIEW, 0, 0, 0},
{R_028CE8_CB_COLOR2_INFO, REG_FLAG_NEED_BO, 0, 0xFFFFFFFF},
{R_028CEC_CB_COLOR2_ATTRIB, REG_FLAG_NEED_BO, 0, 0},
{R_028CF0_CB_COLOR2_DIM, 0, 0, 0},
{GROUP_FORCE_NEW_BLOCK, 0, 0, 0},
{R_028D14_CB_COLOR3_BASE, REG_FLAG_NEED_BO, 0, 0},
{R_028D18_CB_COLOR3_PITCH, 0, 0, 0},
{R_028D1C_CB_COLOR3_SLICE, 0, 0, 0},
{R_028D20_CB_COLOR3_VIEW, 0, 0, 0},
{R_028D24_CB_COLOR3_INFO, REG_FLAG_NEED_BO, 0, 0xFFFFFFFF},
{R_028D28_CB_COLOR3_ATTRIB, REG_FLAG_NEED_BO, 0, 0},
{R_028D2C_CB_COLOR3_DIM, 0, 0, 0},
{GROUP_FORCE_NEW_BLOCK, 0, 0, 0},
{R_028D50_CB_COLOR4_BASE, REG_FLAG_NEED_BO, 0, 0},
{R_028D54_CB_COLOR4_PITCH, 0, 0, 0},
{R_028D58_CB_COLOR4_SLICE, 0, 0, 0},
{R_028D5C_CB_COLOR4_VIEW, 0, 0, 0},
{R_028D60_CB_COLOR4_INFO, REG_FLAG_NEED_BO, 0, 0xFFFFFFFF},
{R_028D64_CB_COLOR4_ATTRIB, REG_FLAG_NEED_BO, 0, 0},
{R_028D68_CB_COLOR4_DIM, 0, 0, 0},
{GROUP_FORCE_NEW_BLOCK, 0, 0, 0},
{R_028D8C_CB_COLOR5_BASE, REG_FLAG_NEED_BO, 0, 0},
{R_028D90_CB_COLOR5_PITCH, 0, 0, 0},
{R_028D94_CB_COLOR5_SLICE, 0, 0, 0},
{R_028D98_CB_COLOR5_VIEW, 0, 0, 0},
{R_028D9C_CB_COLOR5_INFO, REG_FLAG_NEED_BO, 0, 0xFFFFFFFF},
{R_028DA0_CB_COLOR5_ATTRIB, REG_FLAG_NEED_BO, 0, 0},
{R_028DA4_CB_COLOR5_DIM, 0, 0, 0},
{GROUP_FORCE_NEW_BLOCK, 0, 0, 0},
{R_028DC8_CB_COLOR6_BASE, REG_FLAG_NEED_BO, 0, 0},
{R_028DCC_CB_COLOR6_PITCH, 0, 0, 0},
{R_028DD0_CB_COLOR6_SLICE, 0, 0, 0},
{R_028DD4_CB_COLOR6_VIEW, 0, 0, 0},
{R_028DD8_CB_COLOR6_INFO, REG_FLAG_NEED_BO, 0, 0xFFFFFFFF},
{R_028DDC_CB_COLOR6_ATTRIB, REG_FLAG_NEED_BO, 0, 0},
{R_028DE0_CB_COLOR6_DIM, 0, 0, 0},
{GROUP_FORCE_NEW_BLOCK, 0, 0, 0},
{R_028E04_CB_COLOR7_BASE, REG_FLAG_NEED_BO, 0, 0},
{R_028E08_CB_COLOR7_PITCH, 0, 0, 0},
{R_028E0C_CB_COLOR7_SLICE, 0, 0, 0},
{R_028E10_CB_COLOR7_VIEW, 0, 0, 0},
{R_028E14_CB_COLOR7_INFO, REG_FLAG_NEED_BO, 0, 0xFFFFFFFF},
{R_028E18_CB_COLOR7_ATTRIB, REG_FLAG_NEED_BO, 0, 0},
{R_028E1C_CB_COLOR7_DIM, 0, 0, 0},
{GROUP_FORCE_NEW_BLOCK, 0, 0, 0},
{R_028E40_CB_COLOR8_BASE, REG_FLAG_NEED_BO, 0, 0},
{R_028E44_CB_COLOR8_PITCH, 0, 0, 0},
{R_028E48_CB_COLOR8_SLICE, 0, 0, 0},
{R_028E4C_CB_COLOR8_VIEW, 0, 0, 0},
{R_028E50_CB_COLOR8_INFO, REG_FLAG_NEED_BO, 0, 0xFFFFFFFF},
{R_028E54_CB_COLOR8_ATTRIB, REG_FLAG_NEED_BO, 0, 0},
{R_028E58_CB_COLOR8_DIM, 0, 0, 0},
{GROUP_FORCE_NEW_BLOCK, 0, 0, 0},
{R_028E5C_CB_COLOR9_BASE, REG_FLAG_NEED_BO, 0, 0},
{R_028E60_CB_COLOR9_PITCH, 0, 0, 0},
{R_028E64_CB_COLOR9_SLICE, 0, 0, 0},
{R_028E68_CB_COLOR9_VIEW, 0, 0, 0},
{R_028E6C_CB_COLOR9_INFO, REG_FLAG_NEED_BO, 0, 0xFFFFFFFF},
{R_028E70_CB_COLOR9_ATTRIB, REG_FLAG_NEED_BO, 0, 0},
{R_028E74_CB_COLOR9_DIM, 0, 0, 0},
{GROUP_FORCE_NEW_BLOCK, 0, 0, 0},
{R_028E78_CB_COLOR10_BASE, REG_FLAG_NEED_BO, 0, 0},
{R_028E7C_CB_COLOR10_PITCH, 0, 0, 0},
{R_028E80_CB_COLOR10_SLICE, 0, 0, 0},
{R_028E84_CB_COLOR10_VIEW, 0, 0, 0},
{R_028E88_CB_COLOR10_INFO, REG_FLAG_NEED_BO, 0, 0xFFFFFFFF},
{R_028E8C_CB_COLOR10_ATTRIB, REG_FLAG_NEED_BO, 0, 0},
{R_028E90_CB_COLOR10_DIM, 0, 0, 0},
{GROUP_FORCE_NEW_BLOCK, 0, 0, 0},
{R_028E94_CB_COLOR11_BASE, REG_FLAG_NEED_BO, 0, 0},
{R_028E98_CB_COLOR11_PITCH, 0, 0, 0},
{R_028E9C_CB_COLOR11_SLICE, 0, 0, 0},
{R_028EA0_CB_COLOR11_VIEW, 0, 0, 0},
{R_028EA4_CB_COLOR11_INFO, REG_FLAG_NEED_BO, 0, 0xFFFFFFFF},
{R_028EA8_CB_COLOR11_ATTRIB, REG_FLAG_NEED_BO, 0, 0},
{R_028EAC_CB_COLOR11_DIM, 0, 0, 0},
n 0x0000000e, /* VGT_VERTEX_REUSE_BLOCK_CNTL */
}
--
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