[Bug 27692] Evergreen and triple head segfaults xorg

[bugzilla-daemon at freedesktop.org]

https://bugs.freedesktop.org/show_bug.cgi?id=27692

--- Comment #8 from Alex Deucher <agd5f at yahoo.com> 2010-04-18 10:24:39 PDT ---
The clocking gets a bit complex, but there are basically only 2 programmable
pixel PLLs for the CRTC clocks and digital PHY blocks.  In most cases, the CRTC
clock and PHY are derived from one of the two pixel PLLs.  For the >2 head
case, the CRTC clocks on the additional heads are derived from the an
additional DCPLL and the additional PHYs are driven by an external PLL.  This
works for DP because DP uses a fixed clock unlike non-DP.  If the timing is the
same on several non-DP monitors in theory they could be driven by the same
pixel PLL, but that will not work for the general case (I'm not sure this has
been verified on the hw or will work reliably).  You can also drive the PHYs
with the same CRTC in which case all heads driven by that CRTC will get the
exact some timing.  If several heads share the same PHY block and links, they
can not be used at the same time independantly.  But basically, all heads >2
have to be DP from the GPU's perspective.  As Dave said this can be native DP
or an active DP to DVI convertor since the active convertor looks like DP to
the GPU.

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