atombios question plus AMD register reference guides

[jfs]

Hi,
i am trying to understand how the atombios parser works. i have
been looking at both the xf86-video-ati code and the
drivers/gpu/drm/radeon code in recent (2.6.31) linux tree.
i pretty much get the idea, but i am stumbling on some parts.


for example in the following code in ./drivers/gpu/drm/radeon/atom.c:

static int atom_iio_len[] = { 1, 2, 3, 3, 3, 3, 4, 4, 4, 3 };

static void atom_index_iio(struct atom_context *ctx, int base)
{
        ctx->iio = kzalloc(2 * 256, GFP_KERNEL);
        while (CU8(base) == ATOM_IIO_START) {
                ctx->iio[CU8(base + 1)] = base + 2;
                base += 2;
                while (CU8(base) != ATOM_IIO_END)
                        base += atom_iio_len[CU8(base)];
                base += 3;
        }
}
...


i understand this is about some indirect i/o accesses. but would
it be possible to have a high level description of what are these
iios and what is happening?


also here:

---
static int atom_dst_to_src[8][4] = {
        /* translate destination alignment field to the source
alignment encoding */
        {0, 0, 0, 0},
        {1, 2, 3, 0},
        {1, 2, 3, 0},
        {1, 2, 3, 0},
        {4, 5, 6, 7},
        {4, 5, 6, 7},
        {4, 5, 6, 7},
        {4, 5, 6, 7},
};
...

static void atom_put_dst(atom_exec_context *ctx, int arg, uint8_t
attr,
                         int *ptr, uint32_t val, uint32_t saved)
{
        uint32_t align =
            atom_dst_to_src[(attr >> 3) & 7][(attr >> 6) & 3],
old_val =
            val, idx;
        struct atom_context *gctx = ctx->ctx;
        old_val &= atom_arg_mask[align] >> atom_arg_shift[align];
        val <<= atom_arg_shift[align];
        val &= atom_arg_mask[align];
        saved &= ~atom_arg_mask[align];
        val |= saved;
        switch (arg) {
        case ATOM_ARG_REG:

...
---


looks like there needs to be some alignment work done in the code
stream. but i don't get the full picture.



one difficulty i have is that i find it hard to reconcile the
registers accessed in the code with what is described in the
various AMD register reference guides. is there some more
documentation to look at that would give more info on the GPUs
register layout?
for ex, at some point the DRM code is doing a soft reset to this reg:

r600d.h:#define R_008020_GRBM_SOFT_RESET                0x8020

but it is not in the ref guide..

thx a lot
-jfs