broken msi interrupts with radeon rv570 on amd 8151 agp bridge

[Grant Grundler]

On Thu, Nov 05, 2009 at 11:03:37PM +0000, Daniel J Blueman wrote:
...
> As MSI interrupts are normal write transactions, they are largely
> transparent to bridges.

You are correct with the exception that the destination is not host memory.
Bridge address decoding is generally explicit about which address ranges
will be routed and where to. Upstream address routing is *usually* the
negative decoding of "downstream" routed address ranges.

> Interesting to note that only more recent
> kernels (>~2.6.24) started setting up the MSI address register with
> non-8 byte alignment.
> 
> It would be interesting to get the MSI address and data registers when
> MSIs are understood to not being received, and we can decode the
> pattern.

That's a good idea. I would be surprised of the alignment of the
destination mattered to anything but the destination device.

hth,
grant