Enable byte swapping for r600 Hardware

[Eduard Fuchs]

Hi,

I have tested this patch on the MPC8641HPCN board (PowerPC) with HD2400 PCIe 
card. Currently I tested only 32bpp mode, so in 16bpp mode the swapping is 
disabled.

I used the driver from git in the version 6.10.0 (with git tag xf86-video-
ati-6.10.0). Unfortunately crash the latest driver version (6.12) on our 
system.


Best Regards

Eduard Fuchs

--- origin/src/radeon_reg.h     2009-04-02 16:56:15.000000000 +0200
+++ xf86-video-ati/src/radeon_reg.h     2009-04-02 16:43:59.000000000 +0200
@@ -3580,6 +3580,13 @@
 #       define AVIVO_D1GRPH_MACRO_ADDRESS_MODE          (1<<21)

 #define AVIVO_D1GRPH_LUT_SEL                                    0x6108
+
+#define AVIVO_D1GRPH_SWAP_CONTROL                               0x610C
+#       define AVIVO_D1GRPH_SWAP_ENDIAN_NONE            (0)
+#       define AVIVO_D1GRPH_SWAP_ENDIAN_16BIT           (1)
+#       define AVIVO_D1GRPH_SWAP_ENDIAN_32BIT           (2)
+#       define AVIVO_D1GRPH_SWAP_ENDIAN_64BIT           (3)
+
 #define AVIVO_D1GRPH_PRIMARY_SURFACE_ADDRESS                    0x6110
 #define AVIVO_D1GRPH_SECONDARY_SURFACE_ADDRESS                  0x6118
 #define AVIVO_D1GRPH_PITCH                                      0x6120


--- origin/src/atombios_crtc.c  2009-04-02 16:56:15.000000000 +0200
+++ xf86-video-ati/src/atombios_crtc.c  2009-04-02 16:43:59.000000000 +0200
@@ -450,17 +450,21 @@

     if (IS_AVIVO_VARIANT) {
        uint32_t fb_format;
+       uint32_t fb_swap = AVIVO_D1GRPH_SWAP_ENDIAN_NONE;

        switch (crtc->scrn->bitsPerPixel) {
        case 15:
            fb_format = AVIVO_D1GRPH_CONTROL_DEPTH_16BPP | 
AVIVO_D1GRPH_CONTROL_16BPP_ARGB1555;
+               fb_swap = AVIVO_D1GRPH_SWAP_ENDIAN_NONE;
            break;
        case 16:
            fb_format = AVIVO_D1GRPH_CONTROL_DEPTH_16BPP | 
AVIVO_D1GRPH_CONTROL_16BPP_RGB565;
+               fb_swap = AVIVO_D1GRPH_SWAP_ENDIAN_NONE;
            break;
        case 24:
        case 32:
            fb_format = AVIVO_D1GRPH_CONTROL_DEPTH_32BPP | 
AVIVO_D1GRPH_CONTROL_32BPP_ARGB8888;
+               fb_swap = AVIVO_D1GRPH_SWAP_ENDIAN_32BIT;
            break;
        default:
            FatalError("Unsupported screen depth: %d\n", xf86GetDepth());
@@ -488,6 +492,10 @@
        OUTREG(AVIVO_D1GRPH_SECONDARY_SURFACE_ADDRESS + radeon_crtc-
>crtc_offset, fb_location);
        OUTREG(AVIVO_D1GRPH_CONTROL + radeon_crtc->crtc_offset, fb_format);

+#if X_BYTE_ORDER == X_BIG_ENDIAN
+       OUTREG(AVIVO_D1GRPH_SWAP_CONTROL + radeon_crtc->crtc_offset, fb_swap);
+#endif
+
        OUTREG(AVIVO_D1GRPH_SURFACE_OFFSET_X + radeon_crtc->crtc_offset, 0);
        OUTREG(AVIVO_D1GRPH_SURFACE_OFFSET_Y + radeon_crtc->crtc_offset, 0);
        OUTREG(AVIVO_D1GRPH_X_START + radeon_crtc->crtc_offset, 0);