Bug#508999: more on 508999 (lenny with wrong frequencies on Radeon Xpress 200)

[Bernhard R. Link]

* Alex Deucher <alexdeucher at gmail.com> [081222 10:18]:
> We only use the lower 8 bits because bits 9:8 select the pll dividers
> to use; changing it breaks some chips.  Some rv410 chips have a
> similar issue.  Does this patch fix it for you?

The patch does not apply cleanly on the lenny version, it looks like the
first two lines of this are swapped:

>  		RADEONRestoreFP2Registers(pScrn, info->ModeReg);
>  		RADEONRestoreDVOChip(pScrn, output);
> +		if ((radeon_crtc->crtc_id == 0) && info->IsIGP)
> +		    RADEONSelDiv0(pScrn);

Even when I switch those lines so that it applies, it does not work.

> @@ -1419,6 +1423,8 @@ legacy_output_mode_set(xf86OutputPtr output, DisplayModePtr mode,
>      case MT_LCD:
>  	ErrorF("restore LVDS\n");
>  	RADEONRestoreLVDSRegisters(pScrn, info->ModeReg);
> +	if ((radeon_crtc->crtc_id == 0) && (info->ChipFamily == CHIP_FAMILY_RV410))
> +	    RADEONSelDiv0(pScrn);
>  	break;

The cards I have here are 1002:5974 and grep 5974 src/radeon_chipinfo_gen.h
says:
 { 0x5974, CHIP_FAMILY_RS480, 1, 1, 0, 0, 1 },

Thus I added CHIP_FAMILY_RS480 there and then it seems to work. Modified patch
attached.

BTW: I was quite confused by the "ErrorF" there and first thought that
was an error path normaly not used and thus a bit perplexed why changing
that code even helps, but looking at the Xorg.log, it seems to be
actually called....

Hochachtungsvoll,
	Bernhard R. Link
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