tile property contents

[Daniel Vetter]

On Wed, Oct 22, 2014 at 8:34 AM, Andy Ritger <aritger at nvidia.com> wrote:
> I assume the TILE property described below would be per-connector?
>
> It looks like this would handle the DP MST tiled display case.
>
> At the risk of trying to solve too much at once:
>
> There are also configurations where users configure multiple heads to
> drive power walls that they want to be treated as one logical monitor,
> similar to the DP MST tiled display case.  Normally, those powerwall
> configurations don't have any layout information from the monitors
> themselves, and the layout is configured by the user.
>
> Would it be appropriate for users to be able to set the TILE property
> in that sort of scenario?
>
> For the sake of generality, I wonder if max[hv]tiles and [hv]_tile_loc
> should be expressed in pixels rather than tiles?  Sometimes, the tiles
> in those powerwalls may not all have the same resolution, or may be
> configured with overlap.  I suppose that would make the TILE configuration
> specific to the current modetimings on each tile...

Why can't users just set that mode?

And if this is about the initial configuration problem then we (at
intel) are working on some way to load a dt blob as a firmware image
which would contain the entire kms state, and which we'd apply in an
atomic modeset at driver load. Everyone else (boot splash, X, ...)
will then just inherit that config. That should give you even
flicker-free screen walls if you want to ;-)

Cheers, Daniel
-- 
Daniel Vetter
Software Engineer, Intel Corporation
+41 (0) 79 365 57 48 - http://blog.ffwll.ch