xf86-video-r128: Branch 'master' - 13 commits
Connor Behan
cbehan at kemper.freedesktop.org
Mon Jun 25 17:27:32 UTC 2018
src/r128.h | 13 -
src/r128_crtc.c | 532 +++++++++++++++++++++++++++++++++++++++++++++++++++
src/r128_driver.c | 561 ------------------------------------------------------
src/r128_output.c | 23 ++
4 files changed, 561 insertions(+), 568 deletions(-)
New commits:
commit 6f18a15d237b5a6f4ee9d61634ff9bae827398bd
Author: Kevin Brace <kevinbrace at gmx.com>
Date: Sun Jun 17 20:20:06 2018 -0500
Move R128InitDDA2Registers to r128_crtc.c
It does not make sense for this function to be inside r128_driver.c
since it is only called from a function inside r128_crtc.c.
Signed-off-by: Kevin Brace <kevinbrace at gmx.com>
diff --git a/src/r128.h b/src/r128.h
index 464388b..451d5d2 100644
--- a/src/r128.h
+++ b/src/r128.h
@@ -526,7 +526,6 @@ extern void R128InitCommonRegisters(R128SavePtr save, R128InfoPtr info);
extern void R128InitRMXRegisters(R128SavePtr orig, R128SavePtr save, xf86OutputPtr output, DisplayModePtr mode);
extern void R128InitFPRegisters(R128SavePtr orig, R128SavePtr save, xf86OutputPtr output);
extern void R128InitLVDSRegisters(R128SavePtr orig, R128SavePtr save, xf86OutputPtr output);
-extern Bool R128InitDDA2Registers(xf86CrtcPtr crtc, R128SavePtr save, R128PLLPtr pll, DisplayModePtr mode);
extern void R128RestoreCommonRegisters(ScrnInfoPtr pScrn, R128SavePtr restore);
extern void R128RestoreDACRegisters(ScrnInfoPtr pScrn, R128SavePtr restore);
extern void R128RestoreRMXRegisters(ScrnInfoPtr pScrn, R128SavePtr restore);
diff --git a/src/r128_crtc.c b/src/r128_crtc.c
index f4844e0..cb53c8a 100644
--- a/src/r128_crtc.c
+++ b/src/r128_crtc.c
@@ -696,6 +696,82 @@ Bool R128InitDDARegisters(xf86CrtcPtr crtc, R128SavePtr save,
return TRUE;
}
+/* Define DDA2 registers for requested video mode. */
+Bool R128InitDDA2Registers(xf86CrtcPtr crtc, R128SavePtr save,
+ R128PLLPtr pll, DisplayModePtr mode)
+{
+ ScrnInfoPtr pScrn = crtc->scrn;
+ R128InfoPtr info = R128PTR(pScrn);
+ xf86OutputPtr output = R128FirstOutput(crtc);
+ R128OutputPrivatePtr r128_output = output->driver_private;
+
+ int DisplayFifoWidth = 128;
+ int DisplayFifoDepth = 32;
+ int XclkFreq;
+ int VclkFreq;
+ int XclksPerTransfer;
+ int XclksPerTransferPrecise;
+ int UseablePrecision;
+ int Roff;
+ int Ron;
+
+ XclkFreq = pll->xclk;
+
+ VclkFreq = R128Div(pll->reference_freq * save->feedback_div_2,
+ pll->reference_div * save->post_div_2);
+
+ if (info->isDFP && !info->isPro2 && r128_output->PanelXRes > 0) {
+ if (r128_output->PanelXRes != mode->CrtcHDisplay)
+ VclkFreq = (VclkFreq * mode->CrtcHDisplay) / r128_output->PanelXRes;
+ }
+
+ XclksPerTransfer = R128Div(XclkFreq * DisplayFifoWidth,
+ VclkFreq * (info->CurrentLayout.pixel_bytes * 8));
+
+ UseablePrecision = R128MinBits(XclksPerTransfer) + 1;
+
+ XclksPerTransferPrecise = R128Div((XclkFreq * DisplayFifoWidth)
+ << (11 - UseablePrecision),
+ VclkFreq * (info->CurrentLayout.pixel_bytes * 8));
+
+ Roff = XclksPerTransferPrecise * (DisplayFifoDepth - 4);
+
+ Ron = (4 * info->ram->MB
+ + 3 * MAX(info->ram->Trcd - 2, 0)
+ + 2 * info->ram->Trp
+ + info->ram->Twr
+ + info->ram->CL
+ + info->ram->Tr2w
+ + XclksPerTransfer) << (11 - UseablePrecision);
+
+
+ if (Ron + info->ram->Rloop >= Roff) {
+ xf86DrvMsg(pScrn->scrnIndex, X_ERROR,
+ "(Ron = %d) + (Rloop = %d) >= (Roff = %d)\n",
+ Ron, info->ram->Rloop, Roff);
+ return FALSE;
+ }
+
+ save->dda2_config = (XclksPerTransferPrecise
+ | (UseablePrecision << 16)
+ | (info->ram->Rloop << 20));
+
+ /*save->dda2_on_off = (Ron << 16) | Roff;*/
+ /* shift most be 18 otherwise there's corruption on crtc2 */
+ save->dda2_on_off = (Ron << 18) | Roff;
+
+ R128TRACE(("XclkFreq = %d; VclkFreq = %d; per = %d, %d (useable = %d)\n",
+ XclkFreq,
+ VclkFreq,
+ XclksPerTransfer,
+ XclksPerTransferPrecise,
+ UseablePrecision));
+ R128TRACE(("Roff = %d, Ron = %d, Rloop = %d\n",
+ Roff, Ron, info->ram->Rloop));
+
+ return TRUE;
+}
+
static void r128_crtc_load_lut(xf86CrtcPtr crtc);
static void r128_crtc_dpms(xf86CrtcPtr crtc, int mode)
diff --git a/src/r128_driver.c b/src/r128_driver.c
index 8ac8c0e..87395a7 100644
--- a/src/r128_driver.c
+++ b/src/r128_driver.c
@@ -109,10 +109,6 @@
#endif
-#ifndef MAX
-#define MAX(a,b) ((a)>(b)?(a):(b))
-#endif
-
#define USE_CRT_ONLY 0
/* Forward definitions for driver functions */
@@ -2618,82 +2614,6 @@ void R128InitLVDSRegisters(R128SavePtr orig, R128SavePtr save, xf86OutputPtr out
save->lvds_gen_cntl &= ~R128_LVDS_SEL_CRTC2;
}
-/* Define DDA2 registers for requested video mode. */
-Bool R128InitDDA2Registers(xf86CrtcPtr crtc, R128SavePtr save,
- R128PLLPtr pll, DisplayModePtr mode)
-{
- ScrnInfoPtr pScrn = crtc->scrn;
- R128InfoPtr info = R128PTR(pScrn);
- xf86OutputPtr output = R128FirstOutput(crtc);
- R128OutputPrivatePtr r128_output = output->driver_private;
-
- int DisplayFifoWidth = 128;
- int DisplayFifoDepth = 32;
- int XclkFreq;
- int VclkFreq;
- int XclksPerTransfer;
- int XclksPerTransferPrecise;
- int UseablePrecision;
- int Roff;
- int Ron;
-
- XclkFreq = pll->xclk;
-
- VclkFreq = R128Div(pll->reference_freq * save->feedback_div_2,
- pll->reference_div * save->post_div_2);
-
- if (info->isDFP && !info->isPro2 && r128_output->PanelXRes > 0) {
- if (r128_output->PanelXRes != mode->CrtcHDisplay)
- VclkFreq = (VclkFreq * mode->CrtcHDisplay) / r128_output->PanelXRes;
- }
-
- XclksPerTransfer = R128Div(XclkFreq * DisplayFifoWidth,
- VclkFreq * (info->CurrentLayout.pixel_bytes * 8));
-
- UseablePrecision = R128MinBits(XclksPerTransfer) + 1;
-
- XclksPerTransferPrecise = R128Div((XclkFreq * DisplayFifoWidth)
- << (11 - UseablePrecision),
- VclkFreq * (info->CurrentLayout.pixel_bytes * 8));
-
- Roff = XclksPerTransferPrecise * (DisplayFifoDepth - 4);
-
- Ron = (4 * info->ram->MB
- + 3 * MAX(info->ram->Trcd - 2, 0)
- + 2 * info->ram->Trp
- + info->ram->Twr
- + info->ram->CL
- + info->ram->Tr2w
- + XclksPerTransfer) << (11 - UseablePrecision);
-
-
- if (Ron + info->ram->Rloop >= Roff) {
- xf86DrvMsg(pScrn->scrnIndex, X_ERROR,
- "(Ron = %d) + (Rloop = %d) >= (Roff = %d)\n",
- Ron, info->ram->Rloop, Roff);
- return FALSE;
- }
-
- save->dda2_config = (XclksPerTransferPrecise
- | (UseablePrecision << 16)
- | (info->ram->Rloop << 20));
-
- /*save->dda2_on_off = (Ron << 16) | Roff;*/
- /* shift most be 18 otherwise there's corruption on crtc2 */
- save->dda2_on_off = (Ron << 18) | Roff;
-
- R128TRACE(("XclkFreq = %d; VclkFreq = %d; per = %d, %d (useable = %d)\n",
- XclkFreq,
- VclkFreq,
- XclksPerTransfer,
- XclksPerTransferPrecise,
- UseablePrecision));
- R128TRACE(("Roff = %d, Ron = %d, Rloop = %d\n",
- Roff, Ron, info->ram->Rloop));
-
- return TRUE;
-}
-
#if 0
/* Define initial palette for requested video mode. This doesn't do
anything for XFree86 4.0. */
commit 0be9774d038322a779c34a02461342794090cd58
Author: Kevin Brace <kevinbrace at gmx.com>
Date: Sun Jun 17 20:20:05 2018 -0500
Move R128InitDDARegisters to r128_crtc.c
It does not make sense for this function to be inside r128_driver.c
since it is only called from a function inside r128_crtc.c.
Signed-off-by: Kevin Brace <kevinbrace at gmx.com>
diff --git a/src/r128.h b/src/r128.h
index e666dfb..464388b 100644
--- a/src/r128.h
+++ b/src/r128.h
@@ -526,7 +526,6 @@ extern void R128InitCommonRegisters(R128SavePtr save, R128InfoPtr info);
extern void R128InitRMXRegisters(R128SavePtr orig, R128SavePtr save, xf86OutputPtr output, DisplayModePtr mode);
extern void R128InitFPRegisters(R128SavePtr orig, R128SavePtr save, xf86OutputPtr output);
extern void R128InitLVDSRegisters(R128SavePtr orig, R128SavePtr save, xf86OutputPtr output);
-extern Bool R128InitDDARegisters(xf86CrtcPtr crtc, R128SavePtr save, R128PLLPtr pll, DisplayModePtr mode);
extern Bool R128InitDDA2Registers(xf86CrtcPtr crtc, R128SavePtr save, R128PLLPtr pll, DisplayModePtr mode);
extern void R128RestoreCommonRegisters(ScrnInfoPtr pScrn, R128SavePtr restore);
extern void R128RestoreDACRegisters(ScrnInfoPtr pScrn, R128SavePtr restore);
diff --git a/src/r128_crtc.c b/src/r128_crtc.c
index 9750204..f4844e0 100644
--- a/src/r128_crtc.c
+++ b/src/r128_crtc.c
@@ -48,6 +48,11 @@
#include "r128_reg.h"
+#ifndef MAX
+#define MAX(a,b) ((a)>(b)?(a):(b))
+#endif
+
+
/* Define CRTC registers for requested video mode. */
Bool R128InitCrtcRegisters(xf86CrtcPtr crtc, R128SavePtr save, DisplayModePtr mode)
{
@@ -618,6 +623,79 @@ void R128RestorePLL2Registers(ScrnInfoPtr pScrn, R128SavePtr restore)
}
+/* Define DDA registers for requested video mode. */
+Bool R128InitDDARegisters(xf86CrtcPtr crtc, R128SavePtr save,
+ R128PLLPtr pll, DisplayModePtr mode)
+{
+ ScrnInfoPtr pScrn = crtc->scrn;
+ R128InfoPtr info = R128PTR(pScrn);
+ xf86OutputPtr output = R128FirstOutput(crtc);
+ R128OutputPrivatePtr r128_output = output->driver_private;
+
+ int DisplayFifoWidth = 128;
+ int DisplayFifoDepth = 32;
+ int XclkFreq;
+ int VclkFreq;
+ int XclksPerTransfer;
+ int XclksPerTransferPrecise;
+ int UseablePrecision;
+ int Roff;
+ int Ron;
+
+ XclkFreq = pll->xclk;
+
+ VclkFreq = R128Div(pll->reference_freq * save->feedback_div,
+ pll->reference_div * save->post_div);
+
+ if (info->isDFP && !info->isPro2 && r128_output->PanelXRes > 0) {
+ if (r128_output->PanelXRes != mode->CrtcHDisplay)
+ VclkFreq = (VclkFreq * mode->CrtcHDisplay) / r128_output->PanelXRes;
+ }
+
+ XclksPerTransfer = R128Div(XclkFreq * DisplayFifoWidth,
+ VclkFreq * (info->CurrentLayout.pixel_bytes * 8));
+
+ UseablePrecision = R128MinBits(XclksPerTransfer) + 1;
+
+ XclksPerTransferPrecise = R128Div((XclkFreq * DisplayFifoWidth)
+ << (11 - UseablePrecision),
+ VclkFreq * (info->CurrentLayout.pixel_bytes * 8));
+
+ Roff = XclksPerTransferPrecise * (DisplayFifoDepth - 4);
+
+ Ron = (4 * info->ram->MB
+ + 3 * MAX(info->ram->Trcd - 2, 0)
+ + 2 * info->ram->Trp
+ + info->ram->Twr
+ + info->ram->CL
+ + info->ram->Tr2w
+ + XclksPerTransfer) << (11 - UseablePrecision);
+
+ if (Ron + info->ram->Rloop >= Roff) {
+ xf86DrvMsg(pScrn->scrnIndex, X_ERROR,
+ "(Ron = %d) + (Rloop = %d) >= (Roff = %d)\n",
+ Ron, info->ram->Rloop, Roff);
+ return FALSE;
+ }
+
+ save->dda_config = (XclksPerTransferPrecise
+ | (UseablePrecision << 16)
+ | (info->ram->Rloop << 20));
+
+ save->dda_on_off = (Ron << 16) | Roff;
+
+ R128TRACE(("XclkFreq = %d; VclkFreq = %d; per = %d, %d (useable = %d)\n",
+ XclkFreq,
+ VclkFreq,
+ XclksPerTransfer,
+ XclksPerTransferPrecise,
+ UseablePrecision));
+ R128TRACE(("Roff = %d, Ron = %d, Rloop = %d\n",
+ Roff, Ron, info->ram->Rloop));
+
+ return TRUE;
+}
+
static void r128_crtc_load_lut(xf86CrtcPtr crtc);
static void r128_crtc_dpms(xf86CrtcPtr crtc, int mode)
diff --git a/src/r128_driver.c b/src/r128_driver.c
index 2fd9bf2..8ac8c0e 100644
--- a/src/r128_driver.c
+++ b/src/r128_driver.c
@@ -2618,79 +2618,6 @@ void R128InitLVDSRegisters(R128SavePtr orig, R128SavePtr save, xf86OutputPtr out
save->lvds_gen_cntl &= ~R128_LVDS_SEL_CRTC2;
}
-/* Define DDA registers for requested video mode. */
-Bool R128InitDDARegisters(xf86CrtcPtr crtc, R128SavePtr save,
- R128PLLPtr pll, DisplayModePtr mode)
-{
- ScrnInfoPtr pScrn = crtc->scrn;
- R128InfoPtr info = R128PTR(pScrn);
- xf86OutputPtr output = R128FirstOutput(crtc);
- R128OutputPrivatePtr r128_output = output->driver_private;
-
- int DisplayFifoWidth = 128;
- int DisplayFifoDepth = 32;
- int XclkFreq;
- int VclkFreq;
- int XclksPerTransfer;
- int XclksPerTransferPrecise;
- int UseablePrecision;
- int Roff;
- int Ron;
-
- XclkFreq = pll->xclk;
-
- VclkFreq = R128Div(pll->reference_freq * save->feedback_div,
- pll->reference_div * save->post_div);
-
- if (info->isDFP && !info->isPro2 && r128_output->PanelXRes > 0) {
- if (r128_output->PanelXRes != mode->CrtcHDisplay)
- VclkFreq = (VclkFreq * mode->CrtcHDisplay) / r128_output->PanelXRes;
- }
-
- XclksPerTransfer = R128Div(XclkFreq * DisplayFifoWidth,
- VclkFreq * (info->CurrentLayout.pixel_bytes * 8));
-
- UseablePrecision = R128MinBits(XclksPerTransfer) + 1;
-
- XclksPerTransferPrecise = R128Div((XclkFreq * DisplayFifoWidth)
- << (11 - UseablePrecision),
- VclkFreq * (info->CurrentLayout.pixel_bytes * 8));
-
- Roff = XclksPerTransferPrecise * (DisplayFifoDepth - 4);
-
- Ron = (4 * info->ram->MB
- + 3 * MAX(info->ram->Trcd - 2, 0)
- + 2 * info->ram->Trp
- + info->ram->Twr
- + info->ram->CL
- + info->ram->Tr2w
- + XclksPerTransfer) << (11 - UseablePrecision);
-
- if (Ron + info->ram->Rloop >= Roff) {
- xf86DrvMsg(pScrn->scrnIndex, X_ERROR,
- "(Ron = %d) + (Rloop = %d) >= (Roff = %d)\n",
- Ron, info->ram->Rloop, Roff);
- return FALSE;
- }
-
- save->dda_config = (XclksPerTransferPrecise
- | (UseablePrecision << 16)
- | (info->ram->Rloop << 20));
-
- save->dda_on_off = (Ron << 16) | Roff;
-
- R128TRACE(("XclkFreq = %d; VclkFreq = %d; per = %d, %d (useable = %d)\n",
- XclkFreq,
- VclkFreq,
- XclksPerTransfer,
- XclksPerTransferPrecise,
- UseablePrecision));
- R128TRACE(("Roff = %d, Ron = %d, Rloop = %d\n",
- Roff, Ron, info->ram->Rloop));
-
- return TRUE;
-}
-
/* Define DDA2 registers for requested video mode. */
Bool R128InitDDA2Registers(xf86CrtcPtr crtc, R128SavePtr save,
R128PLLPtr pll, DisplayModePtr mode)
commit 732ab99127538b701f71c43086c617b39d9522aa
Author: Kevin Brace <kevinbrace at gmx.com>
Date: Sun Jun 17 20:20:04 2018 -0500
Move R128RestorePLL2Registers to r128_crtc.c
r128_crtc.c is the more logical place this function should be located.
R128PLL2WaitForReadUpdateComplete and R128PLL2WriteUpdate functions were
moved as well.
Signed-off-by: Kevin Brace <kevinbrace at gmx.com>
diff --git a/src/r128_crtc.c b/src/r128_crtc.c
index ef44d0f..9750204 100644
--- a/src/r128_crtc.c
+++ b/src/r128_crtc.c
@@ -460,6 +460,23 @@ static void R128PLLWriteUpdate(ScrnInfoPtr pScrn)
}
+static void R128PLL2WaitForReadUpdateComplete(ScrnInfoPtr pScrn)
+{
+ while (INPLL(pScrn, R128_P2PLL_REF_DIV) & R128_P2PLL_ATOMIC_UPDATE_R);
+}
+
+static void R128PLL2WriteUpdate(ScrnInfoPtr pScrn)
+{
+ R128InfoPtr info = R128PTR(pScrn);
+ unsigned char *R128MMIO = info->MMIO;
+
+ while (INPLL(pScrn, R128_P2PLL_REF_DIV) & R128_P2PLL_ATOMIC_UPDATE_R);
+
+ OUTPLLP(pScrn, R128_P2PLL_REF_DIV,
+ R128_P2PLL_ATOMIC_UPDATE_W,
+ ~(R128_P2PLL_ATOMIC_UPDATE_W));
+}
+
/* Write PLL registers. */
void R128RestorePLLRegisters(ScrnInfoPtr pScrn, R128SavePtr restore)
{
@@ -532,6 +549,74 @@ void R128RestorePLLRegisters(ScrnInfoPtr pScrn, R128SavePtr restore)
}
+/* Write PLL2 registers. */
+void R128RestorePLL2Registers(ScrnInfoPtr pScrn, R128SavePtr restore)
+{
+ R128InfoPtr info = R128PTR(pScrn);
+ unsigned char *R128MMIO = info->MMIO;
+
+ OUTPLLP(pScrn, R128_V2CLK_VCLKTV_CNTL,
+ R128_V2CLK_SRC_SEL_CPUCLK,
+ ~R128_V2CLK_SRC_SEL_MASK);
+
+ OUTPLLP(pScrn,
+ R128_P2PLL_CNTL,
+ R128_P2PLL_RESET
+ | R128_P2PLL_ATOMIC_UPDATE_EN
+ | R128_P2PLL_VGA_ATOMIC_UPDATE_EN,
+ ~(R128_P2PLL_RESET
+ | R128_P2PLL_ATOMIC_UPDATE_EN
+ | R128_P2PLL_VGA_ATOMIC_UPDATE_EN));
+
+#if 1
+ OUTREGP(R128_CLOCK_CNTL_INDEX, 0, R128_PLL2_DIV_SEL_MASK);
+#endif
+
+ /*R128PLL2WaitForReadUpdateComplete(pScrn);*/
+
+ OUTPLLP(pScrn, R128_P2PLL_REF_DIV, restore->p2pll_ref_div, ~R128_P2PLL_REF_DIV_MASK);
+
+/* R128PLL2WriteUpdate(pScrn);
+ R128PLL2WaitForReadUpdateComplete(pScrn);*/
+
+ OUTPLLP(pScrn, R128_P2PLL_DIV_0,
+ restore->p2pll_div_0, ~R128_P2PLL_FB0_DIV_MASK);
+
+/* R128PLL2WriteUpdate(pScrn);
+ R128PLL2WaitForReadUpdateComplete(pScrn);*/
+
+ OUTPLLP(pScrn, R128_P2PLL_DIV_0,
+ restore->p2pll_div_0, ~R128_P2PLL_POST0_DIV_MASK);
+
+ R128PLL2WriteUpdate(pScrn);
+ R128PLL2WaitForReadUpdateComplete(pScrn);
+
+ OUTPLL(R128_HTOTAL2_CNTL, restore->htotal_cntl2);
+
+/* R128PLL2WriteUpdate(pScrn);*/
+
+ OUTPLLP(pScrn, R128_P2PLL_CNTL, 0, ~(R128_P2PLL_RESET
+ | R128_P2PLL_SLEEP
+ | R128_P2PLL_ATOMIC_UPDATE_EN
+ | R128_P2PLL_VGA_ATOMIC_UPDATE_EN));
+
+ R128TRACE(("Wrote: 0x%08x 0x%08x 0x%08x (0x%08x)\n",
+ restore->p2pll_ref_div,
+ restore->p2pll_div_0,
+ restore->htotal_cntl2,
+ INPLL(pScrn, R128_P2PLL_CNTL)));
+ R128TRACE(("Wrote: rd=%d, fd=%d, pd=%d\n",
+ restore->p2pll_ref_div & R128_P2PLL_REF_DIV_MASK,
+ restore->p2pll_div_0 & R128_P2PLL_FB0_DIV_MASK,
+ (restore->p2pll_div_0 & R128_P2PLL_POST0_DIV_MASK) >>16));
+
+ usleep(5000); /* Let the clock to lock */
+
+ OUTPLLP(pScrn, R128_V2CLK_VCLKTV_CNTL,
+ R128_V2CLK_SRC_SEL_P2PLLCLK,
+ ~R128_V2CLK_SRC_SEL_MASK);
+
+}
static void r128_crtc_load_lut(xf86CrtcPtr crtc);
diff --git a/src/r128_driver.c b/src/r128_driver.c
index fd246c1..2fd9bf2 100644
--- a/src/r128_driver.c
+++ b/src/r128_driver.c
@@ -2199,92 +2199,6 @@ void R128RestoreLVDSRegisters(ScrnInfoPtr pScrn, R128SavePtr restore)
}
}
-static void R128PLL2WaitForReadUpdateComplete(ScrnInfoPtr pScrn)
-{
- while (INPLL(pScrn, R128_P2PLL_REF_DIV) & R128_P2PLL_ATOMIC_UPDATE_R);
-}
-
-static void R128PLL2WriteUpdate(ScrnInfoPtr pScrn)
-{
- R128InfoPtr info = R128PTR(pScrn);
- unsigned char *R128MMIO = info->MMIO;
-
- while (INPLL(pScrn, R128_P2PLL_REF_DIV) & R128_P2PLL_ATOMIC_UPDATE_R);
-
- OUTPLLP(pScrn, R128_P2PLL_REF_DIV,
- R128_P2PLL_ATOMIC_UPDATE_W,
- ~(R128_P2PLL_ATOMIC_UPDATE_W));
-}
-
-/* Write PLL2 registers. */
-void R128RestorePLL2Registers(ScrnInfoPtr pScrn, R128SavePtr restore)
-{
- R128InfoPtr info = R128PTR(pScrn);
- unsigned char *R128MMIO = info->MMIO;
-
- OUTPLLP(pScrn, R128_V2CLK_VCLKTV_CNTL,
- R128_V2CLK_SRC_SEL_CPUCLK,
- ~R128_V2CLK_SRC_SEL_MASK);
-
- OUTPLLP(pScrn,
- R128_P2PLL_CNTL,
- R128_P2PLL_RESET
- | R128_P2PLL_ATOMIC_UPDATE_EN
- | R128_P2PLL_VGA_ATOMIC_UPDATE_EN,
- ~(R128_P2PLL_RESET
- | R128_P2PLL_ATOMIC_UPDATE_EN
- | R128_P2PLL_VGA_ATOMIC_UPDATE_EN));
-
-#if 1
- OUTREGP(R128_CLOCK_CNTL_INDEX, 0, R128_PLL2_DIV_SEL_MASK);
-#endif
-
- /*R128PLL2WaitForReadUpdateComplete(pScrn);*/
-
- OUTPLLP(pScrn, R128_P2PLL_REF_DIV, restore->p2pll_ref_div, ~R128_P2PLL_REF_DIV_MASK);
-
-/* R128PLL2WriteUpdate(pScrn);
- R128PLL2WaitForReadUpdateComplete(pScrn);*/
-
- OUTPLLP(pScrn, R128_P2PLL_DIV_0,
- restore->p2pll_div_0, ~R128_P2PLL_FB0_DIV_MASK);
-
-/* R128PLL2WriteUpdate(pScrn);
- R128PLL2WaitForReadUpdateComplete(pScrn);*/
-
- OUTPLLP(pScrn, R128_P2PLL_DIV_0,
- restore->p2pll_div_0, ~R128_P2PLL_POST0_DIV_MASK);
-
- R128PLL2WriteUpdate(pScrn);
- R128PLL2WaitForReadUpdateComplete(pScrn);
-
- OUTPLL(R128_HTOTAL2_CNTL, restore->htotal_cntl2);
-
-/* R128PLL2WriteUpdate(pScrn);*/
-
- OUTPLLP(pScrn, R128_P2PLL_CNTL, 0, ~(R128_P2PLL_RESET
- | R128_P2PLL_SLEEP
- | R128_P2PLL_ATOMIC_UPDATE_EN
- | R128_P2PLL_VGA_ATOMIC_UPDATE_EN));
-
- R128TRACE(("Wrote: 0x%08x 0x%08x 0x%08x (0x%08x)\n",
- restore->p2pll_ref_div,
- restore->p2pll_div_0,
- restore->htotal_cntl2,
- INPLL(pScrn, R128_P2PLL_CNTL)));
- R128TRACE(("Wrote: rd=%d, fd=%d, pd=%d\n",
- restore->p2pll_ref_div & R128_P2PLL_REF_DIV_MASK,
- restore->p2pll_div_0 & R128_P2PLL_FB0_DIV_MASK,
- (restore->p2pll_div_0 & R128_P2PLL_POST0_DIV_MASK) >>16));
-
- usleep(5000); /* Let the clock to lock */
-
- OUTPLLP(pScrn, R128_V2CLK_VCLKTV_CNTL,
- R128_V2CLK_SRC_SEL_P2PLLCLK,
- ~R128_V2CLK_SRC_SEL_MASK);
-
-}
-
/* Write DDA registers. */
void R128RestoreDDARegisters(ScrnInfoPtr pScrn, R128SavePtr restore)
{
commit 9cf18d3f147e38c2c560c5904a71c993ca50a25e
Author: Kevin Brace <kevinbrace at gmx.com>
Date: Sun Jun 17 20:20:03 2018 -0500
Move R128RestorePLLRegisters to r128_crtc.c
r128_crtc.c is the more logical place this function should be located.
R128PLLWaitForReadUpdateComplete and R128PLLWriteUpdate functions were
moved as well.
Signed-off-by: Kevin Brace <kevinbrace at gmx.com>
diff --git a/src/r128_crtc.c b/src/r128_crtc.c
index 3afded9..ef44d0f 100644
--- a/src/r128_crtc.c
+++ b/src/r128_crtc.c
@@ -443,6 +443,95 @@ void R128InitPLL2Registers(xf86CrtcPtr crtc, R128SavePtr save,
save->htotal_cntl2 = 0;
}
+static void R128PLLWaitForReadUpdateComplete(ScrnInfoPtr pScrn)
+{
+ while (INPLL(pScrn, R128_PPLL_REF_DIV) & R128_PPLL_ATOMIC_UPDATE_R);
+}
+
+static void R128PLLWriteUpdate(ScrnInfoPtr pScrn)
+{
+ R128InfoPtr info = R128PTR(pScrn);
+ unsigned char *R128MMIO = info->MMIO;
+
+ while (INPLL(pScrn, R128_PPLL_REF_DIV) & R128_PPLL_ATOMIC_UPDATE_R);
+
+ OUTPLLP(pScrn, R128_PPLL_REF_DIV, R128_PPLL_ATOMIC_UPDATE_W,
+ ~R128_PPLL_ATOMIC_UPDATE_W);
+
+}
+
+/* Write PLL registers. */
+void R128RestorePLLRegisters(ScrnInfoPtr pScrn, R128SavePtr restore)
+{
+ R128InfoPtr info = R128PTR(pScrn);
+ unsigned char *R128MMIO = info->MMIO;
+
+
+ OUTPLLP(pScrn, R128_VCLK_ECP_CNTL,
+ R128_VCLK_SRC_SEL_CPUCLK,
+ ~(R128_VCLK_SRC_SEL_MASK));
+
+ OUTPLLP(pScrn,
+ R128_PPLL_CNTL,
+ R128_PPLL_RESET
+ | R128_PPLL_ATOMIC_UPDATE_EN
+ | R128_PPLL_VGA_ATOMIC_UPDATE_EN,
+ ~(R128_PPLL_RESET
+ | R128_PPLL_ATOMIC_UPDATE_EN
+ | R128_PPLL_VGA_ATOMIC_UPDATE_EN));
+
+ OUTREGP(R128_CLOCK_CNTL_INDEX, R128_PLL_DIV_SEL, ~(R128_PLL_DIV_SEL));
+
+/* R128PLLWaitForReadUpdateComplete(pScrn);*/
+ OUTPLLP(pScrn, R128_PPLL_REF_DIV,
+ restore->ppll_ref_div, ~R128_PPLL_REF_DIV_MASK);
+/* R128PLLWriteUpdate(pScrn);
+
+ R128PLLWaitForReadUpdateComplete(pScrn);*/
+ OUTPLLP(pScrn, R128_PPLL_DIV_3,
+ restore->ppll_div_3, ~R128_PPLL_FB3_DIV_MASK);
+/* R128PLLWriteUpdate(pScrn);*/
+ OUTPLLP(pScrn, R128_PPLL_DIV_3,
+ restore->ppll_div_3, ~R128_PPLL_POST3_DIV_MASK);
+
+ R128PLLWriteUpdate(pScrn);
+ R128PLLWaitForReadUpdateComplete(pScrn);
+
+ OUTPLLP(pScrn, R128_PPLL_DIV_0,
+ restore->ppll_div_0, ~R128_PPLL_FB0_DIV_MASK);
+/* R128PLLWriteUpdate(pScrn);*/
+ OUTPLLP(pScrn, R128_PPLL_DIV_0,
+ restore->ppll_div_0, ~R128_PPLL_POST0_DIV_MASK);
+
+ R128PLLWriteUpdate(pScrn);
+ R128PLLWaitForReadUpdateComplete(pScrn);
+
+ OUTPLL(R128_HTOTAL_CNTL, restore->htotal_cntl);
+/* R128PLLWriteUpdate(pScrn);*/
+
+ OUTPLLP(pScrn, R128_PPLL_CNTL, 0, ~(R128_PPLL_RESET
+ | R128_PPLL_SLEEP
+ | R128_PPLL_ATOMIC_UPDATE_EN
+ | R128_PPLL_VGA_ATOMIC_UPDATE_EN));
+
+ R128TRACE(("Wrote: 0x%08x 0x%08x 0x%08x (0x%08x)\n",
+ restore->ppll_ref_div,
+ restore->ppll_div_3,
+ restore->htotal_cntl,
+ INPLL(pScrn, R128_PPLL_CNTL)));
+ R128TRACE(("Wrote: rd=%d, fd=%d, pd=%d\n",
+ restore->ppll_ref_div & R128_PPLL_REF_DIV_MASK,
+ restore->ppll_div_3 & R128_PPLL_FB3_DIV_MASK,
+ (restore->ppll_div_3 & R128_PPLL_POST3_DIV_MASK) >> 16));
+
+ usleep(5000); /* let the clock lock */
+
+ OUTPLLP(pScrn, R128_VCLK_ECP_CNTL,
+ R128_VCLK_SRC_SEL_PPLLCLK,
+ ~(R128_VCLK_SRC_SEL_MASK));
+
+}
+
static void r128_crtc_load_lut(xf86CrtcPtr crtc);
diff --git a/src/r128_driver.c b/src/r128_driver.c
index 66920fb..fd246c1 100644
--- a/src/r128_driver.c
+++ b/src/r128_driver.c
@@ -2199,23 +2199,6 @@ void R128RestoreLVDSRegisters(ScrnInfoPtr pScrn, R128SavePtr restore)
}
}
-static void R128PLLWaitForReadUpdateComplete(ScrnInfoPtr pScrn)
-{
- while (INPLL(pScrn, R128_PPLL_REF_DIV) & R128_PPLL_ATOMIC_UPDATE_R);
-}
-
-static void R128PLLWriteUpdate(ScrnInfoPtr pScrn)
-{
- R128InfoPtr info = R128PTR(pScrn);
- unsigned char *R128MMIO = info->MMIO;
-
- while (INPLL(pScrn, R128_PPLL_REF_DIV) & R128_PPLL_ATOMIC_UPDATE_R);
-
- OUTPLLP(pScrn, R128_PPLL_REF_DIV, R128_PPLL_ATOMIC_UPDATE_W,
- ~R128_PPLL_ATOMIC_UPDATE_W);
-
-}
-
static void R128PLL2WaitForReadUpdateComplete(ScrnInfoPtr pScrn)
{
while (INPLL(pScrn, R128_P2PLL_REF_DIV) & R128_P2PLL_ATOMIC_UPDATE_R);
@@ -2233,78 +2216,6 @@ static void R128PLL2WriteUpdate(ScrnInfoPtr pScrn)
~(R128_P2PLL_ATOMIC_UPDATE_W));
}
-/* Write PLL registers. */
-void R128RestorePLLRegisters(ScrnInfoPtr pScrn, R128SavePtr restore)
-{
- R128InfoPtr info = R128PTR(pScrn);
- unsigned char *R128MMIO = info->MMIO;
-
-
- OUTPLLP(pScrn, R128_VCLK_ECP_CNTL,
- R128_VCLK_SRC_SEL_CPUCLK,
- ~(R128_VCLK_SRC_SEL_MASK));
-
- OUTPLLP(pScrn,
- R128_PPLL_CNTL,
- R128_PPLL_RESET
- | R128_PPLL_ATOMIC_UPDATE_EN
- | R128_PPLL_VGA_ATOMIC_UPDATE_EN,
- ~(R128_PPLL_RESET
- | R128_PPLL_ATOMIC_UPDATE_EN
- | R128_PPLL_VGA_ATOMIC_UPDATE_EN));
-
- OUTREGP(R128_CLOCK_CNTL_INDEX, R128_PLL_DIV_SEL, ~(R128_PLL_DIV_SEL));
-
-/* R128PLLWaitForReadUpdateComplete(pScrn);*/
- OUTPLLP(pScrn, R128_PPLL_REF_DIV,
- restore->ppll_ref_div, ~R128_PPLL_REF_DIV_MASK);
-/* R128PLLWriteUpdate(pScrn);
-
- R128PLLWaitForReadUpdateComplete(pScrn);*/
- OUTPLLP(pScrn, R128_PPLL_DIV_3,
- restore->ppll_div_3, ~R128_PPLL_FB3_DIV_MASK);
-/* R128PLLWriteUpdate(pScrn);*/
- OUTPLLP(pScrn, R128_PPLL_DIV_3,
- restore->ppll_div_3, ~R128_PPLL_POST3_DIV_MASK);
-
- R128PLLWriteUpdate(pScrn);
- R128PLLWaitForReadUpdateComplete(pScrn);
-
- OUTPLLP(pScrn, R128_PPLL_DIV_0,
- restore->ppll_div_0, ~R128_PPLL_FB0_DIV_MASK);
-/* R128PLLWriteUpdate(pScrn);*/
- OUTPLLP(pScrn, R128_PPLL_DIV_0,
- restore->ppll_div_0, ~R128_PPLL_POST0_DIV_MASK);
-
- R128PLLWriteUpdate(pScrn);
- R128PLLWaitForReadUpdateComplete(pScrn);
-
- OUTPLL(R128_HTOTAL_CNTL, restore->htotal_cntl);
-/* R128PLLWriteUpdate(pScrn);*/
-
- OUTPLLP(pScrn, R128_PPLL_CNTL, 0, ~(R128_PPLL_RESET
- | R128_PPLL_SLEEP
- | R128_PPLL_ATOMIC_UPDATE_EN
- | R128_PPLL_VGA_ATOMIC_UPDATE_EN));
-
- R128TRACE(("Wrote: 0x%08x 0x%08x 0x%08x (0x%08x)\n",
- restore->ppll_ref_div,
- restore->ppll_div_3,
- restore->htotal_cntl,
- INPLL(pScrn, R128_PPLL_CNTL)));
- R128TRACE(("Wrote: rd=%d, fd=%d, pd=%d\n",
- restore->ppll_ref_div & R128_PPLL_REF_DIV_MASK,
- restore->ppll_div_3 & R128_PPLL_FB3_DIV_MASK,
- (restore->ppll_div_3 & R128_PPLL_POST3_DIV_MASK) >> 16));
-
- usleep(5000); /* let the clock lock */
-
- OUTPLLP(pScrn, R128_VCLK_ECP_CNTL,
- R128_VCLK_SRC_SEL_PPLLCLK,
- ~(R128_VCLK_SRC_SEL_MASK));
-
-}
-
/* Write PLL2 registers. */
void R128RestorePLL2Registers(ScrnInfoPtr pScrn, R128SavePtr restore)
{
commit b4edfdf93e2d73e149ff550dfc19de3de145fb71
Author: Kevin Brace <kevinbrace at gmx.com>
Date: Sun Jun 17 12:39:33 2018 -0500
Move R128RestoreDACRegisters to r128_output.c
r128_output.c is the more logical place this function should be located.
Signed-off-by: Kevin Brace <kevinbrace at gmx.com>
diff --git a/src/r128_driver.c b/src/r128_driver.c
index 3a20bbd..66920fb 100644
--- a/src/r128_driver.c
+++ b/src/r128_driver.c
@@ -2144,16 +2144,6 @@ void R128RestoreCommonRegisters(ScrnInfoPtr pScrn, R128SavePtr restore)
OUTREG(R128_CONFIG_CNTL, restore->config_cntl);
}
-/* Write DAC registers */
-void R128RestoreDACRegisters(ScrnInfoPtr pScrn, R128SavePtr restore)
-{
- R128InfoPtr info = R128PTR(pScrn);
- unsigned char *R128MMIO = info->MMIO;
-
- OUTREGP(R128_DAC_CNTL, restore->dac_cntl,
- R128_DAC_RANGE_CNTL | R128_DAC_BLANKING);
-}
-
/* Write RMX registers */
void R128RestoreRMXRegisters(ScrnInfoPtr pScrn, R128SavePtr restore)
{
diff --git a/src/r128_output.c b/src/r128_output.c
index cfcd926..41a2533 100644
--- a/src/r128_output.c
+++ b/src/r128_output.c
@@ -62,6 +62,16 @@ void R128InitDACRegisters(R128SavePtr orig, R128SavePtr save, xf86OutputPtr outp
(info->dac6bits ? 0 : R128_DAC_8BIT_EN));
}
+/* Write DAC registers */
+void R128RestoreDACRegisters(ScrnInfoPtr pScrn, R128SavePtr restore)
+{
+ R128InfoPtr info = R128PTR(pScrn);
+ unsigned char *R128MMIO = info->MMIO;
+
+ OUTREGP(R128_DAC_CNTL, restore->dac_cntl,
+ R128_DAC_RANGE_CNTL | R128_DAC_BLANKING);
+}
+
static void r128_dpms(xf86OutputPtr output, int mode)
{
switch(mode) {
commit 61a116603e57e48714fd3e62310f3df79a9fecc3
Author: Kevin Brace <kevinbrace at gmx.com>
Date: Sun Jun 17 12:39:32 2018 -0500
Move R128InitDACRegisters to r128_output.c
It does not make sense for this function to be inside r128_driver.c
since it is only called from a function inside r128_output.c.
Signed-off-by: Kevin Brace <kevinbrace at gmx.com>
diff --git a/src/r128.h b/src/r128.h
index 4043ec7..e666dfb 100644
--- a/src/r128.h
+++ b/src/r128.h
@@ -523,7 +523,6 @@ extern xf86OutputPtr R128FirstOutput(xf86CrtcPtr crtc);
extern void R128InitVideo(ScreenPtr pScreen);
extern void R128InitCommonRegisters(R128SavePtr save, R128InfoPtr info);
-extern void R128InitDACRegisters(R128SavePtr orig, R128SavePtr save, xf86OutputPtr output);
extern void R128InitRMXRegisters(R128SavePtr orig, R128SavePtr save, xf86OutputPtr output, DisplayModePtr mode);
extern void R128InitFPRegisters(R128SavePtr orig, R128SavePtr save, xf86OutputPtr output);
extern void R128InitLVDSRegisters(R128SavePtr orig, R128SavePtr save, xf86OutputPtr output);
diff --git a/src/r128_driver.c b/src/r128_driver.c
index 591c5eb..3a20bbd 100644
--- a/src/r128_driver.c
+++ b/src/r128_driver.c
@@ -2700,19 +2700,6 @@ void R128InitCommonRegisters(R128SavePtr save, R128InfoPtr info)
save->bus_cntl |= R128_BUS_RD_DISCARD_EN | R128_BUS_RD_ABORT_EN;
}
-/* Define DAC registers for the requested video mode. */
-void R128InitDACRegisters(R128SavePtr orig, R128SavePtr save, xf86OutputPtr output)
-{
- ScrnInfoPtr pScrn = output->scrn;
- R128InfoPtr info = R128PTR(pScrn);
- xf86CrtcPtr crtc = output->crtc;
- R128CrtcPrivatePtr r128_crtc = crtc->driver_private;
-
- save->dac_cntl = (R128_DAC_MASK_ALL | R128_DAC_VGA_ADR_EN |
- (!r128_crtc->crtc_id ? 0 : R128_DAC_CRT_SEL_CRTC2) |
- (info->dac6bits ? 0 : R128_DAC_8BIT_EN));
-}
-
/* Define RMX registers for the requested video mode. */
void R128InitRMXRegisters(R128SavePtr orig, R128SavePtr save,
xf86OutputPtr output, DisplayModePtr mode)
diff --git a/src/r128_output.c b/src/r128_output.c
index 73b4af2..cfcd926 100644
--- a/src/r128_output.c
+++ b/src/r128_output.c
@@ -49,6 +49,19 @@
static void R128ConnectorFindMonitor(ScrnInfoPtr pScrn, xf86OutputPtr output);
+/* Define DAC registers for the requested video mode. */
+void R128InitDACRegisters(R128SavePtr orig, R128SavePtr save, xf86OutputPtr output)
+{
+ ScrnInfoPtr pScrn = output->scrn;
+ R128InfoPtr info = R128PTR(pScrn);
+ xf86CrtcPtr crtc = output->crtc;
+ R128CrtcPrivatePtr r128_crtc = crtc->driver_private;
+
+ save->dac_cntl = (R128_DAC_MASK_ALL | R128_DAC_VGA_ADR_EN |
+ (!r128_crtc->crtc_id ? 0 : R128_DAC_CRT_SEL_CRTC2) |
+ (info->dac6bits ? 0 : R128_DAC_8BIT_EN));
+}
+
static void r128_dpms(xf86OutputPtr output, int mode)
{
switch(mode) {
commit 6713ef02c5ee44f9c519f99934a595e5a5ac378c
Author: Kevin Brace <kevinbrace at gmx.com>
Date: Sun Jun 17 12:39:31 2018 -0500
Move R128RestoreCrtc2Registers to r128_crtc.c
r128_crtc.c is the more logical place this function should be located.
Signed-off-by: Kevin Brace <kevinbrace at gmx.com>
diff --git a/src/r128_crtc.c b/src/r128_crtc.c
index 779a691..3afded9 100644
--- a/src/r128_crtc.c
+++ b/src/r128_crtc.c
@@ -259,6 +259,24 @@ void R128RestoreCrtcRegisters(ScrnInfoPtr pScrn, R128SavePtr restore)
OUTREG(R128_CRTC_PITCH, restore->crtc_pitch);
}
+/* Write CRTC2 registers. */
+void R128RestoreCrtc2Registers(ScrnInfoPtr pScrn, R128SavePtr restore)
+{
+ R128InfoPtr info = R128PTR(pScrn);
+ unsigned char *R128MMIO = info->MMIO;
+
+ OUTREGP(R128_CRTC2_GEN_CNTL, restore->crtc2_gen_cntl,
+ R128_CRTC2_DISP_DIS);
+
+ OUTREG(R128_CRTC2_H_TOTAL_DISP, restore->crtc2_h_total_disp);
+ OUTREG(R128_CRTC2_H_SYNC_STRT_WID, restore->crtc2_h_sync_strt_wid);
+ OUTREG(R128_CRTC2_V_TOTAL_DISP, restore->crtc2_v_total_disp);
+ OUTREG(R128_CRTC2_V_SYNC_STRT_WID, restore->crtc2_v_sync_strt_wid);
+ OUTREG(R128_CRTC2_OFFSET, restore->crtc2_offset);
+ OUTREG(R128_CRTC2_OFFSET_CNTL, restore->crtc2_offset_cntl);
+ OUTREG(R128_CRTC2_PITCH, restore->crtc2_pitch);
+}
+
static Bool R128InitCrtcBase(xf86CrtcPtr crtc, R128SavePtr save, int x, int y)
{
ScrnInfoPtr pScrn = crtc->scrn;
diff --git a/src/r128_driver.c b/src/r128_driver.c
index 3c4d08b..591c5eb 100644
--- a/src/r128_driver.c
+++ b/src/r128_driver.c
@@ -2144,24 +2144,6 @@ void R128RestoreCommonRegisters(ScrnInfoPtr pScrn, R128SavePtr restore)
OUTREG(R128_CONFIG_CNTL, restore->config_cntl);
}
-/* Write CRTC2 registers. */
-void R128RestoreCrtc2Registers(ScrnInfoPtr pScrn, R128SavePtr restore)
-{
- R128InfoPtr info = R128PTR(pScrn);
- unsigned char *R128MMIO = info->MMIO;
-
- OUTREGP(R128_CRTC2_GEN_CNTL, restore->crtc2_gen_cntl,
- R128_CRTC2_DISP_DIS);
-
- OUTREG(R128_CRTC2_H_TOTAL_DISP, restore->crtc2_h_total_disp);
- OUTREG(R128_CRTC2_H_SYNC_STRT_WID, restore->crtc2_h_sync_strt_wid);
- OUTREG(R128_CRTC2_V_TOTAL_DISP, restore->crtc2_v_total_disp);
- OUTREG(R128_CRTC2_V_SYNC_STRT_WID, restore->crtc2_v_sync_strt_wid);
- OUTREG(R128_CRTC2_OFFSET, restore->crtc2_offset);
- OUTREG(R128_CRTC2_OFFSET_CNTL, restore->crtc2_offset_cntl);
- OUTREG(R128_CRTC2_PITCH, restore->crtc2_pitch);
-}
-
/* Write DAC registers */
void R128RestoreDACRegisters(ScrnInfoPtr pScrn, R128SavePtr restore)
{
commit dc218b45075ff1ffe497e25b34c528c5259ef398
Author: Kevin Brace <kevinbrace at gmx.com>
Date: Sun Jun 17 12:39:30 2018 -0500
Move R128RestoreCrtcRegisters to r128_crtc.c
r128_crtc.c is the more logical place this function should be located.
Signed-off-by: Kevin Brace <kevinbrace at gmx.com>
diff --git a/src/r128_crtc.c b/src/r128_crtc.c
index d65c5b7..779a691 100644
--- a/src/r128_crtc.c
+++ b/src/r128_crtc.c
@@ -239,6 +239,26 @@ Bool R128InitCrtc2Registers(xf86CrtcPtr crtc, R128SavePtr save, DisplayModePtr m
return TRUE;
}
+/* Write CRTC registers. */
+void R128RestoreCrtcRegisters(ScrnInfoPtr pScrn, R128SavePtr restore)
+{
+ R128InfoPtr info = R128PTR(pScrn);
+ unsigned char *R128MMIO = info->MMIO;
+
+ OUTREG(R128_CRTC_GEN_CNTL, restore->crtc_gen_cntl);
+
+ OUTREGP(R128_CRTC_EXT_CNTL, restore->crtc_ext_cntl,
+ R128_CRTC_VSYNC_DIS | R128_CRTC_HSYNC_DIS | R128_CRTC_DISPLAY_DIS);
+
+ OUTREG(R128_CRTC_H_TOTAL_DISP, restore->crtc_h_total_disp);
+ OUTREG(R128_CRTC_H_SYNC_STRT_WID, restore->crtc_h_sync_strt_wid);
+ OUTREG(R128_CRTC_V_TOTAL_DISP, restore->crtc_v_total_disp);
+ OUTREG(R128_CRTC_V_SYNC_STRT_WID, restore->crtc_v_sync_strt_wid);
+ OUTREG(R128_CRTC_OFFSET, restore->crtc_offset);
+ OUTREG(R128_CRTC_OFFSET_CNTL, restore->crtc_offset_cntl);
+ OUTREG(R128_CRTC_PITCH, restore->crtc_pitch);
+}
+
static Bool R128InitCrtcBase(xf86CrtcPtr crtc, R128SavePtr save, int x, int y)
{
ScrnInfoPtr pScrn = crtc->scrn;
diff --git a/src/r128_driver.c b/src/r128_driver.c
index 312353d..3c4d08b 100644
--- a/src/r128_driver.c
+++ b/src/r128_driver.c
@@ -2144,26 +2144,6 @@ void R128RestoreCommonRegisters(ScrnInfoPtr pScrn, R128SavePtr restore)
OUTREG(R128_CONFIG_CNTL, restore->config_cntl);
}
-/* Write CRTC registers. */
-void R128RestoreCrtcRegisters(ScrnInfoPtr pScrn, R128SavePtr restore)
-{
- R128InfoPtr info = R128PTR(pScrn);
- unsigned char *R128MMIO = info->MMIO;
-
- OUTREG(R128_CRTC_GEN_CNTL, restore->crtc_gen_cntl);
-
- OUTREGP(R128_CRTC_EXT_CNTL, restore->crtc_ext_cntl,
- R128_CRTC_VSYNC_DIS | R128_CRTC_HSYNC_DIS | R128_CRTC_DISPLAY_DIS);
-
- OUTREG(R128_CRTC_H_TOTAL_DISP, restore->crtc_h_total_disp);
- OUTREG(R128_CRTC_H_SYNC_STRT_WID, restore->crtc_h_sync_strt_wid);
- OUTREG(R128_CRTC_V_TOTAL_DISP, restore->crtc_v_total_disp);
- OUTREG(R128_CRTC_V_SYNC_STRT_WID, restore->crtc_v_sync_strt_wid);
- OUTREG(R128_CRTC_OFFSET, restore->crtc_offset);
- OUTREG(R128_CRTC_OFFSET_CNTL, restore->crtc_offset_cntl);
- OUTREG(R128_CRTC_PITCH, restore->crtc_pitch);
-}
-
/* Write CRTC2 registers. */
void R128RestoreCrtc2Registers(ScrnInfoPtr pScrn, R128SavePtr restore)
{
commit e9564ed077af772dc3f82f15ac4c507ee1c16415
Author: Kevin Brace <kevinbrace at gmx.com>
Date: Sat Jun 16 10:24:37 2018 -0500
Move R128InitPLL2Registers to r128_crtc.c
It does not make sense for this function to be inside r128_driver.c
since it is only called from a function inside r128_crtc.c.
Signed-off-by: Kevin Brace <kevinbrace at gmx.com>
diff --git a/src/r128.h b/src/r128.h
index cde5f40..4043ec7 100644
--- a/src/r128.h
+++ b/src/r128.h
@@ -528,7 +528,6 @@ extern void R128InitRMXRegisters(R128SavePtr orig, R128SavePtr save, xf86
extern void R128InitFPRegisters(R128SavePtr orig, R128SavePtr save, xf86OutputPtr output);
extern void R128InitLVDSRegisters(R128SavePtr orig, R128SavePtr save, xf86OutputPtr output);
extern Bool R128InitDDARegisters(xf86CrtcPtr crtc, R128SavePtr save, R128PLLPtr pll, DisplayModePtr mode);
-extern void R128InitPLL2Registers(xf86CrtcPtr crtc, R128SavePtr save, R128PLLPtr pll, double dot_clock);
extern Bool R128InitDDA2Registers(xf86CrtcPtr crtc, R128SavePtr save, R128PLLPtr pll, DisplayModePtr mode);
extern void R128RestoreCommonRegisters(ScrnInfoPtr pScrn, R128SavePtr restore);
extern void R128RestoreDACRegisters(ScrnInfoPtr pScrn, R128SavePtr restore);
diff --git a/src/r128_crtc.c b/src/r128_crtc.c
index 0ca0adb..d65c5b7 100644
--- a/src/r128_crtc.c
+++ b/src/r128_crtc.c
@@ -350,6 +350,61 @@ static void R128InitPLLRegisters(xf86CrtcPtr crtc, R128SavePtr save,
}
+/* Define PLL2 registers for requested video mode. */
+void R128InitPLL2Registers(xf86CrtcPtr crtc, R128SavePtr save,
+ R128PLLPtr pll, double dot_clock)
+{
+#if R128_DEBUG
+ ScrnInfoPtr pScrn = crtc->scrn;
+#endif
+ unsigned long freq = dot_clock * 100;
+ struct {
+ int divider;
+ int bitvalue;
+ } *post_div,
+ post_divs[] = {
+ /* From RAGE 128 VR/RAGE 128 GL Register
+ Reference Manual (Technical Reference
+ Manual P/N RRG-G04100-C Rev. 0.04), page
+ 3-17 (PLL_DIV_[3:0]). */
+ { 1, 0 }, /* VCLK_SRC */
+ { 2, 1 }, /* VCLK_SRC/2 */
+ { 4, 2 }, /* VCLK_SRC/4 */
+ { 8, 3 }, /* VCLK_SRC/8 */
+
+ { 3, 4 }, /* VCLK_SRC/3 */
+ /* bitvalue = 5 is reserved */
+ { 6, 6 }, /* VCLK_SRC/6 */
+ { 12, 7 }, /* VCLK_SRC/12 */
+ { 0, 0 }
+ };
+
+ if (freq > pll->max_pll_freq) freq = pll->max_pll_freq;
+ if (freq * 12 < pll->min_pll_freq) freq = pll->min_pll_freq / 12;
+
+ for (post_div = &post_divs[0]; post_div->divider; ++post_div) {
+ save->pll_output_freq_2 = post_div->divider * freq;
+ if (save->pll_output_freq_2 >= pll->min_pll_freq
+ && save->pll_output_freq_2 <= pll->max_pll_freq) break;
+ }
+
+ save->dot_clock_freq_2 = freq;
+ save->feedback_div_2 = R128Div(pll->reference_div
+ * save->pll_output_freq_2,
+ pll->reference_freq);
+ save->post_div_2 = post_div->divider;
+
+ R128TRACE(("dc=%d, of=%d, fd=%d, pd=%d\n",
+ save->dot_clock_freq_2,
+ save->pll_output_freq_2,
+ save->feedback_div_2,
+ save->post_div_2));
+
+ save->p2pll_ref_div = pll->reference_div;
+ save->p2pll_div_0 = (save->feedback_div_2 | (post_div->bitvalue<<16));
+ save->htotal_cntl2 = 0;
+}
+
static void r128_crtc_load_lut(xf86CrtcPtr crtc);
diff --git a/src/r128_driver.c b/src/r128_driver.c
index 1875a8c..312353d 100644
--- a/src/r128_driver.c
+++ b/src/r128_driver.c
@@ -2854,61 +2854,6 @@ void R128InitLVDSRegisters(R128SavePtr orig, R128SavePtr save, xf86OutputPtr out
save->lvds_gen_cntl &= ~R128_LVDS_SEL_CRTC2;
}
-/* Define PLL2 registers for requested video mode. */
-void R128InitPLL2Registers(xf86CrtcPtr crtc, R128SavePtr save,
- R128PLLPtr pll, double dot_clock)
-{
-#if R128_DEBUG
- ScrnInfoPtr pScrn = crtc->scrn;
-#endif
- unsigned long freq = dot_clock * 100;
- struct {
- int divider;
- int bitvalue;
- } *post_div,
- post_divs[] = {
- /* From RAGE 128 VR/RAGE 128 GL Register
- Reference Manual (Technical Reference
- Manual P/N RRG-G04100-C Rev. 0.04), page
- 3-17 (PLL_DIV_[3:0]). */
- { 1, 0 }, /* VCLK_SRC */
- { 2, 1 }, /* VCLK_SRC/2 */
- { 4, 2 }, /* VCLK_SRC/4 */
- { 8, 3 }, /* VCLK_SRC/8 */
-
- { 3, 4 }, /* VCLK_SRC/3 */
- /* bitvalue = 5 is reserved */
- { 6, 6 }, /* VCLK_SRC/6 */
- { 12, 7 }, /* VCLK_SRC/12 */
- { 0, 0 }
- };
-
- if (freq > pll->max_pll_freq) freq = pll->max_pll_freq;
- if (freq * 12 < pll->min_pll_freq) freq = pll->min_pll_freq / 12;
-
- for (post_div = &post_divs[0]; post_div->divider; ++post_div) {
- save->pll_output_freq_2 = post_div->divider * freq;
- if (save->pll_output_freq_2 >= pll->min_pll_freq
- && save->pll_output_freq_2 <= pll->max_pll_freq) break;
- }
-
- save->dot_clock_freq_2 = freq;
- save->feedback_div_2 = R128Div(pll->reference_div
- * save->pll_output_freq_2,
- pll->reference_freq);
- save->post_div_2 = post_div->divider;
-
- R128TRACE(("dc=%d, of=%d, fd=%d, pd=%d\n",
- save->dot_clock_freq_2,
- save->pll_output_freq_2,
- save->feedback_div_2,
- save->post_div_2));
-
- save->p2pll_ref_div = pll->reference_div;
- save->p2pll_div_0 = (save->feedback_div_2 | (post_div->bitvalue<<16));
- save->htotal_cntl2 = 0;
-}
-
/* Define DDA registers for requested video mode. */
Bool R128InitDDARegisters(xf86CrtcPtr crtc, R128SavePtr save,
R128PLLPtr pll, DisplayModePtr mode)
commit 07796aa604200a323edeb79d65d16945b60cbc63
Author: Kevin Brace <kevinbrace at gmx.com>
Date: Sat Jun 16 10:24:36 2018 -0500
Move R128InitPLLRegisters to r128_crtc.c
It does not make sense for this function to be inside r128_driver.c
since it is only called from a function inside r128_crtc.c.
Signed-off-by: Kevin Brace <kevinbrace at gmx.com>
diff --git a/src/r128.h b/src/r128.h
index 6142ff8..cde5f40 100644
--- a/src/r128.h
+++ b/src/r128.h
@@ -527,7 +527,6 @@ extern void R128InitDACRegisters(R128SavePtr orig, R128SavePtr save, xf86
extern void R128InitRMXRegisters(R128SavePtr orig, R128SavePtr save, xf86OutputPtr output, DisplayModePtr mode);
extern void R128InitFPRegisters(R128SavePtr orig, R128SavePtr save, xf86OutputPtr output);
extern void R128InitLVDSRegisters(R128SavePtr orig, R128SavePtr save, xf86OutputPtr output);
-extern void R128InitPLLRegisters(xf86CrtcPtr crtc, R128SavePtr save, R128PLLPtr pll, double dot_clock);
extern Bool R128InitDDARegisters(xf86CrtcPtr crtc, R128SavePtr save, R128PLLPtr pll, DisplayModePtr mode);
extern void R128InitPLL2Registers(xf86CrtcPtr crtc, R128SavePtr save, R128PLLPtr pll, double dot_clock);
extern Bool R128InitDDA2Registers(xf86CrtcPtr crtc, R128SavePtr save, R128PLLPtr pll, DisplayModePtr mode);
diff --git a/src/r128_crtc.c b/src/r128_crtc.c
index 534caf6..0ca0adb 100644
--- a/src/r128_crtc.c
+++ b/src/r128_crtc.c
@@ -295,6 +295,61 @@ static Bool R128InitCrtc2Base(xf86CrtcPtr crtc, R128SavePtr save, int x, int y)
return TRUE;
}
+/* Define PLL registers for requested video mode. */
+static void R128InitPLLRegisters(xf86CrtcPtr crtc, R128SavePtr save,
+ R128PLLPtr pll, double dot_clock)
+{
+#if R128_DEBUG
+ ScrnInfoPtr pScrn = crtc->scrn;
+#endif
+ unsigned long freq = dot_clock * 100;
+ struct {
+ int divider;
+ int bitvalue;
+ } *post_div,
+ post_divs[] = {
+ /* From RAGE 128 VR/RAGE 128 GL Register
+ Reference Manual (Technical Reference
+ Manual P/N RRG-G04100-C Rev. 0.04), page
+ 3-17 (PLL_DIV_[3:0]). */
+ { 1, 0 }, /* VCLK_SRC */
+ { 2, 1 }, /* VCLK_SRC/2 */
+ { 4, 2 }, /* VCLK_SRC/4 */
+ { 8, 3 }, /* VCLK_SRC/8 */
+
+ { 3, 4 }, /* VCLK_SRC/3 */
+ /* bitvalue = 5 is reserved */
+ { 6, 6 }, /* VCLK_SRC/6 */
+ { 12, 7 }, /* VCLK_SRC/12 */
+ { 0, 0 }
+ };
+
+ if (freq > pll->max_pll_freq) freq = pll->max_pll_freq;
+ if (freq * 12 < pll->min_pll_freq) freq = pll->min_pll_freq / 12;
+
+ for (post_div = &post_divs[0]; post_div->divider; ++post_div) {
+ save->pll_output_freq = post_div->divider * freq;
+ if (save->pll_output_freq >= pll->min_pll_freq
+ && save->pll_output_freq <= pll->max_pll_freq) break;
+ }
+
+ save->dot_clock_freq = freq;
+ save->feedback_div = R128Div(pll->reference_div * save->pll_output_freq,
+ pll->reference_freq);
+ save->post_div = post_div->divider;
+
+ R128TRACE(("dc=%d, of=%d, fd=%d, pd=%d\n",
+ save->dot_clock_freq,
+ save->pll_output_freq,
+ save->feedback_div,
+ save->post_div));
+
+ save->ppll_ref_div = pll->reference_div;
+ save->ppll_div_3 = (save->feedback_div | (post_div->bitvalue << 16));
+ save->htotal_cntl = 0;
+
+}
+
static void r128_crtc_load_lut(xf86CrtcPtr crtc);
diff --git a/src/r128_driver.c b/src/r128_driver.c
index b814c1e..1875a8c 100644
--- a/src/r128_driver.c
+++ b/src/r128_driver.c
@@ -2854,61 +2854,6 @@ void R128InitLVDSRegisters(R128SavePtr orig, R128SavePtr save, xf86OutputPtr out
save->lvds_gen_cntl &= ~R128_LVDS_SEL_CRTC2;
}
-/* Define PLL registers for requested video mode. */
-void R128InitPLLRegisters(xf86CrtcPtr crtc, R128SavePtr save,
- R128PLLPtr pll, double dot_clock)
-{
-#if R128_DEBUG
- ScrnInfoPtr pScrn = crtc->scrn;
-#endif
- unsigned long freq = dot_clock * 100;
- struct {
- int divider;
- int bitvalue;
- } *post_div,
- post_divs[] = {
- /* From RAGE 128 VR/RAGE 128 GL Register
- Reference Manual (Technical Reference
- Manual P/N RRG-G04100-C Rev. 0.04), page
- 3-17 (PLL_DIV_[3:0]). */
- { 1, 0 }, /* VCLK_SRC */
- { 2, 1 }, /* VCLK_SRC/2 */
- { 4, 2 }, /* VCLK_SRC/4 */
- { 8, 3 }, /* VCLK_SRC/8 */
-
- { 3, 4 }, /* VCLK_SRC/3 */
- /* bitvalue = 5 is reserved */
- { 6, 6 }, /* VCLK_SRC/6 */
- { 12, 7 }, /* VCLK_SRC/12 */
- { 0, 0 }
- };
-
- if (freq > pll->max_pll_freq) freq = pll->max_pll_freq;
- if (freq * 12 < pll->min_pll_freq) freq = pll->min_pll_freq / 12;
-
- for (post_div = &post_divs[0]; post_div->divider; ++post_div) {
- save->pll_output_freq = post_div->divider * freq;
- if (save->pll_output_freq >= pll->min_pll_freq
- && save->pll_output_freq <= pll->max_pll_freq) break;
- }
-
- save->dot_clock_freq = freq;
- save->feedback_div = R128Div(pll->reference_div * save->pll_output_freq,
- pll->reference_freq);
- save->post_div = post_div->divider;
-
- R128TRACE(("dc=%d, of=%d, fd=%d, pd=%d\n",
- save->dot_clock_freq,
- save->pll_output_freq,
- save->feedback_div,
- save->post_div));
-
- save->ppll_ref_div = pll->reference_div;
- save->ppll_div_3 = (save->feedback_div | (post_div->bitvalue << 16));
- save->htotal_cntl = 0;
-
-}
-
/* Define PLL2 registers for requested video mode. */
void R128InitPLL2Registers(xf86CrtcPtr crtc, R128SavePtr save,
R128PLLPtr pll, double dot_clock)
commit c63eb246927f263b20966a76d80efd9acf9713af
Author: Kevin Brace <kevinbrace at gmx.com>
Date: Sat Jun 16 10:24:35 2018 -0500
Convert R128Div to an inline function
Signed-off-by: Kevin Brace <kevinbrace at gmx.com>
diff --git a/src/r128.h b/src/r128.h
index aa98dd0..6142ff8 100644
--- a/src/r128.h
+++ b/src/r128.h
@@ -498,6 +498,12 @@ do { \
info->fifo_slots -= entries; \
} while (0)
+/* Compute n/d with rounding. */
+static inline int R128Div(int n, int d)
+{
+ return (n + (d / 2)) / d;
+}
+
extern R128EntPtr R128EntPriv(ScrnInfoPtr pScrn);
extern void R128WaitForFifoFunction(ScrnInfoPtr pScrn, int entries);
extern void R128WaitForIdle(ScrnInfoPtr pScrn);
diff --git a/src/r128_driver.c b/src/r128_driver.c
index e902d6f..b814c1e 100644
--- a/src/r128_driver.c
+++ b/src/r128_driver.c
@@ -397,12 +397,6 @@ int R128MinBits(int val)
return bits;
}
-/* Compute n/d with rounding. */
-static int R128Div(int n, int d)
-{
- return (n + (d / 2)) / d;
-}
-
/* Finds the first output using a given crtc. */
xf86OutputPtr R128FirstOutput(xf86CrtcPtr crtc)
{
commit 5c494ca862257f1ce839febc8eda68a26353e544
Author: Kevin Brace <kevinbrace at gmx.com>
Date: Sat Jun 16 10:24:34 2018 -0500
Move R128InitCrtc2Base to r128_crtc.c
It does not make sense for this function to be inside r128_driver.c
since it is only called from a function inside r128_crtc.c.
Signed-off-by: Kevin Brace <kevinbrace at gmx.com>
diff --git a/src/r128.h b/src/r128.h
index 769c44f..aa98dd0 100644
--- a/src/r128.h
+++ b/src/r128.h
@@ -523,7 +523,6 @@ extern void R128InitFPRegisters(R128SavePtr orig, R128SavePtr save, xf86O
extern void R128InitLVDSRegisters(R128SavePtr orig, R128SavePtr save, xf86OutputPtr output);
extern void R128InitPLLRegisters(xf86CrtcPtr crtc, R128SavePtr save, R128PLLPtr pll, double dot_clock);
extern Bool R128InitDDARegisters(xf86CrtcPtr crtc, R128SavePtr save, R128PLLPtr pll, DisplayModePtr mode);
-extern Bool R128InitCrtc2Base(xf86CrtcPtr crtc, R128SavePtr save, int x, int y);
extern void R128InitPLL2Registers(xf86CrtcPtr crtc, R128SavePtr save, R128PLLPtr pll, double dot_clock);
extern Bool R128InitDDA2Registers(xf86CrtcPtr crtc, R128SavePtr save, R128PLLPtr pll, DisplayModePtr mode);
extern void R128RestoreCommonRegisters(ScrnInfoPtr pScrn, R128SavePtr restore);
diff --git a/src/r128_crtc.c b/src/r128_crtc.c
index 20a84c0..534caf6 100644
--- a/src/r128_crtc.c
+++ b/src/r128_crtc.c
@@ -267,6 +267,34 @@ static Bool R128InitCrtcBase(xf86CrtcPtr crtc, R128SavePtr save, int x, int y)
return TRUE;
}
+static Bool R128InitCrtc2Base(xf86CrtcPtr crtc, R128SavePtr save, int x, int y)
+{
+ ScrnInfoPtr pScrn = crtc->scrn;
+ R128InfoPtr info = R128PTR(pScrn);
+ int offset = y * info->CurrentLayout.displayWidth + x;
+ int Base = pScrn->fbOffset;
+
+ switch (info->CurrentLayout.pixel_code) {
+ case 15:
+ case 16: offset *= 2; break;
+ case 24: offset *= 3; break;
+ case 32: offset *= 4; break;
+ }
+ Base += offset;
+
+ if (crtc->rotatedData != NULL)
+ Base = pScrn->fbOffset + (char *)crtc->rotatedData - (char *)info->FB;
+
+ Base &= ~7; /* 3 lower bits are always 0 */
+ if (info->CurrentLayout.pixel_code == 24)
+ Base += 8 * (Base % 3); /* Must be multiple of 8 and 3 */
+
+ save->crtc2_offset = Base;
+ save->crtc2_offset_cntl = 0;
+
+ return TRUE;
+}
+
static void r128_crtc_load_lut(xf86CrtcPtr crtc);
diff --git a/src/r128_driver.c b/src/r128_driver.c
index e09bc14..e902d6f 100644
--- a/src/r128_driver.c
+++ b/src/r128_driver.c
@@ -2744,34 +2744,6 @@ void R128InitCommonRegisters(R128SavePtr save, R128InfoPtr info)
save->bus_cntl |= R128_BUS_RD_DISCARD_EN | R128_BUS_RD_ABORT_EN;
}
-Bool R128InitCrtc2Base(xf86CrtcPtr crtc, R128SavePtr save, int x, int y)
-{
- ScrnInfoPtr pScrn = crtc->scrn;
- R128InfoPtr info = R128PTR(pScrn);
- int offset = y * info->CurrentLayout.displayWidth + x;
- int Base = pScrn->fbOffset;
-
- switch (info->CurrentLayout.pixel_code) {
- case 15:
- case 16: offset *= 2; break;
- case 24: offset *= 3; break;
- case 32: offset *= 4; break;
- }
- Base += offset;
-
- if (crtc->rotatedData != NULL)
- Base = pScrn->fbOffset + (char *)crtc->rotatedData - (char *)info->FB;
-
- Base &= ~7; /* 3 lower bits are always 0 */
- if (info->CurrentLayout.pixel_code == 24)
- Base += 8 * (Base % 3); /* Must be multiple of 8 and 3 */
-
- save->crtc2_offset = Base;
- save->crtc2_offset_cntl = 0;
-
- return TRUE;
-}
-
/* Define DAC registers for the requested video mode. */
void R128InitDACRegisters(R128SavePtr orig, R128SavePtr save, xf86OutputPtr output)
{
commit 4e3da789346add1ce4505eb06a7e2c18daa2e843
Author: Kevin Brace <kevinbrace at gmx.com>
Date: Sat Jun 16 10:24:33 2018 -0500
Move R128InitCrtcBase to r128_crtc.c
It does not make sense for this function to be inside r128_driver.c
since it is only called from a function inside r128_crtc.c.
Signed-off-by: Kevin Brace <kevinbrace at gmx.com>
diff --git a/src/r128.h b/src/r128.h
index 5e7aeb9..769c44f 100644
--- a/src/r128.h
+++ b/src/r128.h
@@ -521,7 +521,6 @@ extern void R128InitDACRegisters(R128SavePtr orig, R128SavePtr save, xf86
extern void R128InitRMXRegisters(R128SavePtr orig, R128SavePtr save, xf86OutputPtr output, DisplayModePtr mode);
extern void R128InitFPRegisters(R128SavePtr orig, R128SavePtr save, xf86OutputPtr output);
extern void R128InitLVDSRegisters(R128SavePtr orig, R128SavePtr save, xf86OutputPtr output);
-extern Bool R128InitCrtcBase(xf86CrtcPtr crtc, R128SavePtr save, int x, int y);
extern void R128InitPLLRegisters(xf86CrtcPtr crtc, R128SavePtr save, R128PLLPtr pll, double dot_clock);
extern Bool R128InitDDARegisters(xf86CrtcPtr crtc, R128SavePtr save, R128PLLPtr pll, DisplayModePtr mode);
extern Bool R128InitCrtc2Base(xf86CrtcPtr crtc, R128SavePtr save, int x, int y);
diff --git a/src/r128_crtc.c b/src/r128_crtc.c
index 28e9a44..20a84c0 100644
--- a/src/r128_crtc.c
+++ b/src/r128_crtc.c
@@ -239,6 +239,34 @@ Bool R128InitCrtc2Registers(xf86CrtcPtr crtc, R128SavePtr save, DisplayModePtr m
return TRUE;
}
+static Bool R128InitCrtcBase(xf86CrtcPtr crtc, R128SavePtr save, int x, int y)
+{
+ ScrnInfoPtr pScrn = crtc->scrn;
+ R128InfoPtr info = R128PTR(pScrn);
+ int offset = y * info->CurrentLayout.displayWidth + x;
+ int Base = pScrn->fbOffset;
+
+ switch (info->CurrentLayout.pixel_code) {
+ case 15:
+ case 16: offset *= 2; break;
+ case 24: offset *= 3; break;
+ case 32: offset *= 4; break;
+ }
+ Base += offset;
+
+ if (crtc->rotatedData != NULL)
+ Base = pScrn->fbOffset + (char *)crtc->rotatedData - (char *)info->FB;
+
+ Base &= ~7; /* 3 lower bits are always 0 */
+ if (info->CurrentLayout.pixel_code == 24)
+ Base += 8 * (Base % 3); /* Must be multiple of 8 and 3 */
+
+ save->crtc_offset = Base;
+ save->crtc_offset_cntl = 0;
+
+ return TRUE;
+}
+
static void r128_crtc_load_lut(xf86CrtcPtr crtc);
diff --git a/src/r128_driver.c b/src/r128_driver.c
index 45c76d1..e09bc14 100644
--- a/src/r128_driver.c
+++ b/src/r128_driver.c
@@ -2744,34 +2744,6 @@ void R128InitCommonRegisters(R128SavePtr save, R128InfoPtr info)
save->bus_cntl |= R128_BUS_RD_DISCARD_EN | R128_BUS_RD_ABORT_EN;
}
-Bool R128InitCrtcBase(xf86CrtcPtr crtc, R128SavePtr save, int x, int y)
-{
- ScrnInfoPtr pScrn = crtc->scrn;
- R128InfoPtr info = R128PTR(pScrn);
- int offset = y * info->CurrentLayout.displayWidth + x;
- int Base = pScrn->fbOffset;
-
- switch (info->CurrentLayout.pixel_code) {
- case 15:
- case 16: offset *= 2; break;
- case 24: offset *= 3; break;
- case 32: offset *= 4; break;
- }
- Base += offset;
-
- if (crtc->rotatedData != NULL)
- Base = pScrn->fbOffset + (char *)crtc->rotatedData - (char *)info->FB;
-
- Base &= ~7; /* 3 lower bits are always 0 */
- if (info->CurrentLayout.pixel_code == 24)
- Base += 8 * (Base % 3); /* Must be multiple of 8 and 3 */
-
- save->crtc_offset = Base;
- save->crtc_offset_cntl = 0;
-
- return TRUE;
-}
-
Bool R128InitCrtc2Base(xf86CrtcPtr crtc, R128SavePtr save, int x, int y)
{
ScrnInfoPtr pScrn = crtc->scrn;
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