xf86-video-intel: 2 commits - src/sna/kgem.h src/sna/sna_dri2.c

[Chris Wilson]

 src/sna/kgem.h     |    2 +-
 src/sna/sna_dri2.c |    8 ++------
 2 files changed, 3 insertions(+), 7 deletions(-)

New commits:
commit c89905754b929f0421db7ea6d60b8942ccdbd8af
Author: Chris Wilson <chris at chris-wilson.co.uk>
Date:   Tue Aug 22 20:20:23 2017 +0100

    sna/gen8+: Discard any blt using a LINEAR buffer that is not 64byte aligned
    
    The bug we discovered back in
    
    commit 3a22b6f6d55a5b1e0a1c0a3d597996268ed439ad
    Author: Mika Kuoppala <mika.kuoppala at linux.intel.com>
    Date:   Wed Nov 19 15:10:05 2014 +0200
    
        sna: gen8 BLT broken when address has bit 4 set
    
    turns out to be even wider than our initial finding. It is now
    recommended that you avoid using the BLT on LINEAR addresses that are not
    cache-line aligned (64 bytes). You can convert the offset into a
    coordinate offset (provided the address is at least pixel aligned), but
    that remains quite hairy to fit into the current code base. So keep
    saying no to misaligned blits (we either use the 3D engine instead,
    which may end up thrashing the TLBs given the LINEAR layout, or we just
    use the CPU).
    
    The impact of issuing misaligned blits is that the blitter ends up
    performing the blit presuming the aligned address, causing it to end up
    offset (and vary per line).
    
    Reported-by: Lyude Paul <lyude at redhat.com>
    Signed-off-by: Chris Wilson <chris at chris-wilson.co.uk>

diff --git a/src/sna/kgem.h b/src/sna/kgem.h
index 08b4eb20..b0c38dae 100644
--- a/src/sna/kgem.h
+++ b/src/sna/kgem.h
@@ -587,7 +587,7 @@ static inline bool kgem_bo_can_blt(struct kgem *kgem,
 		return false;
 	}
 
-	if (kgem->gen >= 0100 && bo->proxy && bo->delta & (1 << 4)) {
+	if (kgem->gen >= 0100 && bo->proxy && bo->delta & 63) {
 		DBG(("%s: can not blt to handle=%d, delta=%d\n",
 		     __FUNCTION__, bo->handle, bo->delta));
 		return false;
commit 7534e96ffbe208ec2aa41b1b5848d05749b48797
Author: Chris Wilson <chris at chris-wilson.co.uk>
Date:   Sat Jun 17 20:42:47 2017 +0100

    sna/dri2: Defer the drawable flush
    
    Just flag the DRI2 flush to occur on the next callback flush, as per
    normal, instead of manually emitting the batch.
    
    Signed-off-by: Chris Wilson <chris at chris-wilson.co.uk>

diff --git a/src/sna/sna_dri2.c b/src/sna/sna_dri2.c
index 08660c54..2d822369 100644
--- a/src/sna/sna_dri2.c
+++ b/src/sna/sna_dri2.c
@@ -615,6 +615,8 @@ sna_dri2_create_buffer(DrawablePtr draw,
 	size = (uint32_t)draw->height << 16 | draw->width;
 	switch (attachment) {
 	case DRI2BufferFrontLeft:
+		sna->needs_dri_flush = true;
+
 		pixmap = get_drawable_pixmap(draw);
 		buffer = NULL;
 		if (draw->type != DRAWABLE_PIXMAP)
@@ -643,12 +645,6 @@ sna_dri2_create_buffer(DrawablePtr draw,
 			assert(private->bo->pitch == buffer->pitch);
 			assert(private->bo->active_scanout);
 
-			sna_pixmap_move_to_gpu(pixmap,
-					       MOVE_READ |
-					       __MOVE_FORCE |
-					       __MOVE_DRI);
-			kgem_bo_submit(&sna->kgem, private->bo);
-
 			private->refcnt++;
 			return buffer;
 		}