xf86-video-ati: Branch 'master' - 15 commits
Michel Dänzer
daenzer at kemper.freedesktop.org
Tue Sep 27 09:42:14 UTC 2016
src/drmmode_display.c | 186 ++++++------------------
src/drmmode_display.h | 1
src/pcidb/parse_pci_ids.pl | 7
src/radeon.h | 19 +-
src/radeon_bo_helper.c | 16 +-
src/radeon_chipset_gen.h | 339 +++++++++++++++++++++++++++++++++++++++++++++
src/radeon_dri2.c | 5
src/radeon_glamor.c | 3
src/radeon_kms.c | 46 ++----
src/radeon_present.c | 57 ++++---
src/radeon_probe.c | 4
11 files changed, 478 insertions(+), 205 deletions(-)
New commits:
commit 3fc839ff49f01c24eb94d5e1f0ab4065de47bc17
Author: Michel Dänzer <michel.daenzer at amd.com>
Date: Wed Sep 21 17:50:36 2016 +0900
Only list each unique chipset family once in the log file
(Ported from amdgpu commit 6a1ba044c2b71081e6060d0c096917d6238f2145)
diff --git a/src/pcidb/parse_pci_ids.pl b/src/pcidb/parse_pci_ids.pl
index 4500950..f78e207 100755
--- a/src/pcidb/parse_pci_ids.pl
+++ b/src/pcidb/parse_pci_ids.pl
@@ -16,6 +16,8 @@ my $radeonpcidevicematchfile = 'radeon_pci_device_match_gen.h';
my $radeonchipsetfile = 'radeon_chipset_gen.h';
my $radeonchipinfofile = 'radeon_chipinfo_gen.h';
+my %uniquechipsets;
+
my $csv = Text::CSV_XS->new();
open (CSV, "<", $file) or die $!;
@@ -48,6 +50,7 @@ while (<CSV>) {
print PCIDEVICEMATCH " ATI_DEVICE_MATCH( PCI_CHIP_$columns[1], 0 ),\n";
print RADEONCHIPSET " { PCI_CHIP_$columns[1], \"$columns[8]\" },\n";
+ $uniquechipsets{$columns[8]} = 1;
print RADEONCHIPINFO " { $columns[0], CHIP_FAMILY_$columns[2], ";
@@ -91,6 +94,10 @@ while (<CSV>) {
}
print RADEONCHIPINFO "};\n";
+print RADEONCHIPSET " { -1, NULL }\n};\n\nSymTabRec RADEONUniqueChipsets[] = {\n";
+foreach (sort keys %uniquechipsets) {
+ print RADEONCHIPSET " { 0, \"$_\" },\n";
+}
print RADEONCHIPSET " { -1, NULL }\n};\n";
print PCICHIPSET " { -1, -1, RES_UNDEFINED }\n};\n";
print PCIDEVICEMATCH " { 0, 0, 0 }\n};\n";
diff --git a/src/radeon_chipset_gen.h b/src/radeon_chipset_gen.h
index 5d6d233..ee810cb 100644
--- a/src/radeon_chipset_gen.h
+++ b/src/radeon_chipset_gen.h
@@ -702,3 +702,342 @@ SymTabRec RADEONChipsets[] = {
{ PCI_CHIP_HAWAII_67BE, "HAWAII" },
{ -1, NULL }
};
+
+SymTabRec RADEONUniqueChipsets[] = {
+ { 0, "AMD FireStream 9250" },
+ { 0, "AMD FireStream 9270" },
+ { 0, "AMD Firestream 9170" },
+ { 0, "AMD Firestream 9350" },
+ { 0, "AMD Firestream 9370" },
+ { 0, "AMD Radeon HD 6200 Series Graphics" },
+ { 0, "AMD Radeon HD 6250 Graphics" },
+ { 0, "AMD Radeon HD 6300 Series Graphics" },
+ { 0, "AMD Radeon HD 6310 Graphics" },
+ { 0, "AMD Radeon HD 6700 Series" },
+ { 0, "AMD Radeon HD 6800 Series" },
+ { 0, "AMD Radeon HD 6900 Series" },
+ { 0, "AMD Radeon HD 6900M Series" },
+ { 0, "ARUBA" },
+ { 0, "ATI AMD Stream Processor" },
+ { 0, "ATI ES1000 515E (PCI)" },
+ { 0, "ATI ES1000 5969 (PCI)" },
+ { 0, "ATI FireGL 8700/8800 QH (AGP)" },
+ { 0, "ATI FireGL M22 GL 5464 (PCIE)" },
+ { 0, "ATI FireGL M24 GL 3154 (PCIE)" },
+ { 0, "ATI FireGL Mobility 9000 (M9) Ld (AGP)" },
+ { 0, "ATI FireGL Mobility T2 (M10) NT (AGP)" },
+ { 0, "ATI FireGL Mobility T2e (M11) NV (AGP)" },
+ { 0, "ATI FireGL RV360 AV (AGP)" },
+ { 0, "ATI FireGL T2 AT (AGP)" },
+ { 0, "ATI FireGL V3100 (RV370) 5B64 (PCIE)" },
+ { 0, "ATI FireGL V3200 (RV380) 3E54 (PCIE)" },
+ { 0, "ATI FireGL V3300" },
+ { 0, "ATI FireGL V3350" },
+ { 0, "ATI FireGL V3400" },
+ { 0, "ATI FireGL V3600" },
+ { 0, "ATI FireGL V4000" },
+ { 0, "ATI FireGL V5000 (RV410) (PCIE)" },
+ { 0, "ATI FireGL V5100 (R423) UQ (PCIE)" },
+ { 0, "ATI FireGL V5200" },
+ { 0, "ATI FireGL V5300" },
+ { 0, "ATI FireGL V5600" },
+ { 0, "ATI FireGL V7100 (R423) (PCIE)" },
+ { 0, "ATI FireGL V7200" },
+ { 0, "ATI FireGL V7300" },
+ { 0, "ATI FireGL V7350" },
+ { 0, "ATI FireGL V7400" },
+ { 0, "ATI FireGL V7600" },
+ { 0, "ATI FireGL V7700" },
+ { 0, "ATI FireGL V8600" },
+ { 0, "ATI FireGL V8650" },
+ { 0, "ATI FireGL X1 NG (AGP)" },
+ { 0, "ATI FireGL X2 AK (AGP)" },
+ { 0, "ATI FireGL X2 NK (AGP)" },
+ { 0, "ATI FireGL X3 (R420) JM (AGP)" },
+ { 0, "ATI FireGL Z1 AG (AGP)" },
+ { 0, "ATI FireGL unknown (R423) UR (PCIE)" },
+ { 0, "ATI FireGL unknown (R423) UT (PCIE)" },
+ { 0, "ATI FireMV 2200 (PCI)" },
+ { 0, "ATI FireMV 2200 PCIE (RV370) 5B65 (PCIE)" },
+ { 0, "ATI FireMV 2250" },
+ { 0, "ATI FireMV 2260" },
+ { 0, "ATI FireMV 2400 (PCI)" },
+ { 0, "ATI FireMV 2400 3155 (PCI)" },
+ { 0, "ATI FireMV 2400 PCI" },
+ { 0, "ATI FireMV 2450" },
+ { 0, "ATI FirePro (FireGL) Graphics Adapter" },
+ { 0, "ATI FirePro 2270" },
+ { 0, "ATI FirePro M5750" },
+ { 0, "ATI FirePro M7740" },
+ { 0, "ATI FirePro M7750" },
+ { 0, "ATI FirePro RG220" },
+ { 0, "ATI FirePro RV770" },
+ { 0, "ATI FirePro V3700" },
+ { 0, "ATI FirePro V3750 (FireGL)" },
+ { 0, "ATI FirePro V5700 (FireGL)" },
+ { 0, "ATI FirePro V7750 (FireGL)" },
+ { 0, "ATI FirePro V7760 (FireGL)" },
+ { 0, "ATI FirePro V8700 (FireGL)" },
+ { 0, "ATI FirePro V8750 (FireGL)" },
+ { 0, "ATI Gemini Mobility Radeon HD 2600 XT" },
+ { 0, "ATI Gemini RV630" },
+ { 0, "ATI M54-GL" },
+ { 0, "ATI M98" },
+ { 0, "ATI Mobility FireGL 7800 M7 LX (AGP)" },
+ { 0, "ATI Mobility FireGL Graphics Processor" },
+ { 0, "ATI Mobility FireGL V5000 (M26) (PCIE)" },
+ { 0, "ATI Mobility FireGL V5100 (M28) (PCIE)" },
+ { 0, "ATI Mobility FireGL V5200" },
+ { 0, "ATI Mobility FireGL V5250" },
+ { 0, "ATI Mobility FireGL V5700" },
+ { 0, "ATI Mobility FireGL V5725" },
+ { 0, "ATI Mobility FireGL V7100" },
+ { 0, "ATI Mobility FireGL V7200" },
+ { 0, "ATI Mobility RADEON HD 4850" },
+ { 0, "ATI Mobility RADEON HD 4850 X2" },
+ { 0, "ATI Mobility RADEON HD 4870" },
+ { 0, "ATI Mobility RADEON M98" },
+ { 0, "ATI Mobility Radeon 4100" },
+ { 0, "ATI Mobility Radeon 4300 Series" },
+ { 0, "ATI Mobility Radeon 4330" },
+ { 0, "ATI Mobility Radeon 4500 Series" },
+ { 0, "ATI Mobility Radeon Graphics" },
+ { 0, "ATI Mobility Radeon HD 2300" },
+ { 0, "ATI Mobility Radeon HD 2400" },
+ { 0, "ATI Mobility Radeon HD 2400 XT" },
+ { 0, "ATI Mobility Radeon HD 2600" },
+ { 0, "ATI Mobility Radeon HD 2600 XT" },
+ { 0, "ATI Mobility Radeon HD 3400 Series" },
+ { 0, "ATI Mobility Radeon HD 3430" },
+ { 0, "ATI Mobility Radeon HD 3650" },
+ { 0, "ATI Mobility Radeon HD 3670" },
+ { 0, "ATI Mobility Radeon HD 3850" },
+ { 0, "ATI Mobility Radeon HD 3850 X2" },
+ { 0, "ATI Mobility Radeon HD 3870" },
+ { 0, "ATI Mobility Radeon HD 3870 X2" },
+ { 0, "ATI Mobility Radeon HD 4200" },
+ { 0, "ATI Mobility Radeon HD 4650" },
+ { 0, "ATI Mobility Radeon HD 4670" },
+ { 0, "ATI Mobility Radeon HD 4830" },
+ { 0, "ATI Mobility Radeon HD 4850" },
+ { 0, "ATI Mobility Radeon HD 5000 Series" },
+ { 0, "ATI Mobility Radeon HD 5570" },
+ { 0, "ATI Mobility Radeon HD 5800 Series" },
+ { 0, "ATI Mobility Radeon X1300" },
+ { 0, "ATI Mobility Radeon X1350" },
+ { 0, "ATI Mobility Radeon X1400" },
+ { 0, "ATI Mobility Radeon X1450" },
+ { 0, "ATI Mobility Radeon X1600" },
+ { 0, "ATI Mobility Radeon X1700" },
+ { 0, "ATI Mobility Radeon X1700 XT" },
+ { 0, "ATI Mobility Radeon X1800" },
+ { 0, "ATI Mobility Radeon X1800 XT" },
+ { 0, "ATI Mobility Radeon X1900" },
+ { 0, "ATI Mobility Radeon X2300" },
+ { 0, "ATI Mobility Radeon X700 (M26) (PCIE)" },
+ { 0, "ATI Mobility Radeon X700 XL (M26) (PCIE)" },
+ { 0, "ATI Mobility Radeon X800 (M28) (PCIE)" },
+ { 0, "ATI Mobility Radeon X800 XT (M28) (PCIE)" },
+ { 0, "ATI RADEON E2400" },
+ { 0, "ATI RADEON E4600" },
+ { 0, "ATI RS740" },
+ { 0, "ATI RS740M" },
+ { 0, "ATI RV505" },
+ { 0, "ATI RV560" },
+ { 0, "ATI RV570" },
+ { 0, "ATI RV610" },
+ { 0, "ATI RV630" },
+ { 0, "ATI RV670" },
+ { 0, "ATI RV730 PRO [Radeon HD 4650]" },
+ { 0, "ATI RV730XT [Radeon HD 4670]" },
+ { 0, "ATI RV740" },
+ { 0, "ATI Radeon 3000 Graphics" },
+ { 0, "ATI Radeon 3100 Graphics" },
+ { 0, "ATI Radeon 4100" },
+ { 0, "ATI Radeon 4800 Series" },
+ { 0, "ATI Radeon 7000 IGP (A4+) 4237" },
+ { 0, "ATI Radeon 7500 QW (AGP/PCI)" },
+ { 0, "ATI Radeon 7500 QX (AGP/PCI)" },
+ { 0, "ATI Radeon 8500 AIW BB (AGP)" },
+ { 0, "ATI Radeon 8500 QL (AGP)" },
+ { 0, "ATI Radeon 9000 Ig (AGP/PCI)" },
+ { 0, "ATI Radeon 9000/PRO If (AGP/PCI)" },
+ { 0, "ATI Radeon 9100 IGP (A5) 5834" },
+ { 0, "ATI Radeon 9100 PRO IGP 7834" },
+ { 0, "ATI Radeon 9100 QM (AGP)" },
+ { 0, "ATI Radeon 9200 5961 (AGP)" },
+ { 0, "ATI Radeon 9200 5962 (AGP)" },
+ { 0, "ATI Radeon 9200SE 5964 (AGP)" },
+ { 0, "ATI Radeon 9250 5960 (AGP)" },
+ { 0, "ATI Radeon 9500 AD (AGP)" },
+ { 0, "ATI Radeon 9500 AE (AGP)" },
+ { 0, "ATI Radeon 9600 AP (AGP)" },
+ { 0, "ATI Radeon 9600 AS (AGP)" },
+ { 0, "ATI Radeon 9600SE AQ (AGP)" },
+ { 0, "ATI Radeon 9600TX AF (AGP)" },
+ { 0, "ATI Radeon 9600TX NF (AGP)" },
+ { 0, "ATI Radeon 9600XT AR (AGP)" },
+ { 0, "ATI Radeon 9650" },
+ { 0, "ATI Radeon 9700 Pro ND (AGP)" },
+ { 0, "ATI Radeon 9700/9500Pro NE (AGP)" },
+ { 0, "ATI Radeon 9800 AI (AGP)" },
+ { 0, "ATI Radeon 9800 AJ (AGP)" },
+ { 0, "ATI Radeon 9800 NI (AGP)" },
+ { 0, "ATI Radeon 9800PRO NH (AGP)" },
+ { 0, "ATI Radeon 9800SE AH (AGP)" },
+ { 0, "ATI Radeon 9800XT NJ (AGP)" },
+ { 0, "ATI Radeon HD 2350" },
+ { 0, "ATI Radeon HD 2400 PRO AGP" },
+ { 0, "ATI Radeon HD 2400 Pro" },
+ { 0, "ATI Radeon HD 2400 XT" },
+ { 0, "ATI Radeon HD 2600 LE" },
+ { 0, "ATI Radeon HD 2600 Pro" },
+ { 0, "ATI Radeon HD 2600 Pro AGP" },
+ { 0, "ATI Radeon HD 2600 XT" },
+ { 0, "ATI Radeon HD 2600 XT AGP" },
+ { 0, "ATI Radeon HD 2900 GT" },
+ { 0, "ATI Radeon HD 2900 Pro" },
+ { 0, "ATI Radeon HD 2900 XT" },
+ { 0, "ATI Radeon HD 3200 Graphics" },
+ { 0, "ATI Radeon HD 3300 Graphics" },
+ { 0, "ATI Radeon HD 3430" },
+ { 0, "ATI Radeon HD 3450" },
+ { 0, "ATI Radeon HD 3470" },
+ { 0, "ATI Radeon HD 3600 PRO" },
+ { 0, "ATI Radeon HD 3600 Series" },
+ { 0, "ATI Radeon HD 3600 XT" },
+ { 0, "ATI Radeon HD 3650 AGP" },
+ { 0, "ATI Radeon HD 4200" },
+ { 0, "ATI Radeon HD 4250" },
+ { 0, "ATI Radeon HD 4290" },
+ { 0, "ATI Radeon HD 4350" },
+ { 0, "ATI Radeon HD 4550" },
+ { 0, "ATI Radeon HD 4600 Series" },
+ { 0, "ATI Radeon HD 4700 Series" },
+ { 0, "ATI Radeon HD 4770" },
+ { 0, "ATI Radeon HD 4850 x2" },
+ { 0, "ATI Radeon HD 4870 x2" },
+ { 0, "ATI Radeon HD 5450" },
+ { 0, "ATI Radeon HD 5500 Series" },
+ { 0, "ATI Radeon HD 5570" },
+ { 0, "ATI Radeon HD 5670" },
+ { 0, "ATI Radeon HD 5700 Series" },
+ { 0, "ATI Radeon HD 5800 Series" },
+ { 0, "ATI Radeon HD 5900 Series" },
+ { 0, "ATI Radeon HD 6700 Series" },
+ { 0, "ATI Radeon HD3690" },
+ { 0, "ATI Radeon HD3850" },
+ { 0, "ATI Radeon HD3870" },
+ { 0, "ATI Radeon HD3870 X2" },
+ { 0, "ATI Radeon IGP320 (A3) 4136" },
+ { 0, "ATI Radeon IGP320M (U1) 4336" },
+ { 0, "ATI Radeon IGP330/340/350 (A4) 4137" },
+ { 0, "ATI Radeon IGP330M/340M/350M (U2) 4337" },
+ { 0, "ATI Radeon Mobility 7000 IGP 4437" },
+ { 0, "ATI Radeon Mobility 9000 (M9) Lf (AGP)" },
+ { 0, "ATI Radeon Mobility 9000 (M9) Lg (AGP)" },
+ { 0, "ATI Radeon Mobility 9100 IGP (U3) 5835" },
+ { 0, "ATI Radeon Mobility 9200 (M9+) 5C61 (AGP)" },
+ { 0, "ATI Radeon Mobility 9200 (M9+) 5C63 (AGP)" },
+ { 0, "ATI Radeon Mobility 9200 IGP 7835" },
+ { 0, "ATI Radeon Mobility 9600 (M10) NQ (AGP)" },
+ { 0, "ATI Radeon Mobility 9600 (M10) NS (AGP)" },
+ { 0, "ATI Radeon Mobility 9600 (M11) NR (AGP)" },
+ { 0, "ATI Radeon Mobility 9600/9700 (M10/M11) NP (AGP)" },
+ { 0, "ATI Radeon Mobility 9800 (M18) JN (AGP)" },
+ { 0, "ATI Radeon Mobility M6 LY (AGP)" },
+ { 0, "ATI Radeon Mobility M6 LZ (AGP)" },
+ { 0, "ATI Radeon Mobility M7 LW (AGP)" },
+ { 0, "ATI Radeon Mobility X300 (M22) 5460 (PCIE)" },
+ { 0, "ATI Radeon Mobility X300 (M24) 3152 (PCIE)" },
+ { 0, "ATI Radeon Mobility X600 (M24) 3150 (PCIE)" },
+ { 0, "ATI Radeon Mobility X600 SE (M24C) 5462 (PCIE)" },
+ { 0, "ATI Radeon QD (AGP)" },
+ { 0, "ATI Radeon QE (AGP)" },
+ { 0, "ATI Radeon QF (AGP)" },
+ { 0, "ATI Radeon QG (AGP)" },
+ { 0, "ATI Radeon RV710" },
+ { 0, "ATI Radeon RV730 (AGP)" },
+ { 0, "ATI Radeon VE/7000 QY (AGP/PCI)" },
+ { 0, "ATI Radeon VE/7000 QZ (AGP/PCI)" },
+ { 0, "ATI Radeon X1200" },
+ { 0, "ATI Radeon X1300" },
+ { 0, "ATI Radeon X1300 XT/X1600 Pro" },
+ { 0, "ATI Radeon X1300/X1550" },
+ { 0, "ATI Radeon X1550" },
+ { 0, "ATI Radeon X1550 64-bit" },
+ { 0, "ATI Radeon X1600" },
+ { 0, "ATI Radeon X1650" },
+ { 0, "ATI Radeon X1800" },
+ { 0, "ATI Radeon X1900" },
+ { 0, "ATI Radeon X1950" },
+ { 0, "ATI Radeon X1950 GT" },
+ { 0, "ATI Radeon X2300HD" },
+ { 0, "ATI Radeon X300 (RV370) 5B60 (PCIE)" },
+ { 0, "ATI Radeon X550 (RV370) 5B63 (PCIE)" },
+ { 0, "ATI Radeon X550XTX 5657 (PCIE)" },
+ { 0, "ATI Radeon X600 (RV370) 5B62 (PCIE)" },
+ { 0, "ATI Radeon X600 (RV380) 3E50 (PCIE)" },
+ { 0, "ATI Radeon X700 (RV410) (PCIE)" },
+ { 0, "ATI Radeon X700 PRO (RV410) (PCIE)" },
+ { 0, "ATI Radeon X700 SE (RV410) (PCIE)" },
+ { 0, "ATI Radeon X700 XT (RV410) (PCIE)" },
+ { 0, "ATI Radeon X800 (R420) JH (AGP)" },
+ { 0, "ATI Radeon X800 (R420) JK (AGP)" },
+ { 0, "ATI Radeon X800 (R420) JL (AGP)" },
+ { 0, "ATI Radeon X800 (R423) UH (PCIE)" },
+ { 0, "ATI Radeon X800 (R430) (PCIE)" },
+ { 0, "ATI Radeon X800 SE (R420) (AGP)" },
+ { 0, "ATI Radeon X800 SE (R430) (PCIE)" },
+ { 0, "ATI Radeon X800 VE (R420) JT (AGP)" },
+ { 0, "ATI Radeon X800 XL (R430) (PCIE)" },
+ { 0, "ATI Radeon X800 XTP (R430) (PCIE)" },
+ { 0, "ATI Radeon X800LE (R423) UJ (PCIE)" },
+ { 0, "ATI Radeon X800PRO (R420) JI (AGP)" },
+ { 0, "ATI Radeon X800PRO (R423) UI (PCIE)" },
+ { 0, "ATI Radeon X800SE (R420) JJ (AGP)" },
+ { 0, "ATI Radeon X800SE (R423) UK (PCIE)" },
+ { 0, "ATI Radeon X800XT (R420) JP (AGP)" },
+ { 0, "ATI Radeon X800XT (R423) 5D57 (PCIE)" },
+ { 0, "ATI Radeon X850 (R480) (AGP)" },
+ { 0, "ATI Radeon X850 5D4C (PCIE)" },
+ { 0, "ATI Radeon X850 PRO (R480) (AGP)" },
+ { 0, "ATI Radeon X850 PRO (R480) (PCIE)" },
+ { 0, "ATI Radeon X850 SE (R480) (AGP)" },
+ { 0, "ATI Radeon X850 SE (R480) (PCIE)" },
+ { 0, "ATI Radeon X850 XT (R480) (AGP)" },
+ { 0, "ATI Radeon X850 XT (R480) (PCIE)" },
+ { 0, "ATI Radeon X850 XT PE (R480) (AGP)" },
+ { 0, "ATI Radeon X850 XT PE (R480) (PCIE)" },
+ { 0, "ATI Radeon XPRESS 200 5954 (PCIE)" },
+ { 0, "ATI Radeon XPRESS 200 5974 (PCIE)" },
+ { 0, "ATI Radeon XPRESS 200 5A41 (PCIE)" },
+ { 0, "ATI Radeon XPRESS 200 5A61 (PCIE)" },
+ { 0, "ATI Radeon XPRESS 200M 5955 (PCIE)" },
+ { 0, "ATI Radeon XPRESS 200M 5975 (PCIE)" },
+ { 0, "ATI Radeon XPRESS 200M 5A42 (PCIE)" },
+ { 0, "ATI Radeon XPRESS 200M 5A62 (PCIE)" },
+ { 0, "ATI unknown Radeon / FireGL (R480) 5D50 (PCIE)" },
+ { 0, "BARTS" },
+ { 0, "BONAIRE" },
+ { 0, "CAICOS" },
+ { 0, "CAYMAN" },
+ { 0, "CEDAR" },
+ { 0, "CYPRESS" },
+ { 0, "HAINAN" },
+ { 0, "HAWAII" },
+ { 0, "KABINI" },
+ { 0, "KAVERI" },
+ { 0, "MULLINS" },
+ { 0, "Mobility Radeon HD 6000 Series" },
+ { 0, "OLAND" },
+ { 0, "PALM" },
+ { 0, "PITCAIRN" },
+ { 0, "REDWOOD" },
+ { 0, "SUMO" },
+ { 0, "SUMO2" },
+ { 0, "TAHITI" },
+ { 0, "TURKS" },
+ { 0, "VERDE" },
+ { -1, NULL }
+};
diff --git a/src/radeon_probe.c b/src/radeon_probe.c
index 6d6d8c5..aaace2b 100644
--- a/src/radeon_probe.c
+++ b/src/radeon_probe.c
@@ -78,8 +78,8 @@ static void
RADEONIdentify(int flags)
{
xf86PrintChipsets(RADEON_NAME,
- "Driver for ATI Radeon chipsets",
- RADEONChipsets);
+ "Driver for ATI/AMD Radeon chipsets",
+ RADEONUniqueChipsets);
}
commit 9a5eb1915a240e3021ac38a6dacafef81e7bb743
Author: Michel Dänzer <michel.daenzer at amd.com>
Date: Wed Sep 21 17:48:38 2016 +0900
Clear damage in radeon_scanout_update if it doesn't intersect the CRTC
There's no need to test that same damage again.
(Ported from amdgpu commit a576430526cbc404de64b30e1377a356644e8024)
diff --git a/src/radeon_kms.c b/src/radeon_kms.c
index 384e02f..faa1e0f 100644
--- a/src/radeon_kms.c
+++ b/src/radeon_kms.c
@@ -999,8 +999,10 @@ radeon_scanout_update(xf86CrtcPtr xf86_crtc)
return;
extents = *RegionExtents(pRegion);
- if (!radeon_scanout_extents_intersect(xf86_crtc, &extents))
+ if (!radeon_scanout_extents_intersect(xf86_crtc, &extents)) {
+ RegionEmpty(pRegion);
return;
+ }
scrn = xf86_crtc->scrn;
drm_queue_seq = radeon_drm_queue_alloc(xf86_crtc,
commit 792a30dbe5f7d7815ea14032dbab55b5de8eabca
Author: Michel Dänzer <michel.daenzer at amd.com>
Date: Wed Sep 21 17:43:57 2016 +0900
Remove w/h parameters from radeon_scanout_extents_intersect
We can use the dimensions of the CRTC's mode instead.
(Ported from amdgpu commit ede7f2bcae63be65e05e3029bfe7c742e5978932)
diff --git a/src/radeon_kms.c b/src/radeon_kms.c
index 9d96811..384e02f 100644
--- a/src/radeon_kms.c
+++ b/src/radeon_kms.c
@@ -383,8 +383,7 @@ static Bool RADEONCreateScreenResources_KMS(ScreenPtr pScreen)
}
static Bool
-radeon_scanout_extents_intersect(xf86CrtcPtr xf86_crtc, BoxPtr extents, int w,
- int h)
+radeon_scanout_extents_intersect(xf86CrtcPtr xf86_crtc, BoxPtr extents)
{
extents->x1 -= xf86_crtc->filter_width >> 1;
extents->x2 += xf86_crtc->filter_width >> 1;
@@ -394,8 +393,8 @@ radeon_scanout_extents_intersect(xf86CrtcPtr xf86_crtc, BoxPtr extents, int w,
extents->x1 = max(extents->x1, 0);
extents->y1 = max(extents->y1, 0);
- extents->x2 = min(extents->x2, w);
- extents->y2 = min(extents->y2, h);
+ extents->x2 = min(extents->x2, xf86_crtc->mode.HDisplay);
+ extents->y2 = min(extents->y2, xf86_crtc->mode.VDisplay);
return (extents->x1 < extents->x2 && extents->y1 < extents->y2);
}
@@ -468,8 +467,7 @@ radeon_sync_scanout_pixmaps(xf86CrtcPtr xf86_crtc, RegionPtr new_region,
goto uninit;
extents = *RegionExtents(&remaining);
- if (!radeon_scanout_extents_intersect(xf86_crtc, &extents, dst->width,
- dst->height))
+ if (!radeon_scanout_extents_intersect(xf86_crtc, &extents))
goto uninit;
#if XF86_CRTC_VERSION >= 4
@@ -875,8 +873,7 @@ radeon_scanout_do_update(xf86CrtcPtr xf86_crtc, int scanout_id)
pDraw = &drmmode_crtc->scanout[scanout_id].pixmap->drawable;
extents = *RegionExtents(pRegion);
- if (!radeon_scanout_extents_intersect(xf86_crtc, &extents, pDraw->width,
- pDraw->height))
+ if (!radeon_scanout_extents_intersect(xf86_crtc, &extents))
return FALSE;
if (info->tear_free) {
@@ -985,7 +982,6 @@ radeon_scanout_update(xf86CrtcPtr xf86_crtc)
drmVBlank vbl;
DamagePtr pDamage;
RegionPtr pRegion;
- DrawablePtr pDraw;
BoxRec extents;
if (!xf86_crtc->enabled ||
@@ -1002,10 +998,8 @@ radeon_scanout_update(xf86CrtcPtr xf86_crtc)
if (!RegionNotEmpty(pRegion))
return;
- pDraw = &drmmode_crtc->scanout[0].pixmap->drawable;
extents = *RegionExtents(pRegion);
- if (!radeon_scanout_extents_intersect(xf86_crtc, &extents, pDraw->width,
- pDraw->height))
+ if (!radeon_scanout_extents_intersect(xf86_crtc, &extents))
return;
scrn = xf86_crtc->scrn;
commit 80d794f11a5f047663897e4349da75d89ceff7c7
Author: Michel Dänzer <michel.daenzer at amd.com>
Date: Wed Sep 21 17:38:57 2016 +0900
Make the dedicated scanout mechanism work with arbitrary transforms
This makes TearFree work with arbitrary transforms, and makes transforms
work better even without TearFree, with xserver >= 1.12.
(Ported from amdgpu commit bf000ea7ef91f5ecb59fc3c1ab8ed9eddcc0841d)
diff --git a/src/drmmode_display.c b/src/drmmode_display.c
index 849dc3c..1b1b3e6 100644
--- a/src/drmmode_display.c
+++ b/src/drmmode_display.c
@@ -687,15 +687,15 @@ drmmode_handle_transform(xf86CrtcPtr crtc)
Bool ret;
#if XF86_CRTC_VERSION >= 7
- if (!crtc->transformPresent && crtc->rotation != RR_Rotate_0)
+ if (crtc->transformPresent || crtc->rotation != RR_Rotate_0)
crtc->driverIsPerformingTransform = XF86DriverTransformOutput;
else
crtc->driverIsPerformingTransform = XF86DriverTransformNone;
#else
RADEONInfoPtr info = RADEONPTR(crtc->scrn);
- crtc->driverIsPerformingTransform = info->tear_free &&
- !crtc->transformPresent && crtc->rotation != RR_Rotate_0;
+ crtc->driverIsPerformingTransform = crtc->transformPresent ||
+ (info->tear_free && crtc->rotation != RR_Rotate_0);
#endif
ret = xf86CrtcRotate(crtc);
@@ -815,19 +815,10 @@ drmmode_set_mode_major(xf86CrtcPtr crtc, DisplayModePtr mode,
RegionUninit(pRegion);
pRegion->data = NULL;
pBox = RegionExtents(pRegion);
- pBox->x1 = min(pBox->x1, x);
- pBox->y1 = min(pBox->y1, y);
-
- switch (crtc->rotation & 0xf) {
- case RR_Rotate_90:
- case RR_Rotate_270:
- pBox->x2 = max(pBox->x2, x + mode->VDisplay);
- pBox->y2 = max(pBox->y2, y + mode->HDisplay);
- break;
- default:
- pBox->x2 = max(pBox->x2, x + mode->HDisplay);
- pBox->y2 = max(pBox->y2, y + mode->VDisplay);
- }
+ pBox->x1 = 0;
+ pBox->y1 = 0;
+ pBox->x2 = max(pBox->x2, pScrn->virtualX);
+ pBox->y2 = max(pBox->y2, pScrn->virtualY);
drmmode_crtc->scanout_id = 0;
fb_id = drmmode_crtc->scanout[0].fb_id;
diff --git a/src/radeon_kms.c b/src/radeon_kms.c
index b64c636..9d96811 100644
--- a/src/radeon_kms.c
+++ b/src/radeon_kms.c
@@ -386,19 +386,16 @@ static Bool
radeon_scanout_extents_intersect(xf86CrtcPtr xf86_crtc, BoxPtr extents, int w,
int h)
{
- extents->x1 = max(extents->x1 - xf86_crtc->x, 0);
- extents->y1 = max(extents->y1 - xf86_crtc->y, 0);
-
- switch (xf86_crtc->rotation & 0xf) {
- case RR_Rotate_90:
- case RR_Rotate_270:
- extents->x2 = min(extents->x2 - xf86_crtc->x, h);
- extents->y2 = min(extents->y2 - xf86_crtc->y, w);
- break;
- default:
- extents->x2 = min(extents->x2 - xf86_crtc->x, w);
- extents->y2 = min(extents->y2 - xf86_crtc->y, h);
- }
+ extents->x1 -= xf86_crtc->filter_width >> 1;
+ extents->x2 += xf86_crtc->filter_width >> 1;
+ extents->y1 -= xf86_crtc->filter_height >> 1;
+ extents->y2 += xf86_crtc->filter_height >> 1;
+ pixman_f_transform_bounds(&xf86_crtc->f_framebuffer_to_crtc, extents);
+
+ extents->x1 = max(extents->x1, 0);
+ extents->y1 = max(extents->y1, 0);
+ extents->x2 = min(extents->x2, w);
+ extents->y2 = min(extents->y2, h);
return (extents->x1 < extents->x2 && extents->y1 < extents->y2);
}
@@ -928,12 +925,6 @@ radeon_scanout_do_update(xf86CrtcPtr xf86_crtc, int scanout_id)
SetPicturePictFilter(src, xf86_crtc->filter, xf86_crtc->params,
xf86_crtc->nparams);
- extents.x1 += xf86_crtc->x - (xf86_crtc->filter_width >> 1);
- extents.x2 += xf86_crtc->x + (xf86_crtc->filter_width >> 1);
- extents.y1 += xf86_crtc->y - (xf86_crtc->filter_height >> 1);
- extents.y2 += xf86_crtc->y + (xf86_crtc->filter_height >> 1);
- pixman_f_transform_bounds(&xf86_crtc->f_framebuffer_to_crtc, &extents);
-
pScreen->SourceValidate = NULL;
CompositePicture(PictOpSrc,
src, NULL, dst,
commit 09ba7b3b7b1b724aa386dbf2d33f567d7f26326b
Author: Michel Dänzer <michel.daenzer at amd.com>
Date: Wed Sep 21 17:00:22 2016 +0900
Remove drmmode_load_palette
Not used by any supported version of xserver.
(Ported from amdgpu commits 1091f28e1fa239ee1a973d84a8376fa4a95d7247
and 5a4d3267ac3823fe58b51b0b9075b82375d7180c)
diff --git a/src/drmmode_display.c b/src/drmmode_display.c
index cdfbbe5..849dc3c 100644
--- a/src/drmmode_display.c
+++ b/src/drmmode_display.c
@@ -2498,69 +2498,6 @@ Bool drmmode_set_desired_modes(ScrnInfoPtr pScrn, drmmode_ptr drmmode,
return TRUE;
}
-static void drmmode_load_palette(ScrnInfoPtr pScrn, int numColors,
- int *indices, LOCO *colors, VisualPtr pVisual)
-{
- xf86CrtcConfigPtr xf86_config = XF86_CRTC_CONFIG_PTR(pScrn);
- uint16_t lut_r[256], lut_g[256], lut_b[256];
- int index, j, i;
- int c;
-
- for (c = 0; c < xf86_config->num_crtc; c++) {
- xf86CrtcPtr crtc = xf86_config->crtc[c];
- drmmode_crtc_private_ptr drmmode_crtc = crtc->driver_private;
-
- for (i = 0 ; i < 256; i++) {
- lut_r[i] = drmmode_crtc->lut_r[i] << 6;
- lut_g[i] = drmmode_crtc->lut_g[i] << 6;
- lut_b[i] = drmmode_crtc->lut_b[i] << 6;
- }
-
- switch(pScrn->depth) {
- case 15:
- for (i = 0; i < numColors; i++) {
- index = indices[i];
- for (j = 0; j < 8; j++) {
- lut_r[index * 8 + j] = colors[index].red << 6;
- lut_g[index * 8 + j] = colors[index].green << 6;
- lut_b[index * 8 + j] = colors[index].blue << 6;
- }
- }
- break;
- case 16:
- for (i = 0; i < numColors; i++) {
- index = indices[i];
-
- if (i <= 31) {
- for (j = 0; j < 8; j++) {
- lut_r[index * 8 + j] = colors[index].red << 6;
- lut_b[index * 8 + j] = colors[index].blue << 6;
- }
- }
-
- for (j = 0; j < 4; j++) {
- lut_g[index * 4 + j] = colors[index].green << 6;
- }
- }
- break;
- default:
- for (i = 0; i < numColors; i++) {
- index = indices[i];
- lut_r[index] = colors[index].red << 6;
- lut_g[index] = colors[index].green << 6;
- lut_b[index] = colors[index].blue << 6;
- }
- break;
- }
-
- /* Make the change through RandR */
- if (crtc->randr_crtc)
- RRCrtcGammaSet(crtc->randr_crtc, lut_r, lut_g, lut_b);
- else
- crtc->funcs->gamma_set(crtc, lut_r, lut_g, lut_b, 256);
- }
-}
-
Bool drmmode_setup_colormap(ScreenPtr pScreen, ScrnInfoPtr pScrn)
{
xf86CrtcConfigPtr xf86_config = XF86_CRTC_CONFIG_PTR(pScrn);
@@ -2572,7 +2509,7 @@ Bool drmmode_setup_colormap(ScreenPtr pScreen, ScrnInfoPtr pScrn)
return FALSE;
/* all radeons support 10 bit CLUTs */
if (!xf86HandleColormaps(pScreen, 256, 10,
- drmmode_load_palette, NULL,
+ NULL, NULL,
CMAP_PALETTED_TRUECOLOR
#if 0 /* This option messes up text mode! (eich at suse.de) */
| CMAP_LOAD_EVEN_IF_OFFSCREEN
diff --git a/src/drmmode_display.h b/src/drmmode_display.h
index 7602eb8..ade4a0b 100644
--- a/src/drmmode_display.h
+++ b/src/drmmode_display.h
@@ -96,7 +96,6 @@ typedef struct {
uint32_t dpms_last_seq;
int dpms_last_fps;
uint32_t interpolated_vblanks;
- uint16_t lut_r[256], lut_g[256], lut_b[256];
/* Modeset needed (for DPMS on or after a page flip crossing with a
* modeset)
commit 730f443955cf2bcedd760c9fef5b11c81eacdd84
Author: Michel Dänzer <michel.daenzer at amd.com>
Date: Wed Sep 21 16:48:49 2016 +0900
present: Separate checks for flips vs unflips
All unflip checks apply to flips as well, but not vice versa.
(Ported from amdgpu commit 4d506c23c9a628204fa23607931557b07ada3e31)
diff --git a/src/radeon_present.c b/src/radeon_present.c
index ff4045a..59f3c6b 100644
--- a/src/radeon_present.c
+++ b/src/radeon_present.c
@@ -225,16 +225,13 @@ radeon_present_get_pixmap_tiling_flags(RADEONInfoPtr info, PixmapPtr pixmap)
}
/*
- * Test to see if page flipping is possible on the target crtc
+ * Test to see if unflipping is possible
+ *
+ * These tests have to pass for flips as well
*/
static Bool
-radeon_present_check_flip(RRCrtcPtr crtc, WindowPtr window, PixmapPtr pixmap,
- Bool sync_flip)
+radeon_present_check_unflip(ScrnInfoPtr scrn)
{
- ScreenPtr screen = window->drawable.pScreen;
- ScrnInfoPtr scrn = xf86ScreenToScrn(screen);
- RADEONInfoPtr info = RADEONPTR(scrn);
- PixmapPtr screen_pixmap;
xf86CrtcConfigPtr config = XF86_CRTC_CONFIG_PTR(scrn);
int num_crtcs_on;
int i;
@@ -242,6 +239,35 @@ radeon_present_check_flip(RRCrtcPtr crtc, WindowPtr window, PixmapPtr pixmap,
if (!scrn->vtSema)
return FALSE;
+ for (i = 0, num_crtcs_on = 0; i < config->num_crtc; i++) {
+ drmmode_crtc_private_ptr drmmode_crtc = config->crtc[i]->driver_private;
+
+ if (!config->crtc[i]->enabled)
+ continue;
+
+ if (!drmmode_crtc || drmmode_crtc->rotate.bo ||
+ drmmode_crtc->scanout[0].bo)
+ return FALSE;
+
+ if (drmmode_crtc->pending_dpms_mode == DPMSModeOn)
+ num_crtcs_on++;
+ }
+
+ return num_crtcs_on > 0;
+}
+
+/*
+ * Test to see if page flipping is possible on the target crtc
+ */
+static Bool
+radeon_present_check_flip(RRCrtcPtr crtc, WindowPtr window, PixmapPtr pixmap,
+ Bool sync_flip)
+{
+ ScreenPtr screen = window->drawable.pScreen;
+ ScrnInfoPtr scrn = xf86ScreenToScrn(screen);
+ RADEONInfoPtr info = RADEONPTR(scrn);
+ PixmapPtr screen_pixmap;
+
if (!info->allowPageFlip)
return FALSE;
@@ -259,21 +285,7 @@ radeon_present_check_flip(RRCrtcPtr crtc, WindowPtr window, PixmapPtr pixmap,
radeon_present_get_pixmap_tiling_flags(info, screen_pixmap))
return FALSE;
- for (i = 0, num_crtcs_on = 0; i < config->num_crtc; i++) {
- drmmode_crtc_private_ptr drmmode_crtc = config->crtc[i]->driver_private;
-
- if (!config->crtc[i]->enabled)
- continue;
-
- if (!drmmode_crtc || drmmode_crtc->rotate.bo ||
- drmmode_crtc->scanout[0].bo)
- return FALSE;
-
- if (drmmode_crtc->pending_dpms_mode == DPMSModeOn)
- num_crtcs_on++;
- }
-
- return num_crtcs_on > 0;
+ return radeon_present_check_unflip(scrn);
}
/*
@@ -360,7 +372,7 @@ radeon_present_unflip(ScreenPtr screen, uint64_t event_id)
uint32_t handle;
int i;
- if (!radeon_present_check_flip(NULL, screen->root, pixmap, TRUE))
+ if (!radeon_present_check_unflip(scrn))
goto modeset;
if (!radeon_get_pixmap_handle(pixmap, &handle)) {
commit 343d28672411a510de21fa57986324ef8bcdd1b6
Author: Michel Dänzer <michel.daenzer at amd.com>
Date: Wed Sep 21 16:47:17 2016 +0900
dri2: Don't allow flipping when using a dedicated scanout buffer
Fixes issues when mixing rotation and page flipping with current xserver
Git master.
(Ported from amdgpu commit decabd574f90d3df397c80ec931b3fde8a4afb49)
diff --git a/src/radeon_dri2.c b/src/radeon_dri2.c
index 69fd0ea..1206b2a 100644
--- a/src/radeon_dri2.c
+++ b/src/radeon_dri2.c
@@ -723,7 +723,10 @@ can_exchange(ScrnInfoPtr pScrn, DrawablePtr draw,
for (i = 0; i < xf86_config->num_crtc; i++) {
xf86CrtcPtr crtc = xf86_config->crtc[i];
- if (crtc->enabled && crtc->rotatedData)
+ drmmode_crtc_private_ptr drmmode_crtc = crtc->driver_private;
+
+ if (crtc->enabled &&
+ (crtc->rotatedData || drmmode_crtc->scanout[0].bo))
return FALSE;
}
commit 83e4781d15d66d6fa0e153eb4cd0e3d9e2ebed9f
Author: Michel Dänzer <michel.daenzer at amd.com>
Date: Wed Sep 21 16:44:50 2016 +0900
present: Don't allow flipping when using a dedicated scanout buffer
Fixes issues when mixing rotation and page flipping with current xserver
Git master.
(Ported from amdgpu commit 3ed28ce7cd26f89969617ba901ff253091d0d469)
diff --git a/src/radeon_present.c b/src/radeon_present.c
index 93c18a8..ff4045a 100644
--- a/src/radeon_present.c
+++ b/src/radeon_present.c
@@ -265,7 +265,8 @@ radeon_present_check_flip(RRCrtcPtr crtc, WindowPtr window, PixmapPtr pixmap,
if (!config->crtc[i]->enabled)
continue;
- if (!drmmode_crtc || drmmode_crtc->rotate.bo != NULL)
+ if (!drmmode_crtc || drmmode_crtc->rotate.bo ||
+ drmmode_crtc->scanout[0].bo)
return FALSE;
if (drmmode_crtc->pending_dpms_mode == DPMSModeOn)
commit 8419db3de6157875f9a840773350ecd29cd42d83
Author: Michel Dänzer <michel.daenzer at amd.com>
Date: Wed Sep 21 16:40:42 2016 +0900
Make sure drmmode_crtc->scanout[] are destroyed when not needed
We failed to do this when going back to scanning out directly from the
screen pixmap.
As a bonus, since we now destroy drmmode_crtc->scanout[] after setting
the new scanout buffer, we may avoid the CRTC turning off intermittently
in this case.
(Ported from amdgpu commit 9c3324715fd395fd486ea341654d78f4f298b97f)
diff --git a/src/drmmode_display.c b/src/drmmode_display.c
index 26ba9b1..cdfbbe5 100644
--- a/src/drmmode_display.c
+++ b/src/drmmode_display.c
@@ -781,7 +781,6 @@ drmmode_set_mode_major(xf86CrtcPtr crtc, DisplayModePtr mode,
fb_id = drmmode_crtc->rotate.fb_id;
x = y = 0;
- drmmode_crtc_scanout_free(drmmode_crtc);
} else if (
#ifdef RADEON_PIXMAP_SHARING
!pScreen->isGPU &&
@@ -909,9 +908,13 @@ done:
crtc->y = saved_y;
crtc->rotation = saved_rotation;
crtc->mode = saved_mode;
- } else
+ } else {
crtc->active = TRUE;
+ if (fb_id != drmmode_crtc->scanout[0].fb_id)
+ drmmode_crtc_scanout_free(drmmode_crtc);
+ }
+
free(output_ids);
return ret;
commit 956e03d6a6b9478dd8e77c81f426c0d371c5d7a1
Author: Michel Dänzer <michel.daenzer at amd.com>
Date: Wed Sep 21 16:37:53 2016 +0900
Simplify drmmode_set_mode_major error handling
Initialize ret = FALSE and only set it to TRUE when we've succeeded.
(Ported from amdgpu commit 3bce0519a4008cf87c0e31a7a579e10f5dcdd2f3)
diff --git a/src/drmmode_display.c b/src/drmmode_display.c
index 25c0e99..26ba9b1 100644
--- a/src/drmmode_display.c
+++ b/src/drmmode_display.c
@@ -730,7 +730,7 @@ drmmode_set_mode_major(xf86CrtcPtr crtc, DisplayModePtr mode,
DisplayModeRec saved_mode;
uint32_t *output_ids = NULL;
int output_count = 0;
- Bool ret = TRUE;
+ Bool ret = FALSE;
int i;
int fb_id;
drmModeModeInfo kmode;
@@ -747,10 +747,8 @@ drmmode_set_mode_major(xf86CrtcPtr crtc, DisplayModePtr mode,
crtc->rotation = rotation;
output_ids = calloc(sizeof(uint32_t), xf86_config->num_output);
- if (!output_ids) {
- ret = FALSE;
+ if (!output_ids)
goto done;
- }
for (i = 0; i < xf86_config->num_output; i++) {
xf86OutputPtr output = xf86_config->output[i];
@@ -850,7 +848,6 @@ drmmode_set_mode_major(xf86CrtcPtr crtc, DisplayModePtr mode,
info->front_bo->handle,
&drmmode->fb_id) < 0) {
ErrorF("failed to add fb\n");
- ret = FALSE;
goto done;
}
@@ -867,8 +864,7 @@ drmmode_set_mode_major(xf86CrtcPtr crtc, DisplayModePtr mode,
fb_id, x, y, output_ids,
output_count, &kmode) != 0) {
xf86DrvMsg(crtc->scrn->scrnIndex, X_ERROR,
- "failed to set mode: %s", strerror(errno));
- ret = FALSE;
+ "failed to set mode: %s\n", strerror(errno));
goto done;
} else
ret = TRUE;
commit ace455d1db4db3f9b8b434a3747acfa7e1273db4
Author: Hans de Goede <hdegoede at redhat.com>
Date: Wed Sep 21 16:31:51 2016 +0900
Only add main fb if necessary
If we're doing reverse-prime; or doing rotation the main fb is not used,
and there is no reason to add it in this case.
Signed-off-by: Hans de Goede <hdegoede at redhat.com>
(Ported from xserver commit 4313122dea0df9affc280ee698e929489061ccc6)
(Ported from amdgpu commit a3ca1500703837cbb8d49c554199a25dea7d5e1e)
diff --git a/src/drmmode_display.c b/src/drmmode_display.c
index 4f25ae7..25c0e99 100644
--- a/src/drmmode_display.c
+++ b/src/drmmode_display.c
@@ -734,34 +734,6 @@ drmmode_set_mode_major(xf86CrtcPtr crtc, DisplayModePtr mode,
int i;
int fb_id;
drmModeModeInfo kmode;
- int pitch;
- uint32_t tiling_flags = 0;
-
- if (info->allowColorTiling) {
- if (info->ChipFamily >= CHIP_FAMILY_R600)
- tiling_flags |= RADEON_TILING_MICRO;
- else
- tiling_flags |= RADEON_TILING_MACRO;
- }
-
- pitch = RADEON_ALIGN(pScrn->displayWidth, drmmode_get_pitch_align(pScrn, info->pixel_bytes, tiling_flags)) *
- info->pixel_bytes;
- if (info->ChipFamily >= CHIP_FAMILY_R600) {
- pitch = info->front_surface.level[0].pitch_bytes;
- }
-
- if (drmmode->fb_id == 0) {
- ret = drmModeAddFB(drmmode->fd,
- pScrn->virtualX, pScrn->virtualY,
- pScrn->depth, pScrn->bitsPerPixel,
- pitch,
- info->front_bo->handle,
- &drmmode->fb_id);
- if (ret < 0) {
- ErrorF("failed to add fb\n");
- return FALSE;
- }
- }
saved_mode = crtc->mode;
saved_x = crtc->x;
@@ -869,6 +841,22 @@ drmmode_set_mode_major(xf86CrtcPtr crtc, DisplayModePtr mode,
}
}
+ if (fb_id == 0) {
+ if (drmModeAddFB(drmmode->fd,
+ pScrn->virtualX,
+ pScrn->virtualY,
+ pScrn->depth, pScrn->bitsPerPixel,
+ pScrn->displayWidth * info->pixel_bytes,
+ info->front_bo->handle,
+ &drmmode->fb_id) < 0) {
+ ErrorF("failed to add fb\n");
+ ret = FALSE;
+ goto done;
+ }
+
+ fb_id = drmmode->fb_id;
+ }
+
/* Wait for any pending flip to finish */
do {} while (drmmode_crtc->flip_pending &&
drmHandleEvent(drmmode->fd,
commit eea370dc4f96e680cc29b416fe62d6e2ea09bc91
Author: Hans de Goede <hdegoede at redhat.com>
Date: Wed Sep 21 16:27:11 2016 +0900
Remove unnecessary fb addition from drmmode_xf86crtc_resize
drmmode_set_mode_major() is the only user of drmmode->fb_id and will
create it if necessary.
Signed-off-by: Hans de Goede <hdegoede at redhat.com>
(Ported from xserver commit 877453212166fdc912e0d687cdecee11aba563b5)
(Ported from amdgpu commit 9ca1c24235ff5ab2e028333fc326e2eff008c574)
diff --git a/src/drmmode_display.c b/src/drmmode_display.c
index 89922d6..4f25ae7 100644
--- a/src/drmmode_display.c
+++ b/src/drmmode_display.c
@@ -1982,7 +1982,6 @@ drmmode_xf86crtc_resize (ScrnInfoPtr scrn, int width, int height)
drmmode_ptr drmmode = drmmode_crtc->drmmode;
RADEONInfoPtr info = RADEONPTR(scrn);
struct radeon_bo *old_front = NULL;
- Bool ret;
ScreenPtr screen = xf86ScrnToScreen(scrn);
uint32_t old_fb_id;
int i, pitch, old_width, old_height, old_pitch;
@@ -2085,6 +2084,7 @@ drmmode_xf86crtc_resize (ScrnInfoPtr scrn, int width, int height)
old_height = scrn->virtualY;
old_pitch = scrn->displayWidth;
old_fb_id = drmmode->fb_id;
+ drmmode->fb_id = 0;
old_front = info->front_bo;
scrn->virtualX = width;
@@ -2115,13 +2115,6 @@ drmmode_xf86crtc_resize (ScrnInfoPtr scrn, int width, int height)
if (tiling_flags)
radeon_bo_set_tiling(info->front_bo, tiling_flags, pitch);
- ret = drmModeAddFB(drmmode->fd, width, height, scrn->depth,
- scrn->bitsPerPixel, pitch,
- info->front_bo->handle,
- &drmmode->fb_id);
- if (ret)
- goto fail;
-
if (!info->r600_shadow_fb) {
psurface = radeon_get_pixmap_surface(ppix);
*psurface = info->front_surface;
commit cf52c76484a4adfa3e0b2271ea0c00f46d32ca48
Author: Michel Dänzer <michel.daenzer at amd.com>
Date: Tue Sep 13 18:21:37 2016 +0900
Free priv in amdgpu_set_pixmap_bo also if priv->bo == NULL
Fixes memory leak when destroying pixmaps with priv->bo == NULL.
Reported-by: Qiang Yu <qiang.yu at amd.com>
(Ported from amdgpu commit 7f7f9825caf3983902491da27c16d14cd8bf9b7d)
diff --git a/src/radeon.h b/src/radeon.h
index c914a58..0bf6d37 100644
--- a/src/radeon.h
+++ b/src/radeon.h
@@ -691,11 +691,12 @@ static inline Bool radeon_set_pixmap_bo(PixmapPtr pPix, struct radeon_bo *bo)
return TRUE;
if (priv) {
- if (priv->bo == bo)
- return TRUE;
+ if (priv->bo) {
+ if (priv->bo == bo)
+ return TRUE;
- if (priv->bo)
radeon_bo_unref(priv->bo);
+ }
if (!bo) {
free(priv);
commit 50abcc19e29bb50451d031b2c9e99d691d4faf70
Author: Michel Dänzer <michel.daenzer at amd.com>
Date: Tue Sep 13 18:18:37 2016 +0900
glamor: Fix leak of pixmap private when replacing BO
Reported-by: Qiang Yu <qiang.yu at amd.com>
(Ported from amdgpu commit 397aedafee437c125b8ac1feafb1c3b466842aeb)
diff --git a/src/radeon_glamor.c b/src/radeon_glamor.c
index 7a6bf53..b66848f 100644
--- a/src/radeon_glamor.c
+++ b/src/radeon_glamor.c
@@ -314,10 +314,9 @@ radeon_glamor_set_pixmap_bo(DrawablePtr drawable, PixmapPtr pixmap)
FreeScratchGC(gc);
}
- radeon_set_pixmap_private(pixmap, NULL);
-
/* And redirect the pixmap to the new bo (for 3D). */
glamor_egl_exchange_buffers(old, pixmap);
+ radeon_set_pixmap_private(pixmap, radeon_get_pixmap_private(old));
radeon_set_pixmap_private(old, priv);
screen->ModifyPixmapHeader(old,
commit 8523a733b6a5de6116a6332fefc871d4c32652d8
Author: Michel Dänzer <michel.daenzer at amd.com>
Date: Mon Sep 12 18:54:33 2016 +0900
Propagate failure from radeon_set_pixmap_bo
(Ported from amdgpu commits c315c00e44afc91a7c8e2eab5af836d9643ebb88
and 0d42082108c264568e2aadd15ace70e72388bc65)
diff --git a/src/drmmode_display.c b/src/drmmode_display.c
index a8d4386..89922d6 100644
--- a/src/drmmode_display.c
+++ b/src/drmmode_display.c
@@ -126,12 +126,11 @@ static PixmapPtr drmmode_create_bo_pixmap(ScrnInfoPtr pScrn,
if (!(*pScreen->ModifyPixmapHeader)(pixmap, width, height,
depth, bpp, pitch, NULL)) {
- return NULL;
+ goto fail;
}
if (!info->use_glamor)
exaMoveInPixmap(pixmap);
- radeon_set_pixmap_bo(pixmap, bo);
if (info->ChipFamily >= CHIP_FAMILY_R600) {
surface = radeon_get_pixmap_surface(pixmap);
if (surface && psurf)
@@ -163,22 +162,25 @@ static PixmapPtr drmmode_create_bo_pixmap(ScrnInfoPtr pScrn,
surface->flags |= RADEON_SURF_SET(RADEON_SURF_MODE_2D, MODE);
}
if (radeon_surface_best(info->surf_man, surface)) {
- return NULL;
+ goto fail;
}
if (radeon_surface_init(info->surf_man, surface)) {
- return NULL;
+ goto fail;
}
}
}
- if (info->use_glamor &&
- !radeon_glamor_create_textured_pixmap(pixmap,
- radeon_get_pixmap_private(pixmap))) {
- pScreen->DestroyPixmap(pixmap);
- return NULL;
- }
+ if (!radeon_set_pixmap_bo(pixmap, bo))
+ goto fail;
- return pixmap;
+ if (!info->use_glamor ||
+ radeon_glamor_create_textured_pixmap(pixmap,
+ radeon_get_pixmap_private(pixmap)))
+ return pixmap;
+
+fail:
+ pScreen->DestroyPixmap(pixmap);
+ return NULL;
}
static void drmmode_destroy_bo_pixmap(PixmapPtr pixmap)
@@ -2121,7 +2123,6 @@ drmmode_xf86crtc_resize (ScrnInfoPtr scrn, int width, int height)
goto fail;
if (!info->r600_shadow_fb) {
- radeon_set_pixmap_bo(ppix, info->front_bo);
psurface = radeon_get_pixmap_surface(ppix);
*psurface = info->front_surface;
screen->ModifyPixmapHeader(ppix,
@@ -2145,6 +2146,11 @@ drmmode_xf86crtc_resize (ScrnInfoPtr scrn, int width, int height)
if (info->use_glamor)
radeon_glamor_create_screen_resources(scrn->pScreen);
+ if (!info->r600_shadow_fb) {
+ if (!radeon_set_pixmap_bo(ppix, info->front_bo))
+ goto fail;
+ }
+
/* Clear new buffer */
gc = GetScratchGC(ppix->drawable.depth, scrn->pScreen);
force = info->accel_state->force;
diff --git a/src/radeon.h b/src/radeon.h
index 590966f..c914a58 100644
--- a/src/radeon.h
+++ b/src/radeon.h
@@ -678,7 +678,7 @@ static inline struct radeon_surface *radeon_get_pixmap_surface(PixmapPtr pPix)
uint32_t radeon_get_pixmap_tiling(PixmapPtr pPix);
-static inline void radeon_set_pixmap_bo(PixmapPtr pPix, struct radeon_bo *bo)
+static inline Bool radeon_set_pixmap_bo(PixmapPtr pPix, struct radeon_bo *bo)
{
#ifdef USE_GLAMOR
RADEONInfoPtr info = RADEONPTR(xf86ScreenToScrn(pPix->drawable.pScreen));
@@ -688,11 +688,11 @@ static inline void radeon_set_pixmap_bo(PixmapPtr pPix, struct radeon_bo *bo)
priv = radeon_get_pixmap_private(pPix);
if (priv == NULL && bo == NULL)
- return;
+ return TRUE;
if (priv) {
if (priv->bo == bo)
- return;
+ return TRUE;
if (priv->bo)
radeon_bo_unref(priv->bo);
@@ -709,7 +709,7 @@ static inline void radeon_set_pixmap_bo(PixmapPtr pPix, struct radeon_bo *bo)
if (!priv) {
priv = calloc(1, sizeof (struct radeon_pixmap));
if (!priv)
- goto out;
+ return FALSE;
}
radeon_bo_ref(bo);
@@ -717,8 +717,9 @@ static inline void radeon_set_pixmap_bo(PixmapPtr pPix, struct radeon_bo *bo)
radeon_bo_get_tiling(bo, &priv->tiling_flags, &pitch);
}
-out:
+
radeon_set_pixmap_private(pPix, priv);
+ return TRUE;
} else
#endif /* USE_GLAMOR */
{
@@ -735,7 +736,10 @@ out:
driver_priv->bo = bo;
radeon_bo_get_tiling(bo, &driver_priv->tiling_flags, &pitch);
+ return TRUE;
}
+
+ return FALSE;
}
}
diff --git a/src/radeon_bo_helper.c b/src/radeon_bo_helper.c
index 531bc45..933dc7b 100644
--- a/src/radeon_bo_helper.c
+++ b/src/radeon_bo_helper.c
@@ -312,14 +312,17 @@ Bool radeon_set_shared_pixmap_backing(PixmapPtr ppix, void *fd_handle,
struct radeon_bo *bo;
int ihandle = (int)(long)fd_handle;
uint32_t size = ppix->devKind * ppix->drawable.height;
+ Bool ret = FALSE;
bo = radeon_gem_bo_open_prime(info->bufmgr, ihandle, size);
if (!bo)
- return FALSE;
+ goto error;
memset(surface, 0, sizeof(struct radeon_surface));
- radeon_set_pixmap_bo(ppix, bo);
+ ret = radeon_set_pixmap_bo(ppix, bo);
+ if (!ret)
+ goto error;
if (info->ChipFamily >= CHIP_FAMILY_R600 && info->surf_man) {
uint32_t tiling_flags;
@@ -360,10 +363,12 @@ Bool radeon_set_shared_pixmap_backing(PixmapPtr ppix, void *fd_handle,
surface->stencil_tile_split = (tiling_flags >> RADEON_TILING_EG_STENCIL_TILE_SPLIT_SHIFT) & RADEON_TILING_EG_STENCIL_TILE_SPLIT_MASK;
surface->mtilea = (tiling_flags >> RADEON_TILING_EG_MACRO_TILE_ASPECT_SHIFT) & RADEON_TILING_EG_MACRO_TILE_ASPECT_MASK;
if (radeon_surface_best(info->surf_man, surface)) {
- return FALSE;
+ ret = FALSE;
+ goto error;
}
if (radeon_surface_init(info->surf_man, surface)) {
- return FALSE;
+ ret = FALSE;
+ goto error;
}
/* we have to post hack the surface to reflect the actual size
of the shared pixmap */
@@ -371,11 +376,12 @@ Bool radeon_set_shared_pixmap_backing(PixmapPtr ppix, void *fd_handle,
surface->level[0].nblk_x = ppix->devKind / surface->bpe;
}
+ error:
close(ihandle);
/* we have a reference from the alloc and one from set pixmap bo,
drop one */
radeon_bo_unref(bo);
- return TRUE;
+ return ret;
}
#endif /* RADEON_PIXMAP_SHARING */
diff --git a/src/radeon_kms.c b/src/radeon_kms.c
index 4a5f9da..b64c636 100644
--- a/src/radeon_kms.c
+++ b/src/radeon_kms.c
@@ -347,7 +347,8 @@ static Bool RADEONCreateScreenResources_KMS(ScreenPtr pScreen)
if (info->dri2.enabled || info->use_glamor) {
if (info->front_bo) {
PixmapPtr pPix = pScreen->GetScreenPixmap(pScreen);
- radeon_set_pixmap_bo(pPix, info->front_bo);
+ if (!radeon_set_pixmap_bo(pPix, info->front_bo))
+ return FALSE;
surface = radeon_get_pixmap_surface(pPix);
if (surface) {
*surface = info->front_surface;
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