xf86-video-intel: src/uxa/i830_reg.h src/uxa/intel_batchbuffer.c src/uxa/intel_batchbuffer.h src/uxa/intel.h src/uxa/intel_present.c src/uxa/intel_uxa.c
Chris Wilson
ickle at kemper.freedesktop.org
Fri Apr 22 21:49:47 UTC 2016
src/uxa/i830_reg.h | 6 ++++++
src/uxa/intel.h | 1 +
src/uxa/intel_batchbuffer.c | 11 +++++++++++
src/uxa/intel_batchbuffer.h | 19 ++++++++++++++++++-
src/uxa/intel_present.c | 7 +++++++
src/uxa/intel_uxa.c | 29 +++++++++++++++++++++++++++--
6 files changed, 70 insertions(+), 3 deletions(-)
New commits:
commit cac8e1ee74fa8704a42a5c5ebe65d5ec777cbd67
Author: Chris Wilson <chris at chris-wilson.co.uk>
Date: Fri Apr 22 21:28:34 2016 +0100
uxa: Enable Y-tiling BLT support
Mesa wants to pass Y-tiled framebuffers onto scanout. Admittedly, this
isn't quite that but it does prevent them being jumbled up.
Signed-off-by: Chris Wilson <chris at chris-wilson.co.uk>
diff --git a/src/uxa/i830_reg.h b/src/uxa/i830_reg.h
index d8306bc..ba39d82 100644
--- a/src/uxa/i830_reg.h
+++ b/src/uxa/i830_reg.h
@@ -65,6 +65,12 @@
#define MI_LOAD_SCAN_LINES_DISPLAY_PIPEA (0)
#define MI_LOAD_SCAN_LINES_DISPLAY_PIPEB (0x1<<20)
+#define MI_LOAD_REGISTER_IMM (0x22<<23 | (3-2))
+
+#define BCS_SWCTRL 0x22200
+# define BCS_SWCTRL_SRC_Y (1 << 0)
+# define BCS_SWCTRL_DST_Y (1 << 1)
+
/* BLT commands */
#define COLOR_BLT_CMD ((2<<29)|(0x40<<22)|(0x3))
#define COLOR_BLT_WRITE_ALPHA (1<<21)
diff --git a/src/uxa/intel.h b/src/uxa/intel.h
index 37b23e9..054b626 100644
--- a/src/uxa/intel.h
+++ b/src/uxa/intel.h
@@ -168,6 +168,7 @@ typedef struct intel_screen_private {
const struct intel_device_info *info;
unsigned int BR[20];
+ unsigned int BR_tiling[2];
CloseScreenProcPtr CloseScreen;
diff --git a/src/uxa/intel_batchbuffer.c b/src/uxa/intel_batchbuffer.c
index a29e443..114c602 100644
--- a/src/uxa/intel_batchbuffer.c
+++ b/src/uxa/intel_batchbuffer.c
@@ -245,6 +245,17 @@ void intel_batch_submit(ScrnInfoPtr scrn)
if (intel->batch_used == 0)
return;
+ if (intel->current_batch == I915_EXEC_BLT &&
+ INTEL_INFO(intel)->gen >= 060) {
+ OUT_BATCH(MI_FLUSH_DW);
+ OUT_BATCH(0);
+ OUT_BATCH(0);
+ OUT_BATCH(0);
+ OUT_BATCH(MI_LOAD_REGISTER_IMM);
+ OUT_BATCH(BCS_SWCTRL);
+ OUT_BATCH((BCS_SWCTRL_DST_Y | BCS_SWCTRL_SRC_Y) << 16);
+ }
+
/* Mark the end of the batchbuffer. */
OUT_BATCH(MI_BATCH_BUFFER_END);
/* Emit a padding dword if we aren't going to be quad-word aligned. */
diff --git a/src/uxa/intel_batchbuffer.h b/src/uxa/intel_batchbuffer.h
index e5fb8d0..e71ffd1 100644
--- a/src/uxa/intel_batchbuffer.h
+++ b/src/uxa/intel_batchbuffer.h
@@ -30,7 +30,7 @@ SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
#ifndef _INTEL_BATCHBUFFER_H
#define _INTEL_BATCHBUFFER_H
-#define BATCH_RESERVED 16
+#define BATCH_RESERVED 64
void intel_batch_init(ScrnInfoPtr scrn);
@@ -202,6 +202,23 @@ do { \
#define BEGIN_BATCH(n) __BEGIN_BATCH(n,RENDER_BATCH)
#define BEGIN_BATCH_BLT(n) __BEGIN_BATCH(n,BLT_BATCH)
+#define BEGIN_BATCH_BLT_TILED(n) \
+do { \
+ if (INTEL_INFO(intel)->gen < 060) { \
+ __BEGIN_BATCH(n, BLT_BATCH); \
+ } else { \
+ __BEGIN_BATCH(n+7, BLT_BATCH); \
+ OUT_BATCH(MI_FLUSH_DW); \
+ OUT_BATCH(0); \
+ OUT_BATCH(0); \
+ OUT_BATCH(0); \
+ OUT_BATCH(MI_LOAD_REGISTER_IMM); \
+ OUT_BATCH(BCS_SWCTRL); \
+ OUT_BATCH((BCS_SWCTRL_DST_Y | BCS_SWCTRL_SRC_Y) << 16 | \
+ ((intel->BR_tiling[0] == I915_TILING_Y) ? BCS_SWCTRL_DST_Y : 0) | \
+ ((intel->BR_tiling[1] == I915_TILING_Y) ? BCS_SWCTRL_SRC_Y : 0)); \
+ } \
+} while (0)
#define ADVANCE_BATCH() do { \
if (intel->batch_emitting == 0) \
diff --git a/src/uxa/intel_present.c b/src/uxa/intel_present.c
index a7f904c..ac028ed 100644
--- a/src/uxa/intel_present.c
+++ b/src/uxa/intel_present.c
@@ -244,6 +244,7 @@ intel_present_check_flip(RRCrtcPtr crtc,
ScrnInfoPtr scrn = xf86ScreenToScrn(screen);
intel_screen_private *intel = intel_get_screen_private(scrn);
dri_bo *bo;
+ uint32_t tiling, swizzle;
if (!scrn->vtSema)
return FALSE;
@@ -266,6 +267,12 @@ intel_present_check_flip(RRCrtcPtr crtc,
if (!bo)
return FALSE;
+ if (drm_intel_bo_get_tiling(bo, &tiling, &swizzle))
+ return FALSE;
+
+ if (tiling == I915_TILING_Y)
+ return FALSE;
+
return TRUE;
}
diff --git a/src/uxa/intel_uxa.c b/src/uxa/intel_uxa.c
index 830f094..ec32a72 100644
--- a/src/uxa/intel_uxa.c
+++ b/src/uxa/intel_uxa.c
@@ -176,6 +176,24 @@ intel_uxa_check_solid(DrawablePtr drawable, int alu, Pixel planemask)
return TRUE;
}
+static Bool
+intel_uxa_check_bo_tiling(intel_screen_private *intel,
+ PixmapPtr pixmap,
+ unsigned *tiling_out)
+{
+ struct intel_uxa_pixmap *priv;
+
+ priv = intel_uxa_get_pixmap_private(pixmap);
+ if (!priv)
+ return FALSE;
+
+ if (priv->tiling == I915_TILING_Y && INTEL_INFO(intel)->gen < 060)
+ return FALSE;
+
+ *tiling_out = priv->tiling;
+ return TRUE;
+}
+
/**
* Sets up hardware state for a series of solid fills.
*/
@@ -189,6 +207,9 @@ intel_uxa_prepare_solid(PixmapPtr pixmap, int alu, Pixel planemask, Pixel fg)
intel_uxa_get_pixmap_bo(pixmap),
};
+ if (!intel_uxa_check_bo_tiling(intel, pixmap, &intel->BR_tiling[0]))
+ return FALSE;
+
if (!intel_uxa_check_pitch_2d(pixmap))
return FALSE;
@@ -236,7 +257,7 @@ static void intel_uxa_solid(PixmapPtr pixmap, int x1, int y1, int x2, int y2)
{
int len = INTEL_INFO(intel)->gen >= 0100 ? 7 : 6;
- BEGIN_BATCH_BLT(len);
+ BEGIN_BATCH_BLT_TILED(len);
cmd = XY_COLOR_BLT_CMD | (len - 2);
@@ -310,6 +331,10 @@ intel_uxa_prepare_copy(PixmapPtr source, PixmapPtr dest, int xdir,
intel_uxa_get_pixmap_bo(dest),
};
+ if (!intel_uxa_check_bo_tiling(intel, dest, &intel->BR_tiling[0]) ||
+ !intel_uxa_check_bo_tiling(intel, source, &intel->BR_tiling[1]))
+ return FALSE;
+
if (!intel_uxa_get_aperture_space(scrn, bo_table, ARRAY_SIZE(bo_table)))
return FALSE;
@@ -375,7 +400,7 @@ intel_uxa_copy(PixmapPtr dest, int src_x1, int src_y1, int dst_x1,
{
int len = INTEL_INFO(intel)->gen >= 0100 ? 10 : 8;
- BEGIN_BATCH_BLT(len);
+ BEGIN_BATCH_BLT_TILED(len);
cmd = XY_SRC_COPY_BLT_CMD | (len - 2);
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