xf86-video-intel: 2 commits - src/i915_pciids.h src/sna/gen6_common.h src/sna/gen7_render.c src/sna/gen8_render.c
Chris Wilson
ickle at kemper.freedesktop.org
Fri Feb 27 09:25:27 PST 2015
src/i915_pciids.h | 32 ++++++++++++++++---------
src/sna/gen6_common.h | 64 +++++++++++++++++++++-----------------------------
src/sna/gen7_render.c | 12 ++++-----
src/sna/gen8_render.c | 10 ++++---
4 files changed, 61 insertions(+), 57 deletions(-)
New commits:
commit 9fb815462902a1d2047e135cf5037f47eb0d83d2
Author: Chris Wilson <chris at chris-wilson.co.uk>
Date: Fri Feb 27 13:56:03 2015 +0000
sna/gen7+: Allow GT3 to overlapping copies via an intermediate
This benefits most when GT3 is coupled with eLLC and WT, but it is just
marginally a win over a BLT otherwise.
Signed-off-by: Chris Wilson <chris at chris-wilson.co.uk>
diff --git a/src/sna/gen6_common.h b/src/sna/gen6_common.h
index 212215d..49e241f 100644
--- a/src/sna/gen6_common.h
+++ b/src/sna/gen6_common.h
@@ -30,8 +30,8 @@
#include "sna.h"
-#define NO_RING_SWITCH 0
-#define PREFER_RENDER 0
+#define NO_RING_SWITCH(sna) (!(sna)->kgem.has_semaphores)
+#define PREFER_RENDER 0 /* -1 -> BLT, 1 -> RENDER */
static inline bool is_uncached(struct sna *sna,
struct kgem_bo *bo)
@@ -46,10 +46,7 @@ inline static bool can_switch_to_blt(struct sna *sna,
if (sna->kgem.ring != KGEM_RENDER)
return true;
- if (NO_RING_SWITCH)
- return false;
-
- if (!sna->kgem.has_semaphores)
+ if (NO_RING_SWITCH(sna))
return false;
if (flags & COPY_LAST)
@@ -67,27 +64,6 @@ inline static bool can_switch_to_blt(struct sna *sna,
return kgem_ring_is_idle(&sna->kgem, KGEM_BLT);
}
-inline static bool can_switch_to_render(struct sna *sna,
- struct kgem_bo *bo)
-{
- if (sna->kgem.ring == KGEM_RENDER)
- return true;
-
- if (NO_RING_SWITCH)
- return false;
-
- if (!sna->kgem.has_semaphores)
- return false;
-
- if (bo && !RQ_IS_BLT(bo->rq) && !is_uncached(sna, bo))
- return true;
-
- if (sna->render_state.gt > 2)
- return true;
-
- return !kgem_ring_is_idle(&sna->kgem, KGEM_RENDER);
-}
-
static inline bool untiled_tlb_miss(struct kgem_bo *bo)
{
if (kgem_bo_is_render(bo))
@@ -100,22 +76,32 @@ static int prefer_blt_bo(struct sna *sna,
struct kgem_bo *src,
struct kgem_bo *dst)
{
+ assert(dst != NULL);
+
if (PREFER_RENDER)
return PREFER_RENDER < 0;
- if (dst && dst->rq)
+ if (dst->rq)
return RQ_IS_BLT(dst->rq);
if (sna->flags & SNA_POWERSAVE)
return true;
- if (src && sna->render_state.gt > 1)
- return false;
+ if (src) {
+ if (sna->render_state.gt > 1)
+ return false;
- if (src && src->rq)
- return RQ_IS_BLT(src->rq);
+ if (src->rq)
+ return RQ_IS_BLT(src->rq);
+ } else {
+ if (sna->render_state.gt > 2)
+ return false;
+ }
- return dst == NULL || dst->tiling == I915_TILING_NONE || is_uncached(sna, dst);
+ if (sna->render_state.gt < 2)
+ return true;
+
+ return dst->tiling == I915_TILING_NONE || is_uncached(sna, dst);
}
inline static bool force_blt_ring(struct sna *sna)
@@ -150,16 +136,22 @@ prefer_blt_ring(struct sna *sna, struct kgem_bo *bo, unsigned flags)
nonnull inline static bool
prefer_render_ring(struct sna *sna, struct kgem_bo *bo)
{
+ if (sna->kgem.ring == KGEM_RENDER)
+ return true;
+
+ if (sna->kgem.ring != KGEM_NONE && NO_RING_SWITCH(sna))
+ return false;
+
if (kgem_bo_is_render(bo))
return true;
if (sna->flags & SNA_POWERSAVE)
return false;
- if (sna->render_state.gt < 2)
- return false;
+ if (!prefer_blt_bo(sna, NULL, bo))
+ return true;
- return can_switch_to_render(sna, bo);
+ return !kgem_ring_is_idle(&sna->kgem, KGEM_RENDER);
}
inline static bool
diff --git a/src/sna/gen7_render.c b/src/sna/gen7_render.c
index ed5044d..87b0ca6 100644
--- a/src/sna/gen7_render.c
+++ b/src/sna/gen7_render.c
@@ -60,8 +60,6 @@
#define NO_FILL_ONE 0
#define NO_FILL_CLEAR 0
-#define NO_RING_SWITCH 0
-
#define USE_8_PIXEL_DISPATCH 1
#define USE_16_PIXEL_DISPATCH 1
#define USE_32_PIXEL_DISPATCH 0
@@ -2883,9 +2881,6 @@ prefer_blt_copy(struct sna *sna,
assert((flags & COPY_SYNC) == 0);
- if (src_bo == dst_bo && can_switch_to_blt(sna, dst_bo, flags))
- return true;
-
if (untiled_tlb_miss(src_bo) ||
untiled_tlb_miss(dst_bo))
return true;
@@ -2893,6 +2888,11 @@ prefer_blt_copy(struct sna *sna,
if (force_blt_ring(sna))
return true;
+ if (sna->render_state.gt < 3 &&
+ src_bo == dst_bo &&
+ can_switch_to_blt(sna, dst_bo, flags))
+ return true;
+
if (kgem_bo_is_render(dst_bo) ||
kgem_bo_is_render(src_bo))
return false;
@@ -2951,7 +2951,7 @@ fallback_blt:
&extents)) {
bool big = too_large(extents.x2-extents.x1, extents.y2-extents.y1);
- if ((big || can_switch_to_blt(sna, dst_bo, flags)) &&
+ if ((big || !prefer_render_ring(sna, dst_bo)) &&
sna_blt_copy_boxes(sna, alu,
src_bo, src_dx, src_dy,
dst_bo, dst_dx, dst_dy,
diff --git a/src/sna/gen8_render.c b/src/sna/gen8_render.c
index 5f26088..f6747ef 100644
--- a/src/sna/gen8_render.c
+++ b/src/sna/gen8_render.c
@@ -2704,9 +2704,6 @@ prefer_blt_copy(struct sna *sna,
assert((flags & COPY_SYNC) == 0);
- if (src_bo == dst_bo && can_switch_to_blt(sna, dst_bo, flags))
- return true;
-
if (untiled_tlb_miss(src_bo) ||
untiled_tlb_miss(dst_bo))
return true;
@@ -2714,6 +2711,11 @@ prefer_blt_copy(struct sna *sna,
if (force_blt_ring(sna))
return true;
+ if (sna->render_state.gt < 3 &&
+ src_bo == dst_bo &&
+ can_switch_to_blt(sna, dst_bo, flags))
+ return true;
+
if (kgem_bo_is_render(dst_bo) ||
kgem_bo_is_render(src_bo))
return false;
@@ -2774,7 +2776,7 @@ fallback_blt:
&extents)) {
bool big = too_large(extents.x2-extents.x1, extents.y2-extents.y1);
- if ((big || can_switch_to_blt(sna, dst_bo, flags)) &&
+ if ((big || !prefer_render_ring(sna, dst_bo)) &&
sna_blt_copy_boxes(sna, alu,
src_bo, src_dx, src_dy,
dst_bo, dst_dx, dst_dy,
commit 445423170d24a8a9f57ac887921cdecf4377f7ca
Author: Chris Wilson <chris at chris-wilson.co.uk>
Date: Fri Feb 27 10:15:04 2015 +0000
pciids: sync with kernel 0dc6f20b9
No new ids, just fixed descriptions.
Sync upto
kernel commit 0dc6f20b9803f09726bbb682649d35cda8ef5b5d
Author: Rodrigo Vivi <rodrigo.vivi at intel.com>
Date: Wed Jan 21 11:46:32 2015 -0800
drm/i915/bdw: PCI IDs ending in 0xb are ULT.
Signed-off-by: Chris Wilson <chris at chris-wilson.co.uk>
diff --git a/src/i915_pciids.h b/src/i915_pciids.h
index 180ad0e..f2e47fd 100644
--- a/src/i915_pciids.h
+++ b/src/i915_pciids.h
@@ -214,9 +214,9 @@
INTEL_VGA_DEVICE((((gt) - 1) << 4) | (id), info)
#define _INTEL_BDW_M_IDS(gt, info) \
- _INTEL_BDW_M(gt, 0x1602, info), /* ULT */ \
+ _INTEL_BDW_M(gt, 0x1602, info), /* Halo */ \
_INTEL_BDW_M(gt, 0x1606, info), /* ULT */ \
- _INTEL_BDW_M(gt, 0x160B, info), /* Iris */ \
+ _INTEL_BDW_M(gt, 0x160B, info), /* ULT */ \
_INTEL_BDW_M(gt, 0x160E, info) /* ULX */
#define _INTEL_BDW_D_IDS(gt, info) \
@@ -259,21 +259,31 @@
INTEL_VGA_DEVICE(0x22b2, info), \
INTEL_VGA_DEVICE(0x22b3, info)
-#define INTEL_SKL_IDS(info) \
- INTEL_VGA_DEVICE(0x1916, info), /* ULT GT2 */ \
+#define INTEL_SKL_GT1_IDS(info) \
INTEL_VGA_DEVICE(0x1906, info), /* ULT GT1 */ \
- INTEL_VGA_DEVICE(0x1926, info), /* ULT GT3 */ \
- INTEL_VGA_DEVICE(0x1921, info), /* ULT GT2F */ \
INTEL_VGA_DEVICE(0x190E, info), /* ULX GT1 */ \
+ INTEL_VGA_DEVICE(0x1902, info), /* DT GT1 */ \
+ INTEL_VGA_DEVICE(0x190B, info), /* Halo GT1 */ \
+ INTEL_VGA_DEVICE(0x190A, info) /* SRV GT1 */
+
+#define INTEL_SKL_GT2_IDS(info) \
+ INTEL_VGA_DEVICE(0x1916, info), /* ULT GT2 */ \
+ INTEL_VGA_DEVICE(0x1921, info), /* ULT GT2F */ \
INTEL_VGA_DEVICE(0x191E, info), /* ULX GT2 */ \
INTEL_VGA_DEVICE(0x1912, info), /* DT GT2 */ \
- INTEL_VGA_DEVICE(0x1902, info), /* DT GT1 */ \
INTEL_VGA_DEVICE(0x191B, info), /* Halo GT2 */ \
- INTEL_VGA_DEVICE(0x192B, info), /* Halo GT3 */ \
- INTEL_VGA_DEVICE(0x190B, info), /* Halo GT1 */ \
INTEL_VGA_DEVICE(0x191A, info), /* SRV GT2 */ \
- INTEL_VGA_DEVICE(0x192A, info), /* SRV GT3 */ \
- INTEL_VGA_DEVICE(0x190A, info), /* SRV GT1 */ \
INTEL_VGA_DEVICE(0x191D, info) /* WKS GT2 */
+#define INTEL_SKL_GT3_IDS(info) \
+ INTEL_VGA_DEVICE(0x1926, info), /* ULT GT3 */ \
+ INTEL_VGA_DEVICE(0x192B, info), /* Halo GT3 */ \
+ INTEL_VGA_DEVICE(0x192A, info) /* SRV GT3 */ \
+
+#define INTEL_SKL_IDS(info) \
+ INTEL_SKL_GT1_IDS(info), \
+ INTEL_SKL_GT2_IDS(info), \
+ INTEL_SKL_GT3_IDS(info)
+
+
#endif /* _I915_PCIIDS_H */
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