xf86-video-intel: 3 commits - src/intel_module.c src/render_program/exa_wm_yuv_rgb.g8a src/render_program/exa_wm_yuv_rgb.g8b src/sna/gen8_render.c src/sna/sna_render.h
Chris Wilson
ickle at kemper.freedesktop.org
Thu Apr 16 13:06:35 PDT 2015
src/intel_module.c | 6 +++++
src/render_program/exa_wm_yuv_rgb.g8a | 4 +--
src/render_program/exa_wm_yuv_rgb.g8b | 2 -
src/sna/gen8_render.c | 38 ++++++++++++++++++++++++++++++++--
src/sna/sna_render.h | 2 -
5 files changed, 46 insertions(+), 6 deletions(-)
New commits:
commit 3abc3ce3b52a4bd4de4e7e21f05e60c1bd576b6a
Author: Chris Wilson <chris at chris-wilson.co.uk>
Date: Thu Apr 16 20:59:16 2015 +0100
sna/gen8: reduce CHV VS URB entries to 640
According to BSpec the max number of VS URB entries for CHV is 640.
Based on a patch by Ville Syrjälä.
v2: Start using a GT info block like earlier generations.
Signed-off-by: Ville Syrjälä <ville.syrjala at linux.intel.com> [v1]
Signed-off-by: Chris Wilson <chris at chris-wilson.co.uk>
diff --git a/src/sna/gen8_render.c b/src/sna/gen8_render.c
index ebabb2e..c0fe9f9 100644
--- a/src/sna/gen8_render.c
+++ b/src/sna/gen8_render.c
@@ -205,6 +205,33 @@ static const struct blendinfo {
#define OUT_VERTEX(x,y) vertex_emit_2s(sna, x,y)
#define OUT_VERTEX_F(v) vertex_emit(sna, v)
+struct gt_info {
+ const char *name;
+ struct {
+ int max_vs_entries;
+ } urb;
+};
+
+static const struct gt_info bdw_gt_info = {
+ .name = "Broadwell (gen8)",
+ .urb = { .max_vs_entries = 960 },
+};
+
+static bool is_bdw(struct sna *sna)
+{
+ return sna->kgem.gen == 0100;
+}
+
+static const struct gt_info chv_gt_info = {
+ .name = "Cherryview (gen8)",
+ .urb = { .max_vs_entries = 640 },
+};
+
+static bool is_chv(struct sna *sna)
+{
+ return sna->kgem.gen == 0101;
+}
+
static inline bool too_large(int width, int height)
{
return width > GEN8_MAX_SIZE || height > GEN8_MAX_SIZE;
@@ -462,7 +489,7 @@ gen8_emit_urb(struct sna *sna)
{
/* num of VS entries must be divisible by 8 if size < 9 */
OUT_BATCH(GEN8_3DSTATE_URB_VS | (2 - 2));
- OUT_BATCH(960 << URB_ENTRY_NUMBER_SHIFT |
+ OUT_BATCH(sna->render_state.gen8.info->urb.max_vs_entries << URB_ENTRY_NUMBER_SHIFT |
(2 - 1) << URB_ENTRY_SIZE_SHIFT |
4 << URB_STARTING_ADDRESS_SHIFT);
@@ -3915,6 +3942,13 @@ static bool gen8_render_setup(struct sna *sna)
state->gt = ((devid >> 4) & 0xf) + 1;
DBG(("%s: gt=%d\n", __FUNCTION__, state->gt));
+ if (is_bdw(sna))
+ state->info = &bdw_gt_info;
+ else if (is_chv(sna))
+ state->info = &chv_gt_info;
+ else
+ return false;
+
sna_static_stream_init(&general);
/* Zero pad the start. If you see an offset of 0x0 in the batchbuffer
@@ -4026,5 +4060,5 @@ const char *gen8_render_init(struct sna *sna, const char *backend)
sna->render.max_3d_size = GEN8_MAX_SIZE;
sna->render.max_3d_pitch = 1 << 18;
- return "Broadwell";
+ return sna->render_state.gen8.info->name;
}
diff --git a/src/sna/sna_render.h b/src/sna/sna_render.h
index f59a928..723de80 100644
--- a/src/sna/sna_render.h
+++ b/src/sna/sna_render.h
@@ -540,7 +540,7 @@ enum {
struct gen8_render_state {
unsigned gt;
-
+ const struct gt_info *info;
struct kgem_bo *general_bo;
uint32_t vs_state;
commit 1e1a7875cf6ff7a46e373ddb5c76621df72b8f74
Author: Ville Syrjälä <ville.syrjala at linux.intel.com>
Date: Thu Apr 16 20:40:37 2015 +0300
intel: Add marketing names for CHV
All CHV devices will be branded as "Intel(r) HD Graphics".
Signed-off-by: Ville Syrjälä <ville.syrjala at linux.intel.com>
diff --git a/src/intel_module.c b/src/intel_module.c
index bb74422..faf70ab 100644
--- a/src/intel_module.c
+++ b/src/intel_module.c
@@ -259,6 +259,12 @@ static const SymTabRec intel_chipsets[] = {
{0x163D, "HD graphics"},
{0x163E, "HD graphics"},
+ /* Cherryview (Cherrytrail/Braswell) */
+ {0x22b0, "HD Graphics"},
+ {0x22b1, "HD Graphics"},
+ {0x22b2, "HD Graphics"},
+ {0x22b3, "HD Graphics"},
+
/* When adding new identifiers, also update:
* 1. intel_identify()
* 2. man/intel.man
commit c43617b739e358064396912c7a7a8028ca91d201
Author: Ville Syrjälä <ville.syrjala at linux.intel.com>
Date: Thu Apr 16 20:40:39 2015 +0300
gen8: Fix the YUV->RGB shader
Use the correct register (Yn_01) with first half of the
Y samples instead of using the register (Yn_23) with the
second half twice when computing the green channel.
Also use the Yn_01 register name instead of Yn for the red
channel as well, just for a bit of extra consistency.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=89807
Signed-off-by: Ville Syrjälä <ville.syrjala at linux.intel.com>
Tested-by: Chris Wilson <chris at chris-wilson.co.uk>
diff --git a/src/render_program/exa_wm_yuv_rgb.g8a b/src/render_program/exa_wm_yuv_rgb.g8a
index 7def093..34973ba 100644
--- a/src/render_program/exa_wm_yuv_rgb.g8a
+++ b/src/render_program/exa_wm_yuv_rgb.g8a
@@ -76,7 +76,7 @@ add (16) Cbn<1>F Cb<8,8,1>F -0.501961F { compr align1 };
/*
* R = Y + Cr * 1.596
*/
-mov (8) acc0<1>F Yn<8,8,1>F { compr align1 };
+mov (8) acc0<1>F Yn_01<8,8,1>F { compr align1 };
mac.sat(8) src_sample_r_01<1>F Crn_01<8,8,1>F 1.596F { compr align1 };
mov (8) acc0<1>F Yn_23<8,8,1>F { compr align1 };
@@ -84,7 +84,7 @@ mac.sat(8) src_sample_r_23<1>F Crn_23<8,8,1>F 1.596F { compr align1 };
/*
* G = Crn * -0.813 + Cbn * -0.392 + Y
*/
-mov (8) acc0<1>F Yn_23<8,8,1>F { compr align1 };
+mov (8) acc0<1>F Yn_01<8,8,1>F { compr align1 };
mac (8) acc0<1>F Crn_01<8,8,1>F -0.813F { compr align1 };
mac.sat(8) src_sample_g_01<1>F Cbn_01<8,8,1>F -0.392F { compr align1 };
diff --git a/src/render_program/exa_wm_yuv_rgb.g8b b/src/render_program/exa_wm_yuv_rgb.g8b
index 4494953..2cd6fc4 100644
--- a/src/render_program/exa_wm_yuv_rgb.g8b
+++ b/src/render_program/exa_wm_yuv_rgb.g8b
@@ -6,7 +6,7 @@
{ 0x80600048, 0x21c03ae8, 0x3e8d02c0, 0x3fcc49ba },
{ 0x00600001, 0x24003ae0, 0x008d0320, 0x00000000 },
{ 0x80600048, 0x21e03ae8, 0x3e8d02e0, 0x3fcc49ba },
- { 0x00600001, 0x24003ae0, 0x008d0320, 0x00000000 },
+ { 0x00600001, 0x24003ae0, 0x008d0300, 0x00000000 },
{ 0x00600048, 0x24003ae0, 0x3e8d02c0, 0xbf5020c5 },
{ 0x80600048, 0x22003ae8, 0x3e8d0340, 0xbec8b439 },
{ 0x00600001, 0x24003ae0, 0x008d0320, 0x00000000 },
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