xf86-video-intel: 5 commits - configure.ac src/sna/kgem.c src/sna/kgem.h src/sna/sna_accel.c src/sna/sna_dri2.c
Chris Wilson
ickle at kemper.freedesktop.org
Wed Nov 19 05:44:01 PST 2014
configure.ac | 6 +++---
src/sna/kgem.c | 4 +++-
src/sna/kgem.h | 13 +++++++++++++
src/sna/sna_accel.c | 41 +++++++++++++++++++++++++++++++++++++++--
src/sna/sna_dri2.c | 10 +---------
5 files changed, 59 insertions(+), 15 deletions(-)
New commits:
commit a90cc3b3889fafbd91c11c42d068a9d6474e218b
Author: Chris Wilson <chris at chris-wilson.co.uk>
Date: Tue Nov 18 08:37:25 2014 +0000
sna: Tweak alignment constraints on gen8 to allow BLT
The previous commits prevent us from using the BLT if the destination
address is misaligned. Honour that restriction when creating buffers as
well, so that they are always usuable by the BLT.
Signed-off-by: Chris Wilson <chris at chris-wilson.co.uk>
diff --git a/src/sna/kgem.c b/src/sna/kgem.c
index fe225d2..72ffb04 100644
--- a/src/sna/kgem.c
+++ b/src/sna/kgem.c
@@ -1797,6 +1797,8 @@ inline static uint32_t kgem_pitch_alignment(struct kgem *kgem, unsigned flags)
return 256;
if (flags & CREATE_SCANOUT)
return 64;
+ if (kgem->gen >= 0100)
+ return 32;
return 8;
}
@@ -7234,7 +7236,7 @@ struct kgem_bo *kgem_create_buffer_2d(struct kgem *kgem,
assert(width > 0 && height > 0);
assert(ret != NULL);
stride = ALIGN(width, 2) * bpp >> 3;
- stride = ALIGN(stride, 4);
+ stride = ALIGN(stride, kgem->gen >= 0100 ? 32 : 4);
DBG(("%s: %dx%d, %d bpp, stride=%d\n",
__FUNCTION__, width, height, bpp, stride));
commit 8dee52997891108eec8e4df12dd02f3a060d9cb8
Author: Chris Wilson <chris at chris-wilson.co.uk>
Date: Wed Nov 19 13:38:20 2014 +0000
sna: Add more checks and asserts for BLT capable bo
Before we use the BLT for core acceleration, double check that we can.
This should catch the case where we attempt to operate on SHM pixmaps
which do not meet the restrictions.
Signed-off-by: Chris Wilson <chris at chris-wilson.co.uk>
diff --git a/src/sna/sna_accel.c b/src/sna/sna_accel.c
index 13f52e4..a5784af 100644
--- a/src/sna/sna_accel.c
+++ b/src/sna/sna_accel.c
@@ -5198,6 +5198,9 @@ sna_put_xybitmap_blt(DrawablePtr drawable, GCPtr gc, RegionPtr region,
}
}
+ if (!kgem_bo_can_blt(&sna->kgem, bo))
+ return false;
+
assert_pixmap_contains_box(pixmap, RegionExtents(region));
if (damage)
sna_damage_add_to_pixmap(damage, region, pixmap);
@@ -5210,6 +5213,7 @@ sna_put_xybitmap_blt(DrawablePtr drawable, GCPtr gc, RegionPtr region,
y += dy + drawable->y;
kgem_set_mode(&sna->kgem, KGEM_BLT, bo);
+ assert(kgem_bo_can_blt(&sna->kgem, bo));
/* Region is pre-clipped and translated into pixmap space */
box = region_rects(region);
@@ -5358,6 +5362,9 @@ sna_put_xypixmap_blt(DrawablePtr drawable, GCPtr gc, RegionPtr region,
}
}
+ if (!kgem_bo_can_blt(&sna->kgem, bo))
+ return false;
+
assert_pixmap_contains_box(pixmap, RegionExtents(region));
if (damage)
sna_damage_add_to_pixmap(damage, region, pixmap);
@@ -5370,6 +5377,7 @@ sna_put_xypixmap_blt(DrawablePtr drawable, GCPtr gc, RegionPtr region,
y += dy + drawable->y;
kgem_set_mode(&sna->kgem, KGEM_BLT, bo);
+ assert(kgem_bo_can_blt(&sna->kgem, bo));
skip = h * BitmapBytePad(w + left);
for (i = 1 << (gc->depth-1); i; i >>= 1, bits += skip) {
@@ -8214,6 +8222,7 @@ sna_copy_bitmap_blt(DrawablePtr _bitmap, DrawablePtr drawable, GCPtr gc,
br13 |= copy_ROP[gc->alu] << 16;
kgem_set_mode(&sna->kgem, KGEM_BLT, arg->bo);
+ assert(kgem_bo_can_blt(&sna->kgem, arg->bo));
do {
int bx1 = (box->x1 + sx) & ~7;
int bx2 = (box->x2 + sx + 7) & ~7;
@@ -8436,6 +8445,7 @@ sna_copy_plane_blt(DrawablePtr source, DrawablePtr drawable, GCPtr gc,
br13 |= copy_ROP[gc->alu] << 16;
kgem_set_mode(&sna->kgem, KGEM_BLT, arg->bo);
+ assert(kgem_bo_can_blt(&sna->kgem, arg->bo));
do {
int bx1 = (box->x1 + sx) & ~7;
int bx2 = (box->x2 + sx + 7) & ~7;
@@ -8722,6 +8732,10 @@ sna_copy_plane(DrawablePtr src, DrawablePtr dst, GCPtr gc,
goto fallback;
}
}
+
+ if (!kgem_bo_can_blt(&sna->kgem, arg.bo))
+ return false;
+
RegionUninit(®ion);
return sna_do_copy(src, dst, gc,
src_x, src_y,
@@ -12159,9 +12173,14 @@ sna_poly_fill_rect_tiled_8x8_blt(DrawablePtr drawable,
if (tile_bo->tiling)
return false;
+ if (!kgem_bo_can_blt(&sna->kgem, bo) ||
+ !kgem_bo_can_blt(&sna->kgem, tile_bo))
+ return false;
+
assert(tile_bo->pitch == 8 * drawable->bitsPerPixel >> 3);
kgem_set_mode(&sna->kgem, KGEM_BLT, bo);
+ assert(kgem_bo_can_blt(&sna->kgem, bo));
if (!kgem_check_batch(&sna->kgem, 10+2*3) ||
!kgem_check_reloc(&sna->kgem, 2) ||
!kgem_check_many_bo_fenced(&sna->kgem, bo, tile_bo, NULL)) {
@@ -13097,6 +13116,7 @@ sna_poly_fill_rect_stippled_8x8_blt(DrawablePtr drawable,
}
kgem_set_mode(&sna->kgem, KGEM_BLT, bo);
+ assert(kgem_bo_can_blt(&sna->kgem, bo));
if (!kgem_check_batch(&sna->kgem, 10 + 2*3) ||
!kgem_check_bo_fenced(&sna->kgem, bo) ||
!kgem_check_reloc(&sna->kgem, 1)) {
@@ -13475,6 +13495,7 @@ sna_poly_fill_rect_stippled_1_blt(DrawablePtr drawable,
get_drawable_deltas(drawable, pixmap, &dx, &dy);
kgem_set_mode(&sna->kgem, KGEM_BLT, bo);
+ assert(kgem_bo_can_blt(&sna->kgem, bo));
br00 = 3 << 20;
br13 = bo->pitch;
@@ -14389,6 +14410,7 @@ sna_poly_fill_rect_stippled_n_blt__imm(DrawablePtr drawable,
get_drawable_deltas(drawable, pixmap, &dx, &dy);
kgem_set_mode(&sna->kgem, KGEM_BLT, bo);
+ assert(kgem_bo_can_blt(&sna->kgem, bo));
br00 = XY_MONO_SRC_COPY_IMM | 3 << 20;
br13 = bo->pitch;
@@ -14533,6 +14555,7 @@ sna_poly_fill_rect_stippled_n_blt(DrawablePtr drawable,
get_drawable_deltas(drawable, pixmap, &dx, &dy);
kgem_set_mode(&sna->kgem, KGEM_BLT, bo);
+ assert(kgem_bo_can_blt(&sna->kgem, bo));
br00 = XY_MONO_SRC_COPY | 3 << 20;
br13 = bo->pitch;
@@ -14660,10 +14683,9 @@ sna_poly_fill_rect_stippled_blt(DrawablePtr drawable,
{
PixmapPtr stipple = gc->stipple;
+ PixmapPtr pixmap = get_drawable_pixmap(drawable);
if (bo->tiling == I915_TILING_Y) {
- PixmapPtr pixmap = get_drawable_pixmap(drawable);
-
DBG(("%s: converting bo from Y-tiling\n", __FUNCTION__));
/* This is cheating, but only the gpu_bo can be tiled */
assert(bo == __sna_pixmap_get_bo(pixmap));
@@ -14675,6 +14697,9 @@ sna_poly_fill_rect_stippled_blt(DrawablePtr drawable,
}
}
+ if (!kgem_bo_can_blt(&to_sna_from_pixmap(pixmap)->kgem, bo))
+ return false;
+
if (!sna_drawable_move_to_cpu(&stipple->drawable, MOVE_READ))
return false;
@@ -15221,6 +15246,9 @@ sna_glyph_blt(DrawablePtr drawable, GCPtr gc,
}
}
+ if (!kgem_bo_can_blt(&sna->kgem, bo))
+ return false;
+
if (get_drawable_deltas(drawable, pixmap, &dx, &dy))
RegionTranslate(clip, dx, dy);
_x += drawable->x + dx;
@@ -15239,6 +15267,7 @@ sna_glyph_blt(DrawablePtr drawable, GCPtr gc,
}
kgem_set_mode(&sna->kgem, KGEM_BLT, bo);
+ assert(kgem_bo_can_blt(&sna->kgem, bo));
if (!kgem_check_batch(&sna->kgem, 20) ||
!kgem_check_bo_fenced(&sna->kgem, bo) ||
!kgem_check_reloc(&sna->kgem, 1)) {
@@ -15938,6 +15967,9 @@ sna_reversed_glyph_blt(DrawablePtr drawable, GCPtr gc,
}
}
+ if (!kgem_bo_can_blt(&sna->kgem, bo))
+ return false;
+
if (get_drawable_deltas(drawable, pixmap, &dx, &dy))
RegionTranslate(clip, dx, dy);
_x += drawable->x + dx;
@@ -15956,6 +15988,7 @@ sna_reversed_glyph_blt(DrawablePtr drawable, GCPtr gc,
}
kgem_set_mode(&sna->kgem, KGEM_BLT, bo);
+ assert(kgem_bo_can_blt(&sna->kgem, bo));
if (!kgem_check_batch(&sna->kgem, 20) ||
!kgem_check_bo_fenced(&sna->kgem, bo) ||
!kgem_check_reloc(&sna->kgem, 1)) {
@@ -16397,6 +16430,9 @@ sna_push_pixels_solid_blt(GCPtr gc,
}
}
+ if (!kgem_bo_can_blt(&sna->kgem, bo))
+ return false;
+
if (get_drawable_deltas(drawable, pixmap, &dx, &dy))
RegionTranslate(region, dx, dy);
@@ -16410,6 +16446,7 @@ sna_push_pixels_solid_blt(GCPtr gc,
region->extents.x2, region->extents.y2));
kgem_set_mode(&sna->kgem, KGEM_BLT, bo);
+ assert(kgem_bo_can_blt(&sna->kgem, bo));
/* Region is pre-clipped and translated into pixmap space */
box = region_rects(region);
commit 3a22b6f6d55a5b1e0a1c0a3d597996268ed439ad
Author: Mika Kuoppala <mika.kuoppala at linux.intel.com>
Date: Wed Nov 19 15:10:05 2014 +0200
sna: gen8 BLT broken when address has bit 4 set
With bit 4 set in address, the gen8 blitter fails and blits errorneously
into the cacheline preceeding the destination and similarly when reading from
the source, corrupting memory.
v2: Update the destination base offset pattern as revealed
by igt/tests/gem_userptr_blits/destination-bo-align
v3: Check base address as well
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=79053
Cc: Chris Wilson <chris at chris-wilson.co.uk>
Tested-by: xunx.fang at intel.com [v2]
Signed-off-by: Mika Kuoppala <mika.kuoppala at intel.com>
diff --git a/src/sna/kgem.h b/src/sna/kgem.h
index 6adae3b..3275b4f 100644
--- a/src/sna/kgem.h
+++ b/src/sna/kgem.h
@@ -551,6 +551,13 @@ static inline bool kgem_bo_blt_pitch_is_ok(struct kgem *kgem,
struct kgem_bo *bo)
{
int pitch = bo->pitch;
+
+ if (kgem->gen >= 0100 && pitch & (1 << 4)) { /* bdw is broken */
+ DBG(("%s: can not blt to handle=%d, pitch=%d\n",
+ __FUNCTION__, bo->handle, pitch));
+ return false;
+ }
+
if (kgem->gen >= 040 && bo->tiling)
pitch /= 4;
if (pitch > MAXSHORT) {
@@ -573,6 +580,12 @@ static inline bool kgem_bo_can_blt(struct kgem *kgem,
return false;
}
+ if (kgem->gen >= 0100 && bo->proxy && bo->delta & (1 << 4)) {
+ DBG(("%s: can not blt to handle=%d, delta=%d\n",
+ __FUNCTION__, bo->handle, bo->delta));
+ return false;
+ }
+
return kgem_bo_blt_pitch_is_ok(kgem, bo);
}
commit 29aab766f4b59c71181875880c8c943b93008bdf
Author: Chris Wilson <chris at chris-wilson.co.uk>
Date: Tue Nov 18 20:54:39 2014 +0000
sna/dri2: Remove unused function
Signed-off-by: Chris Wilson <chris at chris-wilson.co.uk>
diff --git a/src/sna/sna_dri2.c b/src/sna/sna_dri2.c
index c8c71c5..f3395ce 100644
--- a/src/sna/sna_dri2.c
+++ b/src/sna/sna_dri2.c
@@ -64,15 +64,7 @@ USE OR OTHER DEALINGS IN THE SOFTWARE.
static inline struct kgem_bo *ref(struct kgem_bo *bo)
{
- assert(bo->refcnt);
- bo->refcnt++;
- return bo;
-}
-
-static inline void unref(struct kgem_bo *bo)
-{
- assert(bo->refcnt > 1);
- bo->refcnt--;
+ return kgem_bo_reference(bo);
}
struct sna_dri2_private {
commit b6eeb7a1f7efa591504070b606be655e27e6e9c2
Author: Chris Wilson <chris at chris-wilson.co.uk>
Date: Wed Nov 5 13:03:41 2014 +0000
Disable DRI3 by default
The external libraries, both in git, and especially shipping already
enabled in distributions, are buggy and lead to server crashes and
lockups. Caveat emptor.
Signed-off-by: Chris Wilson <chris at chris-wilson.co.uk>
diff --git a/configure.ac b/configure.ac
index 328b4e9..cbfc472 100644
--- a/configure.ac
+++ b/configure.ac
@@ -339,10 +339,10 @@ AC_ARG_ENABLE(dri2,
[DRI2=$enableval],
[DRI2=yes])
AC_ARG_ENABLE(dri3,
- AS_HELP_STRING([--disable-dri3],
- [Disable DRI3 support [[default=yes]]]),
+ AS_HELP_STRING([--enable-dri3],
+ [Enable DRI3 support [[default=no]]]),
[DRI3=$enableval],
- [DRI3=yes])
+ [DRI3=no])
AC_ARG_ENABLE(xvmc, AS_HELP_STRING([--disable-xvmc],
[Disable XvMC support [[default=yes]]]),
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