xf86-video-intel: 5 commits - configure.ac src/sna/sna_accel.c src/uxa/i830_reg.h src/uxa/intel_batchbuffer.c src/uxa/intel_batchbuffer.h src/uxa/intel_driver.c src/uxa/intel_uxa.c src/uxa/intel_video.c tools/virtual.c
Chris Wilson
ickle at kemper.freedesktop.org
Fri Mar 14 04:41:50 PDT 2014
configure.ac | 7 ++--
src/sna/sna_accel.c | 9 ++++-
src/uxa/i830_reg.h | 12 +++----
src/uxa/intel_batchbuffer.c | 1
src/uxa/intel_batchbuffer.h | 8 ++++
src/uxa/intel_driver.c | 7 +---
src/uxa/intel_uxa.c | 24 +++++++-------
src/uxa/intel_video.c | 3 +
tools/virtual.c | 74 +++++++++++++++++++++++++++++++-------------
9 files changed, 96 insertions(+), 49 deletions(-)
New commits:
commit b61e6398f0cf94d3c483e30c05ceae4a8383d16c
Author: Chris Wilson <chris at chris-wilson.co.uk>
Date: Fri Mar 14 11:32:38 2014 +0000
sna: Ensure we flush SHM pixmaps if rendering to a GPU shadow
Normally, we try to render into the CPU bo of a SHM pixmap. However, under
the right circumstances we may try to do a series of rendering into the
GPU bo and then copy it back to the CPU bo. In that case, we need to be
sure to mark the pixmap as requiring the flush.
Signed-off-by: Chris Wilson <chris at chris-wilson.co.uk>
diff --git a/src/sna/sna_accel.c b/src/sna/sna_accel.c
index 716a9fe..4f08e99 100644
--- a/src/sna/sna_accel.c
+++ b/src/sna/sna_accel.c
@@ -3438,7 +3438,7 @@ sna_drawable_use_bo(DrawablePtr drawable, unsigned flags, const BoxRec *box,
flags &= ~PREFER_GPU;
if ((flags & (PREFER_GPU | IGNORE_CPU)) == IGNORE_CPU) {
- if (box_inplace(pixmap, box))
+ if (priv->gpu_bo && box_inplace(pixmap, box))
flags |= PREFER_GPU;
}
@@ -3618,6 +3618,7 @@ move_to_gpu:
}
done:
+ assert(priv->move_to_gpu == NULL);
assert(priv->gpu_bo != NULL);
assert(priv->gpu_bo->refcnt);
if (sna_damage_is_all(&priv->gpu_damage,
@@ -3635,6 +3636,7 @@ done:
assert(priv->gpu_bo->proxy == NULL);
assert(priv->clear == false);
assert(priv->cpu == false);
+ assert(!priv->shm);
return priv->gpu_bo;
use_gpu_bo:
@@ -3654,6 +3656,11 @@ use_gpu_bo:
}
}
+ if (priv->shm) {
+ assert(!priv->flush);
+ list_move(&priv->flush_list, &sna->flush_pixmaps);
+ }
+
DBG(("%s: using whole GPU bo\n", __FUNCTION__));
assert(priv->gpu_bo != NULL);
assert(priv->gpu_bo->refcnt);
commit f47f192f2240d19ede0a3a59b7970e4f563f3195
Author: Chris Wilson <chris at chris-wilson.co.uk>
Date: Fri Mar 14 09:17:36 2014 +0000
intel-virtual-output: Include extra debug information for modesets
Signed-off-by: Chris Wilson <chris at chris-wilson.co.uk>
diff --git a/tools/virtual.c b/tools/virtual.c
index 1783c66..0dfd308 100644
--- a/tools/virtual.c
+++ b/tools/virtual.c
@@ -67,8 +67,10 @@
#if 0
#define DBG(x) printf x
+#define EXTRA_DBG 1
#else
#define DBG(x)
+#define EXTRA_DBG 0
#endif
#define FORCE_FULL_REDRAW 0
@@ -1254,9 +1256,32 @@ err:
ret = XRRSetPanning(dst->dpy, res, rr_crtc, memset(&panning, 0, sizeof(panning)));
DBG(("%s-%s: XRRSetPanning %s\n", DisplayString(dst->dpy), dst->name, ret ? "failed" : "success"));
+ (void)ret;
+
+ if (EXTRA_DBG) {
+ XRRCrtcInfo *c;
+ XRRPanning *p;
+
+ c = XRRGetCrtcInfo(dst->dpy, res, rr_crtc);
+ if (c) {
+ DBG(("%s-%s: x=%d, y=%d, rotation=%d, mode=%ld\n",
+ DisplayString(dst->dpy), dst->name,
+ c->x, c->y, c->rotation, c->mode));
+ XRRFreeCrtcInfo(c);
+ }
+
+ p = XRRGetPanning(dst->dpy, res, rr_crtc);
+ if (p) {
+ DBG(("%s-%s: panning (%d, %d)x(%d, %d), tracking (%d, %d)x(%d, %d), border (%d, %d),(%d, %d)\n",
+ DisplayString(dst->dpy), dst->name,
+ p->left, p->top, p->width, p->height,
+ p->track_left, p->track_top, p->track_width, p->track_height,
+ p->border_left, p->border_top, p->border_right, p->border_bottom));
+ XRRFreePanning(p);
+ }
+ }
dst->rr_crtc = rr_crtc;
- (void)ret;
}
free_res:
XRRFreeScreenResources(res);
commit 0ad54325e94c4fd144c9fbcba25c3d167b6c5e18
Author: Chris Wilson <chris at chris-wilson.co.uk>
Date: Fri Mar 14 07:42:32 2014 +0000
intel-virtual-output: Disable remote CRTCs at startup
Signed-off-by: Chris Wilson <chris at chris-wilson.co.uk>
diff --git a/tools/virtual.c b/tools/virtual.c
index 8b8d511..1783c66 100644
--- a/tools/virtual.c
+++ b/tools/virtual.c
@@ -444,6 +444,17 @@ static void clone_update_edid(struct clone *clone)
}
}
+static void disable_crtc(Display *dpy, XRRScreenResources *res, RRCrtc crtc)
+{
+ XRRPanning panning;
+
+ if (crtc == 0)
+ return;
+
+ XRRSetPanning(dpy, res, crtc, memset(&panning, 0, sizeof(panning)));
+ XRRSetCrtcConfig(dpy, res, crtc, CurrentTime, 0, 0, None, RR_Rotate_0, NULL, 0);
+}
+
static int clone_update_modes__randr(struct clone *clone)
{
XRRScreenResources *from_res = NULL, *to_res = NULL;
@@ -510,14 +521,20 @@ static int clone_update_modes__randr(struct clone *clone)
}
}
- clone->dst.rr_crtc = from_info->crtc;
+ /* Disable the remote output */
+ if (from_info->crtc != clone->dst.rr_crtc) {
+ DBG(("%s(%s-%s): disabling active CRTC\n", __func__,
+ DisplayString(clone->dst.dpy), clone->dst.name));
+ disable_crtc(clone->dst.dpy, from_res, from_info->crtc);
+ clone->dst.rr_crtc = 0;
+ clone->dst.mode.id = 0;
+ }
/* Clear all current UserModes on the output, including any active ones */
if (to_info->crtc) {
DBG(("%s(%s-%s): disabling active CRTC\n", __func__,
DisplayString(clone->src.dpy), clone->src.name));
- XRRSetCrtcConfig(clone->src.dpy, to_res, to_info->crtc, CurrentTime,
- 0, 0, None, RR_Rotate_0, NULL, 0);
+ disable_crtc(clone->src.dpy, to_res, to_info->crtc);
}
for (i = 0; i < to_info->nmode; i++) {
DBG(("%s(%s-%s): deleting mode %ld\n", __func__,
@@ -617,8 +634,7 @@ static int clone_update_modes__fixed(struct clone *clone)
if (info->crtc) {
DBG(("%s(%s-%s): disabling active CRTC\n", __func__,
DisplayString(clone->src.dpy), clone->src.name));
- XRRSetCrtcConfig(clone->src.dpy, res, info->crtc, CurrentTime,
- 0, 0, None, RR_Rotate_0, NULL, 0);
+ disable_crtc(clone->src.dpy, res, info->crtc);
}
for (i = 0; i < info->nmode; i++) {
DBG(("%s(%s-%s): deleting mode %ld\n", __func__,
@@ -717,9 +733,7 @@ static RROutput claim_virtual(struct display *display, char *output_name, int nc
/* Some else may have interrupted us and installed that new mode! */
output = XRRGetOutputInfo(dpy, res, rr_output);
if (output) {
- if (output->crtc)
- XRRSetCrtcConfig(dpy, res, output->crtc, CurrentTime,
- 0, 0, None, RR_Rotate_0, NULL, 0);
+ disable_crtc(dpy, res, output->crtc);
XRRFreeOutputInfo(output);
}
XRRFreeScreenResources(res);
@@ -1091,8 +1105,7 @@ static int context_update(struct context *ctx)
DBG(("%s: disabling output '%s'\n",
DisplayString(dst->dpy), dst->name));
- XRRSetCrtcConfig(dst->dpy, res, dst->rr_crtc, CurrentTime,
- 0, 0, None, RR_Rotate_0, NULL, 0);
+ disable_crtc(dpy, res, dst->rr_crtc);
dst->rr_crtc = 0;
dst->mode.id = 0;
}
@@ -1116,8 +1129,7 @@ static int context_update(struct context *ctx)
DBG(("%s: disabling output '%s'\n",
DisplayString(dst->dpy), dst->name));
- XRRSetCrtcConfig(dst->dpy, res, dst->rr_crtc, CurrentTime,
- 0, 0, None, RR_Rotate_0, NULL, 0);
+ disable_crtc(dpy, res, dst->rr_crtc);
dst->rr_crtc = 0;
dst->mode.id = 0;
}
@@ -1147,8 +1159,7 @@ err:
if (dst->rr_crtc) {
DBG(("%s: disabling unused output '%s'\n",
DisplayString(dst->dpy), dst->name));
- XRRSetCrtcConfig(dst->dpy, res, dst->rr_crtc, CurrentTime,
- 0, 0, None, RR_Rotate_0, NULL, 0);
+ disable_crtc(dpy, res, dst->rr_crtc);
dst->rr_crtc = 0;
dst->mode.id = 0;
}
@@ -2189,8 +2200,7 @@ static int last_display_add_clones__randr(struct context *ctx)
if (o->crtc) {
DBG(("%s - disabling active output\n", DisplayString(display->dpy)));
- XRRSetCrtcConfig(display->dpy, res, o->crtc, CurrentTime,
- 0, 0, None, RR_Rotate_0, NULL, 0);
+ disable_crtc(display->dpy, res, o->crtc);
}
XRRFreeOutputInfo(o);
@@ -2692,10 +2702,7 @@ static void context_cleanup(struct context *ctx)
if (output == NULL)
continue;
- if (output->crtc)
- XRRSetCrtcConfig(dpy, res, output->crtc, CurrentTime,
- 0, 0, None, RR_Rotate_0, NULL, 0);
-
+ disable_crtc(dpy, res, output->crtc);
for (j = 0; j < output->nmode; j++)
XRRDeleteOutputMode(dpy, clone->src.rr_output, output->modes[j]);
commit cbcc1b6190ab733c9ab11543af4a4eb1890225e4
Author: Kenneth Graunke <kenneth at whitecape.org>
Date: Thu Mar 6 13:12:32 2014 -0800
uxa: Enable BLT acceleration on Broadwell.
This supports solid, copy, put_image, and get_image acceleration via the
BLT engine. RENDER acceleration (composite) and Xv would be piles of work,
which is not worth doing since SNA exists, and Glamor is coming.
Signed-off-by: Kenneth Graunke <kenneth at whitecape.org>
diff --git a/configure.ac b/configure.ac
index 18c1d2b..7bf07ae 100644
--- a/configure.ac
+++ b/configure.ac
@@ -312,13 +312,14 @@ if test "x$SNA" != "xno"; then
AC_CHECK_HEADERS([sys/sysinfo.h], AC_CHECK_MEMBERS([struct sysinfo.totalram], [], [], [[#include <sys/sysinfo.h>]]))
fi
+uxa_requires_libdrm=2.4.52
AC_ARG_ENABLE(uxa,
AS_HELP_STRING([--enable-uxa],
- [Enable Unified Acceleration Architecture (UXA) [default=yes]]),
+ [Enable Unified Acceleration Architecture (UXA) [default=auto]]),
[UXA="$enableval"],
[UXA=auto])
if test "x$UXA" = "xauto"; then
- if ! pkg-config --exists 'libdrm_intel >= 2.4.29'; then
+ if ! pkg-config --exists "libdrm_intel >= $uxa_requires_libdrm"; then
UXA=no
fi
if ! pkg-config --exists 'pixman-1 >= 0.24.0'; then
@@ -327,7 +328,7 @@ if test "x$UXA" = "xauto"; then
fi
if test "x$UXA" != "xno"; then
AC_DEFINE(USE_UXA, 1, [Enable UXA support])
- PKG_CHECK_MODULES(DRMINTEL, [libdrm_intel >= 2.4.29])
+ PKG_CHECK_MODULES(DRMINTEL, [libdrm_intel >= $uxa_requires_libdrm])
required_pixman_version=0.24
UXA=yes
fi
diff --git a/src/uxa/intel_batchbuffer.c b/src/uxa/intel_batchbuffer.c
index 579a63a..4aabe48 100644
--- a/src/uxa/intel_batchbuffer.c
+++ b/src/uxa/intel_batchbuffer.c
@@ -183,6 +183,7 @@ void intel_batch_emit_flush(ScrnInfoPtr scrn)
int flags;
assert (!intel->in_batch_atomic);
+ assert (INTEL_INFO(intel)->gen < 0100);
/* Big hammer, look to the pipelined flushes in future. */
if ((INTEL_INFO(intel)->gen >= 060)) {
diff --git a/src/uxa/intel_batchbuffer.h b/src/uxa/intel_batchbuffer.h
index b2bb390..79e2ab0 100644
--- a/src/uxa/intel_batchbuffer.h
+++ b/src/uxa/intel_batchbuffer.h
@@ -108,6 +108,8 @@ intel_batch_emit_reloc(intel_screen_private *intel,
uint32_t read_domains,
uint32_t write_domains, uint32_t delta, int needs_fence)
{
+ uint64_t offset;
+
if (needs_fence)
drm_intel_bo_emit_reloc_fence(intel->batch_bo,
intel->batch_used * 4,
@@ -118,7 +120,11 @@ intel_batch_emit_reloc(intel_screen_private *intel,
bo, delta,
read_domains, write_domains);
- intel_batch_emit_dword(intel, bo->offset + delta);
+ offset = bo->offset64 + delta;
+
+ intel_batch_emit_dword(intel, offset);
+ if (INTEL_INFO(intel)->gen >= 0100)
+ intel_batch_emit_dword(intel, offset >> 32);
}
static inline void
diff --git a/src/uxa/intel_driver.c b/src/uxa/intel_driver.c
index 46e06df..7ea3b63 100644
--- a/src/uxa/intel_driver.c
+++ b/src/uxa/intel_driver.c
@@ -405,9 +405,6 @@ static Bool can_accelerate_blt(struct intel_screen_private *intel)
if (INTEL_INFO(intel)->gen == -1)
return FALSE;
- if (INTEL_INFO(intel)->gen >= 0100)
- return FALSE;
-
if (xf86ReturnOptValBool(intel->Options, OPTION_ACCEL_DISABLE, FALSE) ||
!intel_option_cast_string_to_bool(intel, OPTION_ACCEL_METHOD, TRUE)) {
xf86DrvMsg(intel->scrn->scrnIndex, X_CONFIG,
@@ -938,7 +935,7 @@ I830ScreenInit(SCREEN_INIT_ARGS_DECL)
intel_batch_init(scrn);
- if (INTEL_INFO(intel)->gen >= 040)
+ if (INTEL_INFO(intel)->gen >= 040 && INTEL_INFO(intel)->gen < 0100)
gen4_render_state_init(scrn);
miClearVisualTypes();
@@ -1193,7 +1190,7 @@ static Bool I830CloseScreen(CLOSE_SCREEN_ARGS_DECL)
intel_batch_teardown(scrn);
- if (INTEL_INFO(intel)->gen >= 040)
+ if (INTEL_INFO(intel)->gen >= 040 && INTEL_INFO(intel)->gen < 0100)
gen4_render_state_cleanup(scrn);
xf86_cursors_fini(screen);
diff --git a/src/uxa/intel_uxa.c b/src/uxa/intel_uxa.c
index 5314855..e90b148 100644
--- a/src/uxa/intel_uxa.c
+++ b/src/uxa/intel_uxa.c
@@ -324,9 +324,10 @@ static void intel_uxa_solid(PixmapPtr pixmap, int x1, int y1, int x2, int y2)
pitch = intel_pixmap_pitch(pixmap);
{
- BEGIN_BATCH_BLT(6);
+ int len = INTEL_INFO(intel)->gen >= 0100 ? 7 : 6;
+ BEGIN_BATCH_BLT(len);
- cmd = XY_COLOR_BLT_CMD | (6 - 2);
+ cmd = XY_COLOR_BLT_CMD | (len - 2);
if (pixmap->drawable.bitsPerPixel == 32)
cmd |=
@@ -462,9 +463,10 @@ intel_uxa_copy(PixmapPtr dest, int src_x1, int src_y1, int dst_x1,
src_pitch = intel_pixmap_pitch(intel->render_source);
{
- BEGIN_BATCH_BLT(8);
+ int len = INTEL_INFO(intel)->gen >= 0100 ? 10 : 8;
+ BEGIN_BATCH_BLT(len);
- cmd = XY_SRC_COPY_BLT_CMD | (8 - 2);
+ cmd = XY_SRC_COPY_BLT_CMD | (len - 2);
if (dest->drawable.bitsPerPixel == 32)
cmd |=
@@ -509,7 +511,7 @@ static void intel_uxa_done(PixmapPtr pixmap)
ScrnInfoPtr scrn = xf86ScreenToScrn(pixmap->drawable.pScreen);
intel_screen_private *intel = intel_get_screen_private(scrn);
- if (IS_GEN6(intel) || IS_GEN7(intel)) {
+ if (INTEL_INFO(intel)->gen >= 060) {
/* workaround a random BLT hang */
BEGIN_BATCH_BLT(3);
OUT_BATCH(XY_SETUP_CLIP_BLT_CMD | (3 - 2));
@@ -1354,7 +1356,7 @@ Bool intel_uxa_init(ScreenPtr screen)
/* Composite */
if (intel_option_accel_blt(intel)) {
- } else if (IS_GEN2(intel)) {
+ } else if (INTEL_INFO(intel)->gen < 030) {
intel->uxa_driver->check_composite = i830_check_composite;
intel->uxa_driver->check_composite_target = i830_check_composite_target;
intel->uxa_driver->check_composite_texture = i830_check_composite_texture;
@@ -1364,7 +1366,7 @@ Bool intel_uxa_init(ScreenPtr screen)
intel->vertex_flush = i830_vertex_flush;
intel->batch_commit_notify = i830_batch_commit_notify;
- } else if (IS_GEN3(intel)) {
+ } else if (INTEL_INFO(intel)->gen < 040) {
intel->uxa_driver->check_composite = i915_check_composite;
intel->uxa_driver->check_composite_target = i915_check_composite_target;
intel->uxa_driver->check_composite_texture = i915_check_composite_texture;
@@ -1374,7 +1376,7 @@ Bool intel_uxa_init(ScreenPtr screen)
intel->vertex_flush = i915_vertex_flush;
intel->batch_commit_notify = i915_batch_commit_notify;
- } else {
+ } else if (INTEL_INFO(intel)->gen < 0100) {
intel->uxa_driver->check_composite = i965_check_composite;
intel->uxa_driver->check_composite_texture = i965_check_composite_texture;
intel->uxa_driver->prepare_composite = i965_prepare_composite;
@@ -1385,9 +1387,9 @@ Bool intel_uxa_init(ScreenPtr screen)
intel->batch_flush = i965_batch_flush;
intel->batch_commit_notify = i965_batch_commit_notify;
- if (IS_GEN4(intel)) {
+ if (INTEL_INFO(intel)->gen < 050) {
intel->context_switch = gen4_context_switch;
- } else if (IS_GEN5(intel)) {
+ } else if (INTEL_INFO(intel)->gen < 060) {
intel->context_switch = gen5_context_switch;
} else {
intel->context_switch = gen6_context_switch;
diff --git a/src/uxa/intel_video.c b/src/uxa/intel_video.c
index 01919e3..73fb611 100644
--- a/src/uxa/intel_video.c
+++ b/src/uxa/intel_video.c
@@ -356,7 +356,8 @@ void I830InitVideo(ScreenPtr screen)
*/
if (!intel->force_fallback &&
scrn->bitsPerPixel >= 16 &&
- INTEL_INFO(intel)->gen >= 030) {
+ INTEL_INFO(intel)->gen >= 030 &&
+ INTEL_INFO(intel)->gen < 0100) {
texturedAdaptor = I830SetupImageVideoTextured(screen);
if (texturedAdaptor != NULL) {
xf86DrvMsg(scrn->scrnIndex, X_INFO,
commit c1d7abadbb0009e9f2b9d8d3744d4ae5c13a1c8f
Author: Kenneth Graunke <kenneth at whitecape.org>
Date: Thu Mar 6 13:12:31 2014 -0800
uxa: Remove implicit length from BLT command #defines.
These command packets grew on Gen8.
Signed-off-by: Kenneth Graunke <kenneth at whitecape.org>
diff --git a/src/uxa/i830_reg.h b/src/uxa/i830_reg.h
index 93d03cf..d8306bc 100644
--- a/src/uxa/i830_reg.h
+++ b/src/uxa/i830_reg.h
@@ -70,32 +70,32 @@
#define COLOR_BLT_WRITE_ALPHA (1<<21)
#define COLOR_BLT_WRITE_RGB (1<<20)
-#define XY_COLOR_BLT_CMD ((2<<29)|(0x50<<22)|(0x4))
+#define XY_COLOR_BLT_CMD ((2<<29)|(0x50<<22))
#define XY_COLOR_BLT_WRITE_ALPHA (1<<21)
#define XY_COLOR_BLT_WRITE_RGB (1<<20)
#define XY_COLOR_BLT_TILED (1<<11)
-#define XY_SETUP_CLIP_BLT_CMD ((2<<29)|(3<<22)|1)
+#define XY_SETUP_CLIP_BLT_CMD ((2<<29)|(3<<22))
-#define XY_SRC_COPY_BLT_CMD ((2<<29)|(0x53<<22)|6)
+#define XY_SRC_COPY_BLT_CMD ((2<<29)|(0x53<<22))
#define XY_SRC_COPY_BLT_WRITE_ALPHA (1<<21)
#define XY_SRC_COPY_BLT_WRITE_RGB (1<<20)
#define XY_SRC_COPY_BLT_SRC_TILED (1<<15)
#define XY_SRC_COPY_BLT_DST_TILED (1<<11)
-#define SRC_COPY_BLT_CMD ((2<<29)|(0x43<<22)|0x4)
+#define SRC_COPY_BLT_CMD ((2<<29)|(0x43<<22))
#define SRC_COPY_BLT_WRITE_ALPHA (1<<21)
#define SRC_COPY_BLT_WRITE_RGB (1<<20)
#define XY_PAT_BLT_IMMEDIATE ((2<<29)|(0x72<<22))
-#define XY_MONO_PAT_BLT_CMD ((0x2<<29)|(0x52<<22)|0x7)
+#define XY_MONO_PAT_BLT_CMD ((0x2<<29)|(0x52<<22))
#define XY_MONO_PAT_VERT_SEED ((1<<10)|(1<<9)|(1<<8))
#define XY_MONO_PAT_HORT_SEED ((1<<14)|(1<<13)|(1<<12))
#define XY_MONO_PAT_BLT_WRITE_ALPHA (1<<21)
#define XY_MONO_PAT_BLT_WRITE_RGB (1<<20)
-#define XY_MONO_SRC_BLT_CMD ((0x2<<29)|(0x54<<22)|(0x6))
+#define XY_MONO_SRC_BLT_CMD ((0x2<<29)|(0x54<<22))
#define XY_MONO_SRC_BLT_WRITE_ALPHA (1<<21)
#define XY_MONO_SRC_BLT_WRITE_RGB (1<<20)
diff --git a/src/uxa/intel_uxa.c b/src/uxa/intel_uxa.c
index d4ba7fc..5314855 100644
--- a/src/uxa/intel_uxa.c
+++ b/src/uxa/intel_uxa.c
@@ -326,7 +326,7 @@ static void intel_uxa_solid(PixmapPtr pixmap, int x1, int y1, int x2, int y2)
{
BEGIN_BATCH_BLT(6);
- cmd = XY_COLOR_BLT_CMD;
+ cmd = XY_COLOR_BLT_CMD | (6 - 2);
if (pixmap->drawable.bitsPerPixel == 32)
cmd |=
@@ -464,7 +464,7 @@ intel_uxa_copy(PixmapPtr dest, int src_x1, int src_y1, int dst_x1,
{
BEGIN_BATCH_BLT(8);
- cmd = XY_SRC_COPY_BLT_CMD;
+ cmd = XY_SRC_COPY_BLT_CMD | (8 - 2);
if (dest->drawable.bitsPerPixel == 32)
cmd |=
@@ -512,7 +512,7 @@ static void intel_uxa_done(PixmapPtr pixmap)
if (IS_GEN6(intel) || IS_GEN7(intel)) {
/* workaround a random BLT hang */
BEGIN_BATCH_BLT(3);
- OUT_BATCH(XY_SETUP_CLIP_BLT_CMD);
+ OUT_BATCH(XY_SETUP_CLIP_BLT_CMD | (3 - 2));
OUT_BATCH(0);
OUT_BATCH(0);
ADVANCE_BATCH();
More information about the xorg-commit
mailing list