xf86-video-ati: Branch 'master' - 2 commits

[Alex Deucher]

 src/drmmode_display.c |    2 +-
 src/radeon.h          |    2 +-
 src/radeon_kms.c      |   16 ++++++++++------
 src/radeon_video.c    |   19 ++++++++++++++++---
 4 files changed, 28 insertions(+), 11 deletions(-)

New commits:
commit 4fc1fa920584ace2c84d75af82d06962d0c84ec8
Author: Alex Deucher <alexander.deucher at amd.com>
Date:   Thu Sep 26 11:02:55 2013 -0400

    radeon: add glamor Xv support (v2)
    
    v2: guard new glamor Xv bits with USE_GLAMOR
    
    Signed-off-by: Alex Deucher <alexander.deucher at amd.com>
    Reviewed-by: Michel Dänzer <michel.daenzer at amd.com>

diff --git a/src/radeon_kms.c b/src/radeon_kms.c
index 9708dc7..255906b 100644
--- a/src/radeon_kms.c
+++ b/src/radeon_kms.c
@@ -1321,7 +1321,7 @@ Bool RADEONScreenInit_KMS(SCREEN_INIT_ARGS_DECL)
      */
     /* xf86DiDGAInit(pScreen, info->LinearAddr + pScrn->fbOffset); */
 #endif
-    if (!info->use_glamor && info->r600_shadow_fb == FALSE) {
+    if (info->r600_shadow_fb == FALSE) {
         /* Init Xv */
         xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG,
                        "Initializing Xv\n");
diff --git a/src/radeon_video.c b/src/radeon_video.c
index 56cd9ab..b07636c 100644
--- a/src/radeon_video.c
+++ b/src/radeon_video.c
@@ -16,6 +16,10 @@
 #include "xf86.h"
 #include "dixstruct.h"
 
+#ifdef USE_GLAMOR
+#include <glamor.h>
+#endif
+
 /* DPMS */
 #ifdef HAVE_XEXTPROTO_71
 #include <X11/extensions/dpmsconst.h>
@@ -165,9 +169,18 @@ void RADEONInitVideo(ScreenPtr pScreen)
     memcpy(newAdaptors, adaptors, num_adaptors * sizeof(XF86VideoAdaptorPtr));
     adaptors = newAdaptors;
 
-    if ((info->ChipFamily < CHIP_FAMILY_RS400)
-	|| (info->directRenderingEnabled)
-	) {
+#ifdef USE_GLAMOR
+    if (info->use_glamor) {
+	texturedAdaptor = glamor_xv_init(pScreen, 16);
+	if (texturedAdaptor != NULL) {
+	    adaptors[num_adaptors++] = texturedAdaptor;
+	    xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Set up glamor textured video\n");
+	} else
+	    xf86DrvMsg(pScrn->scrnIndex, X_ERROR, "Failed to set up glamor textured video\n");
+    } else
+#endif
+	if ((info->ChipFamily < CHIP_FAMILY_RS400)
+	       || info->directRenderingEnabled) {
 	texturedAdaptor = RADEONSetupImageTexturedVideo(pScreen);
 	if (texturedAdaptor != NULL) {
 	    adaptors[num_adaptors++] = texturedAdaptor;
commit 41dfe327ac8740ac2cd84def96b5947224e422e7
Author: Alex Deucher <alexander.deucher at amd.com>
Date:   Thu Sep 26 11:00:49 2013 -0400

    radeon: fix limit handling for cards with >4G of ram
    
    We can overflow the 32-bit limit.
    
    Signed-off-by: Alex Deucher <alexander.deucher at amd.com>
    Reviewed-by: Michel Dänzer <michel.daenzer at amd.com>

diff --git a/src/drmmode_display.c b/src/drmmode_display.c
index 921b7ba..76b79d8 100644
--- a/src/drmmode_display.c
+++ b/src/drmmode_display.c
@@ -1478,7 +1478,7 @@ drmmode_xf86crtc_resize (ScrnInfoPtr scrn, int width, int height)
 	ScreenPtr   screen = xf86ScrnToScreen(scrn);
 	uint32_t    old_fb_id;
 	int	    i, pitch, old_width, old_height, old_pitch;
-	int screen_size;
+	uint32_t screen_size;
 	int cpp = info->pixel_bytes;
 	struct radeon_bo *front_bo;
 	struct radeon_surface surface;
diff --git a/src/radeon.h b/src/radeon.h
index 4660893..f1817e7 100644
--- a/src/radeon.h
+++ b/src/radeon.h
@@ -524,7 +524,7 @@ extern void radeon_cs_flush_indirect(ScrnInfoPtr pScrn);
 extern void radeon_ddx_cs_start(ScrnInfoPtr pScrn,
 				int num, const char *file,
 				const char *func, int line);
-void radeon_kms_update_vram_limit(ScrnInfoPtr pScrn, int new_fb_size);
+void radeon_kms_update_vram_limit(ScrnInfoPtr pScrn, uint32_t new_fb_size);
 extern RADEONEntPtr RADEONEntPriv(ScrnInfoPtr pScrn);
 
 drmVBlankSeqType radeon_populate_vbl_request_type(xf86CrtcPtr crtc);
diff --git a/src/radeon_kms.c b/src/radeon_kms.c
index 82e88d4..9708dc7 100644
--- a/src/radeon_kms.c
+++ b/src/radeon_kms.c
@@ -1450,7 +1450,7 @@ static Bool radeon_setup_kernel_mem(ScreenPtr pScreen)
     RADEONInfoPtr info = RADEONPTR(pScrn);
     xf86CrtcConfigPtr   xf86_config = XF86_CRTC_CONFIG_PTR(pScrn);
     int cpp = info->pixel_bytes;
-    int screen_size;
+    uint32_t screen_size;
     int pitch, base_align;
     uint32_t tiling_flags = 0;
     struct radeon_surface surface;
@@ -1600,11 +1600,11 @@ static Bool radeon_setup_kernel_mem(ScreenPtr pScreen)
     return TRUE;
 }
 
-void radeon_kms_update_vram_limit(ScrnInfoPtr pScrn, int new_fb_size)
+void radeon_kms_update_vram_limit(ScrnInfoPtr pScrn, uint32_t new_fb_size)
 {
     xf86CrtcConfigPtr   xf86_config = XF86_CRTC_CONFIG_PTR(pScrn);
     RADEONInfoPtr info = RADEONPTR(pScrn);
-    int remain_size_bytes;
+    uint64_t remain_size_bytes;
     int c;
 
     for (c = 0; c < xf86_config->num_crtc; c++) {
@@ -1615,9 +1615,13 @@ void radeon_kms_update_vram_limit(ScrnInfoPtr pScrn, int new_fb_size)
 
     remain_size_bytes = info->vram_size - new_fb_size;
     remain_size_bytes = (remain_size_bytes / 10) * 9;
-    radeon_cs_set_limit(info->cs, RADEON_GEM_DOMAIN_VRAM, remain_size_bytes);
+    if (remain_size_bytes > 0xffffffff)
+	remain_size_bytes = 0xffffffff;
+    radeon_cs_set_limit(info->cs, RADEON_GEM_DOMAIN_VRAM,
+			(uint32_t)remain_size_bytes);
 
-    xf86DrvMsg(pScrn->scrnIndex, X_INFO, "VRAM usage limit set to %dK\n", remain_size_bytes / 1024);
+    xf86DrvMsg(pScrn->scrnIndex, X_INFO, "VRAM usage limit set to %uK\n",
+	       (uint32_t)remain_size_bytes / 1024);
 }
 
 /* Used to disallow modes that are not supported by the hardware */