xf86-video-intel: 2 commits - src/sna/gen4_render.c src/sna/gen5_render.c src/sna/gen6_render.c src/sna/gen7_render.c src/sna/gen7_render.h
Chris Wilson
ickle at kemper.freedesktop.org
Wed Mar 27 10:10:12 PDT 2013
src/sna/gen4_render.c | 9 +++++----
src/sna/gen5_render.c | 9 +++++----
src/sna/gen6_render.c | 9 +++++----
src/sna/gen7_render.c | 13 ++++++++-----
src/sna/gen7_render.h | 2 ++
5 files changed, 25 insertions(+), 17 deletions(-)
New commits:
commit 19dfa72c28c6dc677dbfec3a538d4481985195e5
Author: Chris Wilson <chris at chris-wilson.co.uk>
Date: Wed Mar 27 16:56:10 2013 +0000
sna/gen4+: Set read-write allocation mode for the target render cache
As we often first clear the destination before performing a blend, we
get a performance boost if that first write populates the render cache.
Signed-off-by: Chris Wilson <chris at chris-wilson.co.uk>
diff --git a/src/sna/gen4_render.c b/src/sna/gen4_render.c
index e40a1b7..1bf5ad2 100644
--- a/src/sna/gen4_render.c
+++ b/src/sna/gen4_render.c
@@ -502,7 +502,7 @@ gen4_bind_bo(struct sna *sna,
assert(sna->kgem.gen != 040 || !kgem_bo_is_snoop(bo));
/* After the first bind, we manage the cache domains within the batch */
- offset = kgem_bo_get_binding(bo, format);
+ offset = kgem_bo_get_binding(bo, format | is_dst << 31);
if (offset) {
if (is_dst)
kgem_bo_mark_dirty(bo);
@@ -517,9 +517,10 @@ gen4_bind_bo(struct sna *sna,
GEN4_SURFACE_BLEND_ENABLED |
format << GEN4_SURFACE_FORMAT_SHIFT);
- if (is_dst)
+ if (is_dst) {
+ ss[0] |= GEN4_SURFACE_RC_READ_WRITE;
domains = I915_GEM_DOMAIN_RENDER << 16 | I915_GEM_DOMAIN_RENDER;
- else
+ } else
domains = I915_GEM_DOMAIN_SAMPLER << 16;
ss[1] = kgem_add_reloc(&sna->kgem, offset + 1, bo, domains, 0);
@@ -530,7 +531,7 @@ gen4_bind_bo(struct sna *sna,
ss[4] = 0;
ss[5] = 0;
- kgem_bo_set_binding(bo, format, offset);
+ kgem_bo_set_binding(bo, format | is_dst << 31, offset);
DBG(("[%x] bind bo(handle=%d, addr=%d), format=%d, width=%d, height=%d, pitch=%d, tiling=%d -> %s\n",
offset, bo->handle, ss[1],
diff --git a/src/sna/gen5_render.c b/src/sna/gen5_render.c
index 8b50d22..7038444 100644
--- a/src/sna/gen5_render.c
+++ b/src/sna/gen5_render.c
@@ -490,7 +490,7 @@ gen5_bind_bo(struct sna *sna,
/* After the first bind, we manage the cache domains within the batch */
if (!DBG_NO_SURFACE_CACHE) {
- offset = kgem_bo_get_binding(bo, format);
+ offset = kgem_bo_get_binding(bo, format | is_dst << 31);
if (offset) {
if (is_dst)
kgem_bo_mark_dirty(bo);
@@ -506,9 +506,10 @@ gen5_bind_bo(struct sna *sna,
GEN5_SURFACE_BLEND_ENABLED |
format << GEN5_SURFACE_FORMAT_SHIFT);
- if (is_dst)
+ if (is_dst) {
+ ss[0] |= GEN5_SURFACE_RC_READ_WRITE;
domains = I915_GEM_DOMAIN_RENDER << 16 | I915_GEM_DOMAIN_RENDER;
- else
+ } else
domains = I915_GEM_DOMAIN_SAMPLER << 16;
ss[1] = kgem_add_reloc(&sna->kgem, offset + 1, bo, domains, 0);
@@ -519,7 +520,7 @@ gen5_bind_bo(struct sna *sna,
ss[4] = 0;
ss[5] = 0;
- kgem_bo_set_binding(bo, format, offset);
+ kgem_bo_set_binding(bo, format | is_dst << 31, offset);
DBG(("[%x] bind bo(handle=%d, addr=%d), format=%d, width=%d, height=%d, pitch=%d, tiling=%d -> %s\n",
offset, bo->handle, ss[1],
diff --git a/src/sna/gen6_render.c b/src/sna/gen6_render.c
index 64eccc5..8101faf 100644
--- a/src/sna/gen6_render.c
+++ b/src/sna/gen6_render.c
@@ -1035,7 +1035,7 @@ gen6_bind_bo(struct sna *sna,
uint32_t is_scanout = is_dst && bo->scanout;
/* After the first bind, we manage the cache domains within the batch */
- offset = kgem_bo_get_binding(bo, format | is_scanout << 31);
+ offset = kgem_bo_get_binding(bo, format | is_dst << 30 | is_scanout << 31);
if (offset) {
DBG(("[%x] bo(handle=%d), format=%d, reuse %s binding\n",
offset, bo->handle, format,
@@ -1051,9 +1051,10 @@ gen6_bind_bo(struct sna *sna,
ss[0] = (GEN6_SURFACE_2D << GEN6_SURFACE_TYPE_SHIFT |
GEN6_SURFACE_BLEND_ENABLED |
format << GEN6_SURFACE_FORMAT_SHIFT);
- if (is_dst)
+ if (is_dst) {
+ ss[0] |= GEN6_SURFACE_RC_READ_WRITE;
domains = I915_GEM_DOMAIN_RENDER << 16 |I915_GEM_DOMAIN_RENDER;
- else
+ } else
domains = I915_GEM_DOMAIN_SAMPLER << 16;
ss[1] = kgem_add_reloc(&sna->kgem, offset + 1, bo, domains, 0);
ss[2] = ((width - 1) << GEN6_SURFACE_WIDTH_SHIFT |
@@ -1064,7 +1065,7 @@ gen6_bind_bo(struct sna *sna,
ss[4] = 0;
ss[5] = is_scanout ? 0 : 3 << 16;
- kgem_bo_set_binding(bo, format | is_scanout << 31, offset);
+ kgem_bo_set_binding(bo, format | is_dst << 30 | is_scanout << 31, offset);
DBG(("[%x] bind bo(handle=%d, addr=%d), format=%d, width=%d, height=%d, pitch=%d, tiling=%d -> %s\n",
offset, bo->handle, ss[1],
commit d9b8c2039d1be17af8c56364341fc3e10795f200
Author: Chris Wilson <chris at chris-wilson.co.uk>
Date: Wed Mar 27 14:49:15 2013 +0000
sna/gen7: Fix MOCS for Haswell
The memory attributes changed slightly, and in particular there is now
an explicit uncached setting - which of course happened to be the value
currently selected.
Signed-off-by: Chris Wilson <chris at chris-wilson.co.uk>
diff --git a/src/sna/gen7_render.c b/src/sna/gen7_render.c
index 9e40860..773d2f3 100644
--- a/src/sna/gen7_render.c
+++ b/src/sna/gen7_render.c
@@ -1190,7 +1190,7 @@ gen7_bind_bo(struct sna *sna,
COMPILE_TIME_ASSERT(sizeof(struct gen7_surface_state) == 32);
/* After the first bind, we manage the cache domains within the batch */
- offset = kgem_bo_get_binding(bo, format | is_scanout << 31);
+ offset = kgem_bo_get_binding(bo, format | is_dst << 30 | is_scanout << 31);
if (offset) {
if (is_dst)
kgem_bo_mark_dirty(bo);
@@ -1203,22 +1203,25 @@ gen7_bind_bo(struct sna *sna,
ss[0] = (GEN7_SURFACE_2D << GEN7_SURFACE_TYPE_SHIFT |
gen7_tiling_bits(bo->tiling) |
format << GEN7_SURFACE_FORMAT_SHIFT);
- if (is_dst)
+ if (bo->tiling == I915_TILING_Y)
+ ss[0] |= GEN7_SURFACE_VALIGN_4;
+ if (is_dst) {
+ ss[0] |= GEN7_SURFACE_RC_READ_WRITE;
domains = I915_GEM_DOMAIN_RENDER << 16 |I915_GEM_DOMAIN_RENDER;
- else
+ } else
domains = I915_GEM_DOMAIN_SAMPLER << 16;
ss[1] = kgem_add_reloc(&sna->kgem, offset + 1, bo, domains, 0);
ss[2] = ((width - 1) << GEN7_SURFACE_WIDTH_SHIFT |
(height - 1) << GEN7_SURFACE_HEIGHT_SHIFT);
ss[3] = (bo->pitch - 1) << GEN7_SURFACE_PITCH_SHIFT;
ss[4] = 0;
- ss[5] = is_scanout ? 0 : 3 << 16;
+ ss[5] = is_scanout ? 0 : sna->kgem.gen == 075 ? 5 << 16 : 3 << 16;
ss[6] = 0;
ss[7] = 0;
if (sna->kgem.gen == 075)
ss[7] |= HSW_SURFACE_SWIZZLE(RED, GREEN, BLUE, ALPHA);
- kgem_bo_set_binding(bo, format | is_scanout << 31, offset);
+ kgem_bo_set_binding(bo, format | is_dst << 30 | is_scanout << 31, offset);
DBG(("[%x] bind bo(handle=%d, addr=%d), format=%d, width=%d, height=%d, pitch=%d, tiling=%d -> %s\n",
offset, bo->handle, ss[1],
diff --git a/src/sna/gen7_render.h b/src/sna/gen7_render.h
index 1661d4c..cacddf4 100644
--- a/src/sna/gen7_render.h
+++ b/src/sna/gen7_render.h
@@ -1224,6 +1224,8 @@ struct gen7_sampler_state {
/* Surface state DW0 */
#define GEN7_SURFACE_RC_READ_WRITE (1 << 8)
+#define GEN7_SURFACE_VALIGN_4 (1 << 16)
+#define GEN7_SURFACE_HALIGN_8 (1 << 15)
#define GEN7_SURFACE_TILED (1 << 14)
#define GEN7_SURFACE_TILED_Y (1 << 13)
#define GEN7_SURFACE_FORMAT_SHIFT 18
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