xf86-video-intel: 9 commits - src/intel_device.c src/sna/kgem.c src/sna/sna_accel.c src/sna/sna_driver.c
Chris Wilson
ickle at kemper.freedesktop.org
Wed Jun 26 02:03:46 PDT 2013
src/intel_device.c | 6 +++-
src/sna/kgem.c | 33 +++++++++++++++++++++-----
src/sna/sna_accel.c | 63 ++++++++++++++++++++++++++++++++-------------------
src/sna/sna_driver.c | 1
4 files changed, 71 insertions(+), 32 deletions(-)
New commits:
commit fc5b9a96194583c67705d7d05afc3e04e97e3338
Author: Chris Wilson <chris at chris-wilson.co.uk>
Date: Tue Jun 25 22:58:31 2013 +0100
sna: Clear mapped state after performing manual tiling
Signed-off-by: Chris Wilson <chris at chris-wilson.co.uk>
diff --git a/src/sna/sna_accel.c b/src/sna/sna_accel.c
index 0bd9bbe..065def9 100644
--- a/src/sna/sna_accel.c
+++ b/src/sna/sna_accel.c
@@ -4010,6 +4010,12 @@ try_upload_tiled_x(PixmapPtr pixmap, RegionRec *region,
if (priv->cpu_damage)
sna_damage_subtract(&priv->cpu_damage, region);
+ if (priv->mapped) {
+ assert(!priv->shm);
+ priv->pixmap->devPrivate.ptr = NULL;
+ priv->mapped = false;
+ }
+
priv->clear = false;
priv->cpu = false;
return true;
commit 3f33abee370bb1ce60bca91f29affc62d06b0bad
Author: Chris Wilson <chris at chris-wilson.co.uk>
Date: Tue Jun 25 22:43:48 2013 +0100
sna: Do not force creation of CPU maps on !llc
Signed-off-by: Chris Wilson <chris at chris-wilson.co.uk>
diff --git a/src/sna/kgem.c b/src/sna/kgem.c
index a9724e1..55c4fe5 100644
--- a/src/sna/kgem.c
+++ b/src/sna/kgem.c
@@ -3848,8 +3848,13 @@ large_inactive:
} while (!list_is_empty(cache) &&
__kgem_throttle_retire(kgem, flags));
- if (flags & CREATE_CPU_MAP && !kgem->has_llc)
+ if (flags & CREATE_CPU_MAP && !kgem->has_llc) {
+ if (list_is_empty(&kgem->active[bucket][tiling]) &&
+ list_is_empty(&kgem->inactive[bucket]))
+ flags &= ~CREATE_CACHED;
+
goto create;
+ }
}
if (flags & CREATE_INACTIVE)
@@ -4083,6 +4088,9 @@ search_inactive:
}
create:
+ if (flags & CREATE_CACHED)
+ return NULL;
+
if (bucket >= NUM_CACHE_BUCKETS)
size = ALIGN(size, 1024);
handle = gem_create(kgem->fd, size);
diff --git a/src/sna/sna_accel.c b/src/sna/sna_accel.c
index 428535e..0bd9bbe 100644
--- a/src/sna/sna_accel.c
+++ b/src/sna/sna_accel.c
@@ -3901,7 +3901,7 @@ create_upload_tiled_x(struct kgem *kgem,
{
unsigned create, tiling;
- if (priv->shm)
+ if (priv->shm || priv->cpu)
return false;
if ((priv->create & KGEM_CAN_CREATE_GPU) == 0)
@@ -3917,6 +3917,8 @@ create_upload_tiled_x(struct kgem *kgem,
create = CREATE_CPU_MAP | CREATE_INACTIVE | CREATE_EXACT;
if (pixmap->usage_hint == SNA_CREATE_FB)
create |= CREATE_SCANOUT;
+ if (!kgem->has_llc)
+ create |= CREATE_CACHED;
priv->gpu_bo =
kgem_create_2d(kgem,
commit 77fa8ab08b441934218ddb8f690be1a919f0ec64
Author: Chris Wilson <chris at chris-wilson.co.uk>
Date: Tue Jun 25 22:25:25 2013 +0100
sna: Free just-allocated bo if we fail to set-tiling on CREATE_EXACT
If the caller requires an exactly constructed bo, abandon the attempt if
we cannot set the tiling as specified.
Signed-off-by: Chris Wilson <chris at chris-wilson.co.uk>
diff --git a/src/sna/kgem.c b/src/sna/kgem.c
index 8e056d3..a9724e1 100644
--- a/src/sna/kgem.c
+++ b/src/sna/kgem.c
@@ -3777,6 +3777,7 @@ large_inactive:
list_del(&bo->list);
+ assert(bo->domain != DOMAIN_GPU);
bo->unique_id = kgem_get_unique_id(kgem);
bo->pitch = pitch;
bo->delta = 0;
@@ -3827,9 +3828,11 @@ large_inactive:
break;
}
+ assert(bo->tiling == tiling);
bo->pitch = pitch;
bo->delta = 0;
bo->unique_id = kgem_get_unique_id(kgem);
+ bo->domain = DOMAIN_NONE;
kgem_bo_remove_from_inactive(kgem, bo);
@@ -4092,18 +4095,26 @@ create:
return NULL;
}
- bo->domain = DOMAIN_CPU;
- bo->unique_id = kgem_get_unique_id(kgem);
- bo->pitch = pitch;
- if (tiling != I915_TILING_NONE &&
- gem_set_tiling(kgem->fd, handle, tiling, pitch))
- bo->tiling = tiling;
if (bucket >= NUM_CACHE_BUCKETS) {
DBG(("%s: marking large bo for automatic flushing\n",
__FUNCTION__));
bo->flush = true;
}
+ bo->unique_id = kgem_get_unique_id(kgem);
+ if (tiling == I915_TILING_NONE ||
+ gem_set_tiling(kgem->fd, handle, tiling, pitch)) {
+ bo->tiling = tiling;
+ bo->pitch = pitch;
+ } else {
+ if (flags & CREATE_EXACT) {
+ if (bo->pitch != pitch || bo->tiling != tiling) {
+ kgem_bo_free(kgem, bo);
+ return NULL;
+ }
+ }
+ }
+
assert(bytes(bo) >= bo->pitch * kgem_aligned_height(kgem, height, bo->tiling));
debug_alloc__bo(kgem, bo);
commit 273716029e5318f1670e7111be2085c950995d42
Author: Chris Wilson <chris at chris-wilson.co.uk>
Date: Tue Jun 25 21:35:09 2013 +0100
sna: Rearrange tiled x upload so that damage accumulation is last
Signed-off-by: Chris Wilson <chris at chris-wilson.co.uk>
diff --git a/src/sna/sna_accel.c b/src/sna/sna_accel.c
index 47b2509..428535e 100644
--- a/src/sna/sna_accel.c
+++ b/src/sna/sna_accel.c
@@ -3976,11 +3976,24 @@ try_upload_tiled_x(PixmapPtr pixmap, RegionRec *region,
if (dst == NULL)
return false;
+ kgem_bo_sync__cpu(&sna->kgem, priv->gpu_bo);
+
box = RegionRects(region);
n = RegionNumRects(region);
DBG(("%s: upload(%d, %d, %d, %d) x %d\n", __FUNCTION__, x, y, w, h, n));
+ do {
+ memcpy_to_tiled_x(&sna->kgem, bits, dst,
+ pixmap->drawable.bitsPerPixel,
+ stride, priv->gpu_bo->pitch,
+ box->x1 - x, box->y1 - y,
+ box->x1, box->y1,
+ box->x2 - box->x1, box->y2 - box->y1);
+ box++;
+ } while (--n);
+ __kgem_bo_unmap__cpu(&sna->kgem, priv->gpu_bo, dst);
+
if (!DAMAGE_IS_ALL(priv->gpu_damage)) {
sna_damage_add(&priv->gpu_damage, region);
sna_damage_reduce_all(&priv->gpu_damage,
@@ -3995,18 +4008,6 @@ try_upload_tiled_x(PixmapPtr pixmap, RegionRec *region,
if (priv->cpu_damage)
sna_damage_subtract(&priv->cpu_damage, region);
- kgem_bo_sync__cpu(&sna->kgem, priv->gpu_bo);
- do {
- memcpy_to_tiled_x(&sna->kgem, bits, dst,
- pixmap->drawable.bitsPerPixel,
- stride, priv->gpu_bo->pitch,
- box->x1 - x, box->y1 - y,
- box->x1, box->y1,
- box->x2 - box->x1, box->y2 - box->y1);
- box++;
- } while (--n);
- __kgem_bo_unmap__cpu(&sna->kgem, priv->gpu_bo, dst);
-
priv->clear = false;
priv->cpu = false;
return true;
commit e033a28bcb37867f3c947475714e1ef45c868825
Author: Chris Wilson <chris at chris-wilson.co.uk>
Date: Tue Jun 25 21:12:23 2013 +0100
sna: Optimize clears to white
Signed-off-by: Chris Wilson <chris at chris-wilson.co.uk>
diff --git a/src/sna/sna_accel.c b/src/sna/sna_accel.c
index 65d97c7..47b2509 100644
--- a/src/sna/sna_accel.c
+++ b/src/sna/sna_accel.c
@@ -1987,8 +1987,9 @@ skip_inplace_map:
assert(!priv->mapped);
if (priv->clear) {
- DBG(("%s: applying clear [%08x]\n",
- __FUNCTION__, priv->clear_color));
+ DBG(("%s: applying clear [%08x] size=%dx%d, stride=%d (total=%d)\n",
+ __FUNCTION__, priv->clear_color, pixmap->drawable.width, pixmap->drawable.height,
+ pixmap->devKind, pixmap->devKind * pixmap->drawable.height));
if (priv->cpu_bo) {
DBG(("%s: syncing CPU bo\n", __FUNCTION__));
@@ -1996,7 +1997,9 @@ skip_inplace_map:
assert(pixmap->devPrivate.ptr == (void *)((unsigned long)priv->cpu_bo->map & ~3));
}
- if (priv->clear_color == 0 || pixmap->drawable.bitsPerPixel == 8) {
+ if (priv->clear_color == 0 ||
+ pixmap->drawable.bitsPerPixel == 8 ||
+ priv->clear_color == (1 << pixmap->drawable.bitsPerPixel) - 1) {
memset(pixmap->devPrivate.ptr, priv->clear_color,
pixmap->devKind * pixmap->drawable.height);
} else {
@@ -14208,7 +14211,8 @@ sna_get_image_blt(DrawablePtr drawable,
pitch = PixmapBytePad(w, pixmap->drawable.depth);
if (priv->clear_color == 0 ||
- pixmap->drawable.bitsPerPixel == 8) {
+ pixmap->drawable.bitsPerPixel == 8 ||
+ priv->clear_color == (1U << pixmap->drawable.bitsPerPixel) - 1) {
memset(dst, priv->clear_color, pitch * h);
} else {
pixman_fill((uint32_t *)dst,
commit b77c334a26c55d3028971897dcba21407a7a4743
Author: Chris Wilson <chris at chris-wilson.co.uk>
Date: Tue Jun 25 19:08:30 2013 +0100
sna: Do not perform tiling inplace if the destination is busy
Rather than waiting on the GPU stall, just use the standard mechanisms to
queue the uploads.
Signed-off-by: Chris Wilson <chris at chris-wilson.co.uk>
diff --git a/src/sna/sna_accel.c b/src/sna/sna_accel.c
index b91d148..65d97c7 100644
--- a/src/sna/sna_accel.c
+++ b/src/sna/sna_accel.c
@@ -3959,6 +3959,16 @@ try_upload_tiled_x(PixmapPtr pixmap, RegionRec *region,
assert(priv->gpu_bo->tiling == I915_TILING_X);
+ if (region->data == NULL &&
+ w >= pixmap->drawable.width &&
+ h >= pixmap->drawable.height) {
+ DBG(("%s: discarding operations to GPU bo\n", __FUNCTION__));
+ kgem_bo_undo(&sna->kgem, priv->gpu_bo);
+ }
+
+ if (__kgem_bo_is_busy(&sna->kgem, priv->gpu_bo))
+ return false;
+
dst = __kgem_bo_map__cpu(&sna->kgem, priv->gpu_bo);
if (dst == NULL)
return false;
@@ -3968,13 +3978,6 @@ try_upload_tiled_x(PixmapPtr pixmap, RegionRec *region,
DBG(("%s: upload(%d, %d, %d, %d) x %d\n", __FUNCTION__, x, y, w, h, n));
- if (n == 1 &&
- w >= pixmap->drawable.width &&
- h >= pixmap->drawable.height) {
- DBG(("%s: discarding operations to GPU bo\n", __FUNCTION__));
- kgem_bo_undo(&sna->kgem, priv->gpu_bo);
- }
-
if (!DAMAGE_IS_ALL(priv->gpu_damage)) {
sna_damage_add(&priv->gpu_damage, region);
sna_damage_reduce_all(&priv->gpu_damage,
commit 4b0cdf28b884755cb842d3303fc0dd9bec62ab24
Author: Chris Wilson <chris at chris-wilson.co.uk>
Date: Tue Jun 25 18:09:36 2013 +0100
sna: Be explicit when creating tiled-x pixmaps for manual tiling uplaods
Signed-off-by: Chris Wilson <chris at chris-wilson.co.uk>
diff --git a/src/sna/sna_accel.c b/src/sna/sna_accel.c
index df34acd..b91d148 100644
--- a/src/sna/sna_accel.c
+++ b/src/sna/sna_accel.c
@@ -3920,7 +3920,7 @@ create_upload_tiled_x(struct kgem *kgem,
pixmap->drawable.width,
pixmap->drawable.height,
pixmap->drawable.bitsPerPixel,
- tiling, create);
+ I915_TILING_X, create);
return priv->gpu_bo != NULL;
}
@@ -3982,6 +3982,7 @@ try_upload_tiled_x(PixmapPtr pixmap, RegionRec *region,
pixmap->drawable.height);
if (DAMAGE_IS_ALL(priv->gpu_damage)) {
list_del(&priv->flush_list);
+ sna_damage_destroy(&priv->cpu_damage);
sna_pixmap_free_cpu(sna, priv);
}
}
commit 98feba417c87dce020df6a6ed157e3546591d8e7
Author: Chris Wilson <chris at chris-wilson.co.uk>
Date: Tue Jun 25 18:35:45 2013 +0100
sna: Drop master when closing the screen
As we reacquire master when initialisation the next gen of the server,
to keep the reference counting consistent we need to release our master
reference on CloseScreen.
Signed-off-by: Chris Wilson <chris at chris-wilson.co.uk>
diff --git a/src/intel_device.c b/src/intel_device.c
index 74c9301..1880a9b 100644
--- a/src/intel_device.c
+++ b/src/intel_device.c
@@ -196,8 +196,10 @@ int intel_put_master(ScrnInfoPtr scrn)
ret = 0;
assert(dev->master_count);
- if (--dev->master_count == 0)
+ if (--dev->master_count == 0) {
+ assert(ioctl(dev->fd, DRM_IOCTL_SET_MASTER) == 0);
ret = ioctl(dev->fd, DRM_IOCTL_DROP_MASTER);
+ }
return ret;
}
diff --git a/src/sna/sna_driver.c b/src/sna/sna_driver.c
index e203717..3428d5b 100644
--- a/src/sna/sna_driver.c
+++ b/src/sna/sna_driver.c
@@ -773,6 +773,7 @@ static Bool sna_late_close_screen(CLOSE_SCREEN_ARGS_DECL)
free(depths);
free(screen->visuals);
+ intel_put_master(xf86ScreenToScrn(screen));
return TRUE;
}
commit febfd388235fbe566a505d7d83733305cf344850
Author: Chris Wilson <chris at chris-wilson.co.uk>
Date: Tue Jun 25 18:05:28 2013 +0100
intel: Use the correct errno value for reporting the drmSetVersion failure
Signed-off-by: Chris Wilson <chris at chris-wilson.co.uk>
diff --git a/src/intel_device.c b/src/intel_device.c
index cb3cb16..74c9301 100644
--- a/src/intel_device.c
+++ b/src/intel_device.c
@@ -156,7 +156,7 @@ int intel_get_device(ScrnInfoPtr scrn)
if (ret != 0) {
xf86DrvMsg(scrn->scrnIndex, X_ERROR,
"[drm] failed to set drm interface version: %s [%d].\n",
- strerror(ret), ret);
+ strerror(errno), errno);
dev->open_count--;
return -1;
}
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