xf86-video-intel: src/sna/gen5_render.c src/sna/sna_render.h

[Chris Wilson]

 src/sna/gen5_render.c |   19 ++++++++++++++-----
 src/sna/sna_render.h  |    2 +-
 2 files changed, 15 insertions(+), 6 deletions(-)

New commits:
commit 74dd10d252df2d826b6db5da7e53bd7c5d76dec0
Author: Chris Wilson <chris at chris-wilson.co.uk>
Date:   Tue Jul 23 09:37:15 2013 +0100

    sna/gen5: The cached value of the pipelined pointers key requires 32-bits
    
    Storing only the low 16-bits of the key for the pipelined state meant
    that we forced an update with every new drawing op - with the side
    effect of flushing the render cache.
    
    Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=67157
    Signed-off-by: Chris Wilson <chris at chris-wilson.co.uk>

diff --git a/src/sna/gen5_render.c b/src/sna/gen5_render.c
index 557013e..ef9d7f4 100644
--- a/src/sna/gen5_render.c
+++ b/src/sna/gen5_render.c
@@ -844,12 +844,15 @@ gen5_emit_pipelined_pointers(struct sna *sna,
 			    kernel);
 	bp = gen5_get_blend(blend, op->has_component_alpha, op->dst.format);
 
-	DBG(("%s: sp=%d, bp=%d\n", __FUNCTION__, sp, bp));
 	key = sp | (uint32_t)bp << 16 | (op->mask.bo != NULL) << 31;
+	DBG(("%s: sp=%d, bp=%d, key=%08x (current sp=%d, bp=%d, key=%08x)\n",
+	     __FUNCTION__, sp, bp, key,
+	     sna->render_state.gen5.last_pipelined_pointers & 0xffff,
+	     (sna->render_state.gen5.last_pipelined_pointers >> 16) & 0x7fff,
+	     sna->render_state.gen5.last_pipelined_pointers));
 	if (key == sna->render_state.gen5.last_pipelined_pointers)
 		return false;
 
-
 	OUT_BATCH(GEN5_3DSTATE_PIPELINED_POINTERS | 5);
 	OUT_BATCH(sna->render_state.gen5.vs);
 	OUT_BATCH(GEN5_GS_DISABLE); /* passthrough */
@@ -858,8 +861,11 @@ gen5_emit_pipelined_pointers(struct sna *sna,
 	OUT_BATCH(sna->render_state.gen5.wm + sp);
 	OUT_BATCH(sna->render_state.gen5.cc + bp);
 
-	bp = (sna->render_state.gen5.last_pipelined_pointers & 0x7fff0000) != (bp << 16);
+	bp = (sna->render_state.gen5.last_pipelined_pointers & 0x7fff0000) != ((uint32_t)bp << 16);
 	sna->render_state.gen5.last_pipelined_pointers = key;
+
+	gen5_emit_urb(sna);
+
 	return bp;
 }
 
@@ -1029,7 +1035,8 @@ gen5_emit_state(struct sna *sna,
 		offset &= ~1;
 	gen5_emit_binding_table(sna, offset & ~1);
 	if (gen5_emit_pipelined_pointers(sna, op, op->op, op->u.gen5.wm_kernel)){
-		gen5_emit_urb(sna);
+		DBG(("%s: changed blend state, flush required? %d\n",
+		     __FUNCTION__, (offset & 1) && op->op > PictOpSrc));
 		flush = (offset & 1) && op->op > PictOpSrc;
 	}
 	gen5_emit_vertex_elements(sna, op);
@@ -1043,8 +1050,10 @@ gen5_emit_state(struct sna *sna,
 		kgem_bo_mark_dirty(op->dst.bo);
 		flush = false;
 	}
-	if (flush)
+	if (flush) {
+		DBG(("%s: forcing flush\n", __FUNCTION__));
 		gen5_emit_pipe_flush(sna);
+	}
 }
 
 static void gen5_bind_surfaces(struct sna *sna,
diff --git a/src/sna/sna_render.h b/src/sna/sna_render.h
index 2636394..86df2d0 100644
--- a/src/sna/sna_render.h
+++ b/src/sna/sna_render.h
@@ -391,10 +391,10 @@ struct gen5_render_state {
 	int ve_id;
 	uint32_t drawrect_offset;
 	uint32_t drawrect_limit;
+	uint32_t last_pipelined_pointers;
 	uint16_t last_primitive;
 	int16_t floats_per_vertex;
 	uint16_t surface_table;
-	uint16_t last_pipelined_pointers;
 
 	bool needs_invariant;
 };