xf86-video-intel: src/sna/sna_render.c

[Chris Wilson]

 src/sna/sna_render.c |    3 +++
 1 file changed, 3 insertions(+)

New commits:
commit 42a6b25817985e22e7d462be87fbd97973d96a29
Author: Chris Wilson <chris at chris-wilson.co.uk>
Date:   Sat Feb 9 15:30:58 2013 +0000

    sna: Fix alignment of the base of partial buffers for pre-G33 chipsets
    
    The older chipsets have much more restrictive alignment rules for the
    base address of tiled but unfenced objects.
    
    Bugzilla: https://bugs.launchpad.net/ubuntu/+source/xserver-xorg-video-intel/+bug/1120108
    Signed-off-by: Chris Wilson <chris at chris-wilson.co.uk>

diff --git a/src/sna/sna_render.c b/src/sna/sna_render.c
index 697b802..69ac21c 100644
--- a/src/sna/sna_render.c
+++ b/src/sna/sna_render.c
@@ -899,6 +899,9 @@ sna_render_pixmap_partial(struct sna *sna,
 		DBG(("%s: tile size for tiling %d: %dx%d, size=%d\n",
 		     __FUNCTION__, bo->tiling, tile_width, tile_height, tile_size));
 
+		if (sna->kgem.gen < 033)
+			tile_width = bo->pitch;
+
 		/* Ensure we align to an even tile row */
 		box.y1 = box.y1 & ~(2*tile_height - 1);
 		box.y2 = ALIGN(box.y2, 2*tile_height);