xf86-video-intel: 5 commits - src/i915_pciids.h src/intel_module.c src/render_program/exa_wm_src_affine.g8b src/render_program/exa_wm_src_sample_argb.g8b src/render_program/exa_wm_src_sample_planar.g8b src/render_program/exa_wm_write.g8b src/render_program/exa_wm_yuv_rgb.g8b src/render_program/Makefile.am src/sna/gen4_vertex.c src/sna/gen8_eu.c src/sna/gen8_eu.h src/sna/gen8_render.c src/sna/gen8_render.h src/sna/gen8_vertex.c src/sna/gen8_vertex.h src/sna/kgem.c src/sna/Makefile.am src/sna/sna_accel.c src/sna/sna_display.c src/sna/sna.h src/sna/sna_render.h src/sna/sna_render_inline.h
Chris Wilson
ickle at kemper.freedesktop.org
Wed Dec 11 13:51:18 PST 2013
src/i915_pciids.h | 25
src/intel_module.c | 7
src/render_program/Makefile.am | 23
src/render_program/exa_wm_src_affine.g8b | 4
src/render_program/exa_wm_src_sample_argb.g8b | 3
src/render_program/exa_wm_src_sample_planar.g8b | 5
src/render_program/exa_wm_write.g8b | 17
src/render_program/exa_wm_yuv_rgb.g8b | 12
src/sna/Makefile.am | 6
src/sna/gen4_vertex.c | 2
src/sna/gen8_eu.c | 1379 ++++++++
src/sna/gen8_eu.h | 19
src/sna/gen8_render.c | 3910 ++++++++++++++++++++++++
src/sna/gen8_render.h | 1132 ++++++
src/sna/gen8_vertex.c | 297 +
src/sna/gen8_vertex.h | 14
src/sna/kgem.c | 2
src/sna/sna.h | 1
src/sna/sna_accel.c | 4
src/sna/sna_display.c | 3
src/sna/sna_render.h | 56
src/sna/sna_render_inline.h | 8
22 files changed, 6917 insertions(+), 12 deletions(-)
New commits:
commit 7c62925ba7f18f55ee34b946bddba84a07b83985
Author: Chris Wilson <chris at chris-wilson.co.uk>
Date: Wed Dec 11 21:30:06 2013 +0000
sna: Remove unused variable
sna_display.c: In function 'sna_crtc_redisplay__fallback':
sna_display.c:4104:19: warning: unused variable 'sna_crtc' [-Wunused-variable]
struct sna_crtc *sna_crtc = to_sna_crtc(crtc);
Signed-off-by: Chris Wilson <chris at chris-wilson.co.uk>
diff --git a/src/sna/sna_display.c b/src/sna/sna_display.c
index 44e0feb..15e32df 100644
--- a/src/sna/sna_display.c
+++ b/src/sna/sna_display.c
@@ -4101,7 +4101,6 @@ static void
sna_crtc_redisplay__fallback(xf86CrtcPtr crtc, RegionPtr region, struct kgem_bo *bo)
{
struct sna *sna = to_sna(crtc->scrn);
- struct sna_crtc *sna_crtc = to_sna_crtc(crtc);
ScreenPtr screen = sna->scrn->pScreen;
PictFormatPtr format;
PicturePtr src, dst;
commit 7e76f21a4d9d8f5424c257e6e7686d5bb0bb6cf7
Author: Chris Wilson <chris at chris-wilson.co.uk>
Date: Mon Jul 22 18:56:03 2013 +0100
intel: Recognise gen8
Assign gen=8 to the Broadwell PCI IDs, no marketing names are known at
this point in time.
Signed-off-by: Chris Wilson <chris at chris-wilson.co.uk>
diff --git a/src/intel_module.c b/src/intel_module.c
index d739aa7..fb8734a 100644
--- a/src/intel_module.c
+++ b/src/intel_module.c
@@ -110,6 +110,10 @@ static const struct intel_device_info intel_haswell_info = {
.gen = 075,
};
+static const struct intel_device_info intel_broadwell_info = {
+ .gen = 0100,
+};
+
static const SymTabRec intel_chipsets[] = {
{PCI_CHIP_I810, "i810"},
{PCI_CHIP_I810_DC100, "i810-dc100"},
@@ -262,6 +266,9 @@ static const struct pci_id_match intel_device_match[] = {
INTEL_VLV_D_IDS(&intel_valleyview_info),
INTEL_VLV_M_IDS(&intel_valleyview_info),
+ INTEL_BDW_D_IDS(&intel_broadwell_info),
+ INTEL_BDW_M_IDS(&intel_broadwell_info),
+
INTEL_VGA_DEVICE(PCI_MATCH_ANY, &intel_generic_info),
#endif
commit f7d1c2b8d1883280e7916bb4473ff6436b186950
Author: Chris Wilson <chris at chris-wilson.co.uk>
Date: Tue Jul 23 08:17:58 2013 +0100
sna: Enable scanline waits for Broadwell
Broadwell uses the same mechanism as Haswell for vsync.
Signed-off-by: Chris Wilson <chris at chris-wilson.co.uk>
diff --git a/src/sna/sna_display.c b/src/sna/sna_display.c
index e4dca71..44e0feb 100644
--- a/src/sna/sna_display.c
+++ b/src/sna/sna_display.c
@@ -3977,7 +3977,7 @@ sna_wait_for_scanline(struct sna *sna,
DBG(("%s: pipe=%d, y1=%d, y2=%d, full_height?=%d\n",
__FUNCTION__, pipe, y1, y2, full_height));
- if (sna->kgem.gen >= 0100)
+ if (sna->kgem.gen >= 0110)
ret = false;
else if (sna->kgem.gen >= 075)
ret = sna_emit_wait_for_scanline_hsw(sna, crtc, pipe, y1, y2, full_height);
commit e017542d10e875260e3eef1b0369f4ea106df0f5
Author: Chris Wilson <chris at chris-wilson.co.uk>
Date: Thu Dec 6 22:11:32 2012 +0000
sna/gen8: Initial backend for Broadwell
Should match the functionality of the earlier generations, but untuned.
Signed-off-by: Chris Wilson <chris at chris-wilson.co.uk>
diff --git a/src/render_program/Makefile.am b/src/render_program/Makefile.am
index 1298625..9d36787 100644
--- a/src/render_program/Makefile.am
+++ b/src/render_program/Makefile.am
@@ -174,6 +174,14 @@ INTEL_G7B = \
exa_wm_yuv_rgb.g7b \
$(NULL)
+INTEL_G8B = \
+ exa_wm_src_affine.g8b \
+ exa_wm_src_sample_argb.g8b \
+ exa_wm_src_sample_planar.g8b \
+ exa_wm_write.g8b \
+ exa_wm_yuv_rgb.g8b \
+ $(NULL)
+
EXTRA_DIST = \
$(INTEL_G4A) \
$(INTEL_G4I) \
@@ -185,11 +193,12 @@ EXTRA_DIST = \
$(INTEL_G6B) \
$(INTEL_G6I) \
$(INTEL_G7A) \
- $(INTEL_G7B)
+ $(INTEL_G7B) \
+ $(INTEL_G8B)
if HAVE_GEN4ASM
-SUFFIXES = .g4a .g4b .g5a .g5b .g6a .g6b .g7a .g7b
+SUFFIXES = .g4a .g4b .g5a .g5b .g6a .g6b .g7a .g7b .g8b
.g4a.g4b:
$(AM_V_GEN)m4 -I$(srcdir) -s $< > $*.g4m && @INTEL_GEN4ASM@ -o $@ $*.g4m && @INTEL_GEN4ASM@ -g 5 -o $@.gen5 $*.g4m && rm $*.g4m
@@ -201,17 +210,17 @@ SUFFIXES = .g4a .g4b .g5a .g5b .g6a .g6b .g7a .g7b
.g7a.g7b:
$(AM_V_GEN)m4 -I$(srcdir) -s $< > $*.g7m && @INTEL_GEN4ASM@ -g 7 -o $@ $*.g7m && rm $*.g7m
+.g7a.g8b:
+ $(AM_V_GEN)m4 -I$(srcdir) -s $< > $*.g8m && @INTEL_GEN4ASM@ -g 8 -o $@ $*.g8m && rm $*.g8m
$(INTEL_G4B): $(INTEL_GEN4ASM) $(INTEL_G4I)
$(INTEL_G5B): $(INTEL_GEN4ASM) $(INTEL_G4I)
$(INTEL_G6B): $(INTEL_GEN4ASM) $(INTEL_G4I) $(INTEL_G6I)
$(INTEL_G7B): $(INTEL_GEN4ASM) $(INTEL_G4I) $(INTEL_G6I)
+$(INTEL_G8B): $(INTEL_GEN4ASM) $(INTEL_G4I) $(INTEL_G6I)
-BUILT_SOURCES= $(INTEL_G4B) $(INTEL_G5B) $(INTEL_G6B) $(INTEL_G7B)
+BUILT_SOURCES=$(INTEL_G4B) $(INTEL_G4B_GEN5) $(INTEL_G5B) $(INTEL_G6B) $(INTEL_G7B) $(INTEL_G8B)
clean-local:
- -rm -f $(INTEL_G4B) $(INTEL_G4B_GEN5)
- -rm -f $(INTEL_G5B)
- -rm -f $(INTEL_G6B)
- -rm -f $(INTEL_G7B)
+ -rm -f $(BUILT_SOURCES)
endif
diff --git a/src/render_program/exa_wm_src_affine.g8b b/src/render_program/exa_wm_src_affine.g8b
new file mode 100644
index 0000000..2a55d70
--- /dev/null
+++ b/src/render_program/exa_wm_src_affine.g8b
@@ -0,0 +1,4 @@
+ { 0x0060005a, 0x28403ae8, 0x3a0000c0, 0x008d0040 },
+ { 0x0060005a, 0x28603ae8, 0x3a0000c0, 0x008d0080 },
+ { 0x0060005a, 0x28803ae8, 0x3a0000d0, 0x008d0040 },
+ { 0x0060005a, 0x28a03ae8, 0x3a0000d0, 0x008d0080 },
diff --git a/src/render_program/exa_wm_src_sample_argb.g8b b/src/render_program/exa_wm_src_sample_argb.g8b
new file mode 100644
index 0000000..2349b3d
--- /dev/null
+++ b/src/render_program/exa_wm_src_sample_argb.g8b
@@ -0,0 +1,3 @@
+ { 0x00000001, 0x2008060c, 0x00000000, 0x00000000 },
+ { 0x00600001, 0x28200208, 0x008d0000, 0x00000000 },
+ { 0x02800031, 0x21c00a48, 0x0e000820, 0x0a8c0001 },
diff --git a/src/render_program/exa_wm_src_sample_planar.g8b b/src/render_program/exa_wm_src_sample_planar.g8b
new file mode 100644
index 0000000..3a5e25c
--- /dev/null
+++ b/src/render_program/exa_wm_src_sample_planar.g8b
@@ -0,0 +1,5 @@
+ { 0x00000001, 0x2008060c, 0x00000000, 0x0000e000 },
+ { 0x00600001, 0x28200208, 0x008d0000, 0x00000000 },
+ { 0x02800031, 0x22000a48, 0x0e000820, 0x0a2c0001 },
+ { 0x02800031, 0x21c00a48, 0x0e000820, 0x0a2c0003 },
+ { 0x02800031, 0x22400a48, 0x0e000820, 0x0a2c0005 },
diff --git a/src/render_program/exa_wm_write.g8b b/src/render_program/exa_wm_write.g8b
new file mode 100644
index 0000000..6943307
--- /dev/null
+++ b/src/render_program/exa_wm_write.g8b
@@ -0,0 +1,17 @@
+ { 0x00600001, 0x28403ae8, 0x008d01c0, 0x00000000 },
+ { 0x00600001, 0x28603ae8, 0x008d01e0, 0x00000000 },
+ { 0x00600001, 0x28803ae8, 0x008d0200, 0x00000000 },
+ { 0x00600001, 0x28a03ae8, 0x008d0220, 0x00000000 },
+ { 0x00600001, 0x28c03ae8, 0x008d0240, 0x00000000 },
+ { 0x00600001, 0x28e03ae8, 0x008d0260, 0x00000000 },
+ { 0x00600001, 0x29003ae8, 0x008d0280, 0x00000000 },
+ { 0x00600001, 0x29203ae8, 0x008d02a0, 0x00000000 },
+ { 0x05800031, 0x24000a40, 0x0e000840, 0x90031000 },
+ { 0x0000007e, 0x00000000, 0x00000000, 0x00000000 },
+ { 0x0000007e, 0x00000000, 0x00000000, 0x00000000 },
+ { 0x0000007e, 0x00000000, 0x00000000, 0x00000000 },
+ { 0x0000007e, 0x00000000, 0x00000000, 0x00000000 },
+ { 0x0000007e, 0x00000000, 0x00000000, 0x00000000 },
+ { 0x0000007e, 0x00000000, 0x00000000, 0x00000000 },
+ { 0x0000007e, 0x00000000, 0x00000000, 0x00000000 },
+ { 0x0000007e, 0x00000000, 0x00000000, 0x00000000 },
diff --git a/src/render_program/exa_wm_yuv_rgb.g8b b/src/render_program/exa_wm_yuv_rgb.g8b
new file mode 100644
index 0000000..0da262c
--- /dev/null
+++ b/src/render_program/exa_wm_yuv_rgb.g8b
@@ -0,0 +1,12 @@
+ { 0x00800040, 0x23003ae8, 0x3e8d0200, 0xbd808081 },
+ { 0x00800041, 0x23003ae8, 0x3e8d0300, 0x3f94fdf4 },
+ { 0x00800040, 0x22c03ae8, 0x3e8d01c0, 0xbf008084 },
+ { 0x00800040, 0x23403ae8, 0x3e8d0240, 0xbf008084 },
+ { 0x00800001, 0x24003ae0, 0x008d0300, 0x00000000 },
+ { 0x80800048, 0x21c03ae8, 0x3e8d02c0, 0x3fcc49ba },
+ { 0x00800001, 0x24003ae0, 0x008d0300, 0x00000000 },
+ { 0x00800048, 0x24003ae0, 0x3e8d02c0, 0xbf5020c5 },
+ { 0x80800048, 0x22003ae8, 0x3e8d0340, 0xbec8b439 },
+ { 0x00800001, 0x24003ae0, 0x008d0300, 0x00000000 },
+ { 0x80800048, 0x22403ae8, 0x3e8d0340, 0x40011687 },
+ { 0x00800001, 0x22803ee8, 0x38000000, 0x3f800000 },
diff --git a/src/sna/Makefile.am b/src/sna/Makefile.am
index 3377b9c..16679c1 100644
--- a/src/sna/Makefile.am
+++ b/src/sna/Makefile.am
@@ -100,6 +100,12 @@ libsna_la_SOURCES = \
gen6_render.h \
gen7_render.c \
gen7_render.h \
+ gen8_eu.c \
+ gen8_eu.h \
+ gen8_render.c \
+ gen8_render.h \
+ gen8_vertex.c \
+ gen8_vertex.h \
$(NULL)
if DRI2
diff --git a/src/sna/gen4_vertex.c b/src/sna/gen4_vertex.c
index 0585c4c..1ea10b0 100644
--- a/src/sna/gen4_vertex.c
+++ b/src/sna/gen4_vertex.c
@@ -88,6 +88,7 @@ int gen4_vertex_finish(struct sna *sna)
assert(sna->render.vertex_offset == 0);
assert(sna->render.vertex_used);
assert(sna->render.vertex_used <= sna->render.vertex_size);
+ assert(sna->render.nvertex_reloc);
sna_vertex_wait__locked(&sna->render);
@@ -125,7 +126,6 @@ int gen4_vertex_finish(struct sna *sna)
}
}
-
size = 256*1024;
assert(!sna->render.active);
sna->render.vertices = NULL;
diff --git a/src/sna/gen8_eu.c b/src/sna/gen8_eu.c
new file mode 100644
index 0000000..7b6d887
--- /dev/null
+++ b/src/sna/gen8_eu.c
@@ -0,0 +1,1379 @@
+/*
+ * Copyright © 2013 Intel Corporation
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
+ */
+
+#ifdef HAVE_CONFIG_H
+#include "config.h"
+#endif
+
+#include <string.h>
+
+#include "compiler.h"
+#include "brw/brw.h"
+#include "gen8_eu.h"
+
+#ifndef ARRAY_SIZE
+#define ARRAY_SIZE(a) (sizeof(a)/sizeof(a[0]))
+#endif
+
+/* EU ISA */
+
+#define MRF_HACK_START 111
+
+struct gen8_instruction {
+ uint32_t data[4];
+};
+
+static inline unsigned
+__gen8_mask(unsigned high, unsigned low)
+{
+ assert(high >= low);
+ return (1 << (high - low + 1)) - 1;
+}
+
+/**
+ * Fetch a set of contiguous bits from the instruction.
+ *
+ * Bits indexes range from 0..127; fields may not cross 32-bit boundaries.
+ */
+static inline unsigned
+__gen8_bits(struct gen8_instruction *insn, unsigned high, unsigned low)
+{
+ /* We assume the field doesn't cross 32-bit boundaries. */
+ const unsigned word = high / 32;
+
+ assert(word == low / 32);
+
+ high %= 32;
+ low %= 32;
+
+ return (insn->data[word] >> low) & __gen8_mask(high, low);
+}
+
+/**
+ * Set bits in the instruction, with proper shifting and masking.
+ *
+ * Bits indexes range from 0..127; fields may not cross 32-bit boundaries.
+ */
+static inline void
+__gen8_set_bits(struct gen8_instruction *insn,
+ unsigned high,
+ unsigned low,
+ unsigned value)
+{
+ const unsigned word = high / 32;
+ unsigned mask;
+
+ assert(word == low / 32);
+
+ high %= 32;
+ low %= 32;
+ assert(value < __gen8_mask(high, low) + 1);
+
+ mask = __gen8_mask(high, low) << low;
+ insn->data[word] &= ~mask;
+ insn->data[word] |= (value << low) & mask;
+
+ assert(__gen8_bits(insn, 32*word+high, 32*word+low) == value);
+}
+
+#define F(name, high, low) \
+static inline void __gen8_set_##name(struct gen8_instruction *insn, unsigned v) \
+{ \
+ __gen8_set_bits(insn, high, low, v); \
+} \
+static inline unsigned __gen8_##name(struct gen8_instruction *insn) \
+{ \
+ return __gen8_bits(insn, high, low); \
+}
+
+/**
+* Direct addressing only:
+* @{
+*/
+F(src1_da_reg_nr, 108, 101);
+F(src0_da_reg_nr, 76, 69);
+F(dst_da1_hstride, 62, 61);
+F(dst_da_reg_nr, 60, 53);
+F(dst_da16_subreg_nr, 52, 52);
+F(dst_da1_subreg_nr, 52, 48);
+F(da16_writemask, 51, 48); /* Dst.ChanEn */
+/** @} */
+
+F(src1_vert_stride, 120, 117)
+F(src1_da1_width, 116, 114)
+F(src1_da16_swiz_w, 115, 114)
+F(src1_da16_swiz_z, 113, 112)
+F(src1_da1_hstride, 113, 112)
+F(src1_address_mode, 111, 111)
+/** Src1.SrcMod @{ */
+F(src1_negate, 110, 110)
+F(src1_abs, 109, 109)
+/** @} */
+F(src1_da16_subreg_nr, 100, 100)
+F(src1_da1_subreg_nr, 100, 96)
+F(src1_da16_swiz_y, 99, 98)
+F(src1_da16_swiz_x, 97, 96)
+F(src1_reg_type, 94, 91)
+F(src1_reg_file, 90, 89)
+F(src0_vert_stride, 88, 85)
+F(src0_da1_width, 84, 82)
+F(src0_da16_swiz_w, 83, 82)
+F(src0_da16_swiz_z, 81, 80)
+F(src0_da1_hstride, 81, 80)
+F(src0_address_mode, 79, 79)
+/** Src0.SrcMod @{ */
+F(src0_negate, 78, 78)
+F(src0_abs, 77, 77)
+/** @} */
+F(src0_da16_subreg_nr, 68, 68)
+F(src0_da1_subreg_nr, 68, 64)
+F(src0_da16_swiz_y, 67, 66)
+F(src0_da16_swiz_x, 65, 64)
+F(dst_address_mode, 63, 63)
+F(src0_reg_type, 46, 43)
+F(src0_reg_file, 42, 41)
+F(dst_reg_type, 40, 37)
+F(dst_reg_file, 36, 35)
+F(mask_control, 34, 34)
+F(flag_reg_nr, 33, 33)
+F(flag_subreg_nr, 32, 32)
+F(saturate, 31, 31)
+F(branch_control, 30, 30)
+F(debug_control, 30, 30)
+F(cmpt_control, 29, 29)
+F(acc_wr_control, 28, 28)
+F(cond_modifier, 27, 24)
+F(exec_size, 23, 21)
+F(pred_inv, 20, 20)
+F(pred_control, 19, 16)
+F(thread_control, 15, 14)
+F(qtr_control, 13, 12)
+F(nib_control, 11, 11)
+F(dep_control, 10, 9)
+F(access_mode, 8, 8)
+/* Bit 7 is Reserved (for future Opcode expansion) */
+F(opcode, 6, 0)
+
+/**
+* Three-source instructions:
+* @{
+*/
+F(src2_3src_reg_nr, 125, 118)
+F(src2_3src_subreg_nr, 117, 115)
+F(src2_3src_swizzle, 114, 107)
+F(src2_3src_rep_ctrl, 106, 106)
+F(src1_3src_reg_nr, 104, 97)
+F(src1_3src_subreg_hi, 96, 96)
+F(src1_3src_subreg_lo, 95, 94)
+F(src1_3src_swizzle, 93, 86)
+F(src1_3src_rep_ctrl, 85, 85)
+F(src0_3src_reg_nr, 83, 76)
+F(src0_3src_subreg_nr, 75, 73)
+F(src0_3src_swizzle, 72, 65)
+F(src0_3src_rep_ctrl, 64, 64)
+F(dst_3src_reg_nr, 63, 56)
+F(dst_3src_subreg_nr, 55, 53)
+F(dst_3src_writemask, 52, 49)
+F(dst_3src_type, 48, 46)
+F(src_3src_type, 45, 43)
+F(src2_3src_negate, 42, 42)
+F(src2_3src_abs, 41, 41)
+F(src1_3src_negate, 40, 40)
+F(src1_3src_abs, 39, 39)
+F(src0_3src_negate, 38, 38)
+F(src0_3src_abs, 37, 37)
+/** @} */
+
+/**
+* Fields for SEND messages:
+* @{
+*/
+F(eot, 127, 127)
+F(mlen, 124, 121)
+F(rlen, 120, 116)
+F(header_present, 115, 115)
+F(function_control, 114, 96)
+F(sfid, 27, 24)
+F(math_function, 27, 24)
+/** @} */
+
+/**
+* URB message function control bits:
+* @{
+*/
+F(urb_per_slot_offset, 113, 113)
+F(urb_interleave, 111, 111)
+F(urb_global_offset, 110, 100)
+F(urb_opcode, 99, 96)
+/** @} */
+
+/**
+* Sampler message function control bits:
+* @{
+*/
+F(sampler_simd_mode, 114, 113)
+F(sampler_msg_type, 112, 108)
+F(sampler, 107, 104)
+F(binding_table_index, 103, 96)
+/** @} */
+
+/**
+ * Data port message function control bits:
+ * @ {
+ */
+F(dp_category, 114, 114)
+F(dp_message_type, 113, 110)
+F(dp_message_control, 109, 104)
+F(dp_binding_table_index, 103, 96)
+/** @} */
+
+/**
+ * Thread Spawn message function control bits:
+ * @ {
+ */
+F(ts_resource_select, 100, 100)
+F(ts_request_type, 97, 97)
+F(ts_opcode, 96, 96)
+/** @} */
+
+/**
+ * Video Motion Estimation message function control bits:
+ * @ {
+ */
+F(vme_message_type, 110, 109)
+F(vme_binding_table_index, 103, 96)
+/** @} */
+
+/**
+ * Check & Refinement Engine message function control bits:
+ * @ {
+ */
+F(cre_message_type, 110, 109)
+F(cre_binding_table_index, 103, 96)
+/** @} */
+
+#undef F
+
+/**
+* Flow control instruction bits:
+* @{
+*/
+static inline unsigned __gen8_uip(struct gen8_instruction *insn)
+{
+ return insn->data[2];
+}
+
+static inline void __gen8_set_uip(struct gen8_instruction *insn, unsigned uip)
+{
+ insn->data[2] = uip;
+}
+
+static inline unsigned __gen8_jip(struct gen8_instruction *insn)
+{
+ return insn->data[3];
+}
+
+static inline void __gen8_set_jip(struct gen8_instruction *insn, unsigned jip)
+{
+ insn->data[3] = jip;
+}
+/** @} */
+
+static inline int __gen8_src1_imm_d(struct gen8_instruction *insn)
+{
+ return insn->data[3];
+}
+
+static inline unsigned __gen8_src1_imm_ud(struct gen8_instruction *insn)
+{
+ return insn->data[3];
+}
+
+static inline float __gen8_src1_imm_f(struct gen8_instruction *insn)
+{
+ union {
+ uint32_t u;
+ float f;
+ } ft = { insn->data[3] };
+ return ft.f;
+}
+
+static void
+__gen8_set_dst(struct brw_compile *p,
+ struct gen8_instruction *inst,
+ struct brw_reg reg)
+{
+ /* MRFs haven't existed since Gen7, so we better not be using them. */
+ if (reg.file == BRW_MESSAGE_REGISTER_FILE) {
+ reg.file = BRW_GENERAL_REGISTER_FILE;
+ reg.nr += MRF_HACK_START;
+ }
+
+ assert(reg.file != BRW_MESSAGE_REGISTER_FILE);
+
+ if (reg.file == BRW_GENERAL_REGISTER_FILE)
+ assert(reg.nr < BRW_MAX_GRF);
+
+ __gen8_set_dst_reg_file(inst, reg.file);
+ __gen8_set_dst_reg_type(inst, reg.type);
+
+ assert(reg.address_mode == BRW_ADDRESS_DIRECT);
+
+ __gen8_set_dst_da_reg_nr(inst, reg.nr);
+
+ if (__gen8_access_mode(inst) == BRW_ALIGN_1) {
+ /* Set Dst.SubRegNum[4:0] */
+ __gen8_set_dst_da1_subreg_nr(inst, reg.subnr);
+
+ /* Set Dst.HorzStride */
+ if (reg.hstride == BRW_HORIZONTAL_STRIDE_0)
+ reg.hstride = BRW_HORIZONTAL_STRIDE_1;
+ __gen8_set_dst_da1_hstride(inst, reg.hstride);
+ } else {
+ /* Align16 SubRegNum only has a single bit (bit 4; bits 3:0 MBZ). */
+ assert(reg.subnr == 0 || reg.subnr == 16);
+ __gen8_set_dst_da16_subreg_nr(inst, reg.subnr >> 4);
+ __gen8_set_da16_writemask(inst, reg.dw1.bits.writemask);
+ }
+
+#if 1
+ if (reg.width == BRW_WIDTH_8 && p->compressed)
+ __gen8_set_exec_size(inst, BRW_EXECUTE_16);
+ else
+ __gen8_set_exec_size(inst, reg.width);
+#else
+ if (reg.width < BRW_EXECUTE_8)
+ __gen8_set_exec_size(inst, reg.width);
+#endif
+}
+
+static void
+__gen8_validate_reg(struct gen8_instruction *inst, struct brw_reg reg)
+{
+ int hstride_for_reg[] = {0, 1, 2, 4};
+ int vstride_for_reg[] = {0, 1, 2, 4, 8, 16, 32, 64, 128, 256};
+ int width_for_reg[] = {1, 2, 4, 8, 16};
+ int execsize_for_reg[] = {1, 2, 4, 8, 16};
+ int width, hstride, vstride, execsize;
+
+ if (reg.file == BRW_IMMEDIATE_VALUE) {
+ /* TODO: check immediate vectors */
+ return;
+ }
+
+ if (reg.file == BRW_ARCHITECTURE_REGISTER_FILE)
+ return;
+
+ assert(reg.hstride >= 0 && reg.hstride < ARRAY_SIZE(hstride_for_reg));
+ hstride = hstride_for_reg[reg.hstride];
+
+ if (reg.vstride == 0xf) {
+ vstride = -1;
+ } else {
+ assert(reg.vstride >= 0 && reg.vstride < ARRAY_SIZE(vstride_for_reg));
+ vstride = vstride_for_reg[reg.vstride];
+ }
+
+ assert(reg.width >= 0 && reg.width < ARRAY_SIZE(width_for_reg));
+ width = width_for_reg[reg.width];
+
+ assert(__gen8_exec_size(inst) >= 0 &&
+ __gen8_exec_size(inst) < ARRAY_SIZE(execsize_for_reg));
+ execsize = execsize_for_reg[__gen8_exec_size(inst)];
+
+ /* Restrictions from 3.3.10: Register Region Restrictions. */
+ /* 3. */
+ assert(execsize >= width);
+
+ /* 4. */
+ if (execsize == width && hstride != 0) {
+ assert(vstride == -1 || vstride == width * hstride);
+ }
+
+ /* 5. */
+ if (execsize == width && hstride == 0) {
+ /* no restriction on vstride. */
+ }
+
+ /* 6. */
+ if (width == 1) {
+ assert(hstride == 0);
+ }
+
+ /* 7. */
+ if (execsize == 1 && width == 1) {
+ assert(hstride == 0);
+ assert(vstride == 0);
+ }
+
+ /* 8. */
+ if (vstride == 0 && hstride == 0) {
+ assert(width == 1);
+ }
+
+ /* 10. Check destination issues. */
+}
+
+static void
+__gen8_set_src0(struct gen8_instruction *inst, struct brw_reg reg)
+{
+ /* MRFs haven't existed since Gen7, so we better not be using them. */
+ if (reg.file == BRW_MESSAGE_REGISTER_FILE) {
+ reg.file = BRW_GENERAL_REGISTER_FILE;
+ reg.nr += MRF_HACK_START;
+ }
+
+ if (reg.file == BRW_GENERAL_REGISTER_FILE)
+ assert(reg.nr < BRW_MAX_GRF);
+
+ __gen8_validate_reg(inst, reg);
+
+ __gen8_set_src0_reg_file(inst, reg.file);
+ __gen8_set_src0_reg_type(inst, reg.type);
+ __gen8_set_src0_abs(inst, reg.abs);
+ __gen8_set_src0_negate(inst, reg.negate);
+
+ assert(reg.address_mode == BRW_ADDRESS_DIRECT);
+
+ if (reg.file == BRW_IMMEDIATE_VALUE) {
+ inst->data[3] = reg.dw1.ud;
+
+ /* Required to set some fields in src1 as well: */
+ __gen8_set_src1_reg_file(inst, 0); /* arf */
+ __gen8_set_src1_reg_type(inst, reg.type);
+ } else {
+ __gen8_set_src0_da_reg_nr(inst, reg.nr);
+
+ if (__gen8_access_mode(inst) == BRW_ALIGN_1) {
+ /* Set Src0.SubRegNum[4:0] */
+ __gen8_set_src0_da1_subreg_nr(inst, reg.subnr);
+
+ if (reg.width == BRW_WIDTH_1 &&
+ __gen8_exec_size(inst) == BRW_EXECUTE_1) {
+ __gen8_set_src0_da1_hstride(inst, BRW_HORIZONTAL_STRIDE_0);
+ __gen8_set_src0_vert_stride(inst, BRW_VERTICAL_STRIDE_0);
+ } else {
+ __gen8_set_src0_da1_hstride(inst, reg.hstride);
+ __gen8_set_src0_vert_stride(inst, reg.vstride);
+ }
+ __gen8_set_src0_da1_width(inst, reg.width);
+ } else {
+ /* Align16 SubRegNum only has a single bit (bit 4; bits 3:0 MBZ). */
+ assert(reg.subnr == 0 || reg.subnr == 16);
+ __gen8_set_src0_da16_subreg_nr(inst, reg.subnr >> 4);
+
+ __gen8_set_src0_da16_swiz_x(inst,
+ BRW_GET_SWZ(reg.dw1.bits.swizzle,
+ BRW_CHANNEL_X));
+ __gen8_set_src0_da16_swiz_y(inst,
+ BRW_GET_SWZ(reg.dw1.bits.swizzle,
+ BRW_CHANNEL_Y));
+ __gen8_set_src0_da16_swiz_z(inst,
+ BRW_GET_SWZ(reg.dw1.bits.swizzle,
+ BRW_CHANNEL_Z));
+ __gen8_set_src0_da16_swiz_w(inst,
+ BRW_GET_SWZ(reg.dw1.bits.swizzle,
+ BRW_CHANNEL_W));
+
+ /* This is an oddity of the fact that we're using the same
+ * descriptions for registers in both Align16 and Align1 modes.
+ */
+ if (reg.vstride == BRW_VERTICAL_STRIDE_8)
+ __gen8_set_src0_vert_stride(inst, BRW_VERTICAL_STRIDE_4);
+ else
+ __gen8_set_src0_vert_stride(inst, reg.vstride);
+ }
+ }
+}
+
+static void
+__gen8_set_src1(struct gen8_instruction *inst, struct brw_reg reg)
+{
+ /* MRFs haven't existed since Gen7, so we better not be using them. */
+ if (reg.file == BRW_MESSAGE_REGISTER_FILE) {
+ reg.file = BRW_GENERAL_REGISTER_FILE;
+ reg.nr += MRF_HACK_START;
+ }
+
+ if (reg.file == BRW_GENERAL_REGISTER_FILE)
+ assert(reg.nr < BRW_MAX_GRF);
+
+ __gen8_validate_reg(inst, reg);
+
+ __gen8_set_src1_reg_file(inst, reg.file);
+ __gen8_set_src1_reg_type(inst, reg.type);
+ __gen8_set_src1_abs(inst, reg.abs);
+ __gen8_set_src1_negate(inst, reg.negate);
+
+ /* Only src1 can be an immediate in two-argument instructions. */
+ assert(__gen8_src0_reg_file(inst) != BRW_IMMEDIATE_VALUE);
+
+ assert(reg.address_mode == BRW_ADDRESS_DIRECT);
+
+ if (reg.file == BRW_IMMEDIATE_VALUE) {
+ inst->data[3] = reg.dw1.ud;
+ } else {
+ __gen8_set_src1_da_reg_nr(inst, reg.nr);
+
+ if (__gen8_access_mode(inst) == BRW_ALIGN_1) {
+ /* Set Src0.SubRegNum[4:0] */
+ __gen8_set_src1_da1_subreg_nr(inst, reg.subnr);
+
+ if (reg.width == BRW_WIDTH_1 &&
+ __gen8_exec_size(inst) == BRW_EXECUTE_1) {
+ __gen8_set_src1_da1_hstride(inst, BRW_HORIZONTAL_STRIDE_0);
+ __gen8_set_src1_vert_stride(inst, BRW_VERTICAL_STRIDE_0);
+ } else {
+ __gen8_set_src1_da1_hstride(inst, reg.hstride);
+ __gen8_set_src1_vert_stride(inst, reg.vstride);
+ }
+ __gen8_set_src1_da1_width(inst, reg.width);
+ } else {
+ /* Align16 SubRegNum only has a single bit (bit 4; bits 3:0 MBZ). */
+ assert(reg.subnr == 0 || reg.subnr == 16);
+ __gen8_set_src1_da16_subreg_nr(inst, reg.subnr >> 4);
+
+ __gen8_set_src1_da16_swiz_x(inst,
+ BRW_GET_SWZ(reg.dw1.bits.swizzle,
+ BRW_CHANNEL_X));
+ __gen8_set_src1_da16_swiz_y(inst,
+ BRW_GET_SWZ(reg.dw1.bits.swizzle,
+ BRW_CHANNEL_Y));
+ __gen8_set_src1_da16_swiz_z(inst,
+ BRW_GET_SWZ(reg.dw1.bits.swizzle,
+ BRW_CHANNEL_Z));
+ __gen8_set_src1_da16_swiz_w(inst,
+ BRW_GET_SWZ(reg.dw1.bits.swizzle,
+ BRW_CHANNEL_W));
+
+ /* This is an oddity of the fact that we're using the same
+ * descriptions for registers in both Align16 and Align1 modes.
+ */
+ if (reg.vstride == BRW_VERTICAL_STRIDE_8)
+ __gen8_set_src1_vert_stride(inst, BRW_VERTICAL_STRIDE_4);
+ else
+ __gen8_set_src1_vert_stride(inst, reg.vstride);
+ }
+ }
+}
+
+/**
+ * Set the Message Descriptor and Extended Message Descriptor fields
+ * for SEND messages.
+ *
+ * \note This zeroes out the Function Control bits, so it must be called
+ * \b before filling out any message-specific data. Callers can
+ * choose not to fill in irrelevant bits; they will be zero.
+ */
+static void
+__gen8_set_message_descriptor(struct gen8_instruction *inst,
+ enum brw_message_target sfid,
+ unsigned msg_length,
+ unsigned response_length,
+ bool header_present,
+ bool end_of_thread)
+{
+ __gen8_set_src1(inst, brw_imm_d(0));
+
+ __gen8_set_sfid(inst, sfid);
+ __gen8_set_mlen(inst, msg_length);
+ __gen8_set_rlen(inst, response_length);
+ __gen8_set_header_present(inst, header_present);
+ __gen8_set_eot(inst, end_of_thread);
+}
+
+#if 0
+static void
+__gen8_set_urb_message(struct gen8_instruction *inst,
+ unsigned opcode,
+ unsigned msg_length,
+ unsigned response_length,
+ bool end_of_thread,
+ unsigned offset,
+ bool interleave)
+{
+ __gen8_set_message_descriptor(inst, BRW_SFID_URB, msg_length, response_length,
+ true, end_of_thread);
+ __gen8_set_src0(inst, brw_vec8_grf(MRF_HACK_START + 1, 0));
+ __gen8_set_urb_opcode(inst, 0); /* URB_WRITE_HWORD */
+ __gen8_set_urb_global_offset(inst, offset);
+ __gen8_set_urb_interleave(inst, interleave);
+ /* per_slot_offset = 0 makes it ignore offsets in message header */
+ __gen8_set_urb_per_slot_offset(inst, 0);
+}
+#endif
+
+static void
+__gen8_set_sampler_message(struct gen8_instruction *inst,
+ unsigned binding_table_index,
+ unsigned sampler,
+ unsigned msg_type,
+ unsigned response_length,
+ unsigned msg_length,
+ bool header_present,
+ unsigned simd_mode)
+{
+ __gen8_set_message_descriptor(inst, BRW_SFID_SAMPLER, msg_length,
+ response_length, header_present, false);
+
+ __gen8_set_binding_table_index(inst, binding_table_index);
+ __gen8_set_sampler(inst, sampler);
+ __gen8_set_sampler_msg_type(inst, msg_type);
+ __gen8_set_sampler_simd_mode(inst, simd_mode);
+}
+
+static void
+__gen8_set_dp_message(struct gen8_instruction *inst,
+ enum brw_message_target sfid,
+ unsigned binding_table_index,
+ unsigned msg_type,
+ unsigned msg_control,
+ unsigned mlen,
+ unsigned rlen,
+ bool header_present,
+ bool end_of_thread)
+{
+ /* Binding table index is from 0..255 */
+ assert((binding_table_index & 0xff) == binding_table_index);
+
+ /* Message Type is only 5 bits */
+ assert((msg_type & 0x1f) == msg_type);
+
+ /* Message Control is only 6 bits */
+ assert((msg_control & 0x3f) == msg_control);
+
+ __gen8_set_message_descriptor(inst, sfid, mlen, rlen, header_present,
+ end_of_thread);
+ __gen8_set_function_control(inst,
+ binding_table_index | msg_type << 14 | msg_control << 8);
+}
+
+static inline struct gen8_instruction *
+gen8_next_insn(struct brw_compile *p, int opcode)
+{
+ struct gen8_instruction *insn;
+
+ assert(p->nr_insn + 1 < BRW_EU_MAX_INSN);
+
+ insn = memcpy(&p->store[p->nr_insn++], p->current, sizeof(*insn));
+ __gen8_set_opcode(insn, opcode);
+
+ return insn;
+}
+
+static void gen8_math(struct brw_compile *p,
+ struct brw_reg dst,
+ unsigned function,
+ unsigned saturate,
+ unsigned msg_reg_nr,
+ struct brw_reg src,
+ unsigned data_type,
+ unsigned precision)
+{
+ struct gen8_instruction *insn = gen8_next_insn(p, BRW_OPCODE_MATH);
+
+ assert(dst.file == BRW_GENERAL_REGISTER_FILE);
+ assert(src.file == BRW_GENERAL_REGISTER_FILE);
+
+ assert(dst.hstride == BRW_HORIZONTAL_STRIDE_1);
+ assert(src.hstride == BRW_HORIZONTAL_STRIDE_1);
+
+ /* Source modifiers are ignored for extended math instructions. */
+ assert(!src.negate);
+ assert(!src.abs);
+
+ if (function != BRW_MATH_FUNCTION_INT_DIV_QUOTIENT &&
+ function != BRW_MATH_FUNCTION_INT_DIV_QUOTIENT_AND_REMAINDER) {
+ assert(src.type == BRW_REGISTER_TYPE_F);
+ }
+
+ /* Math is the same ISA format as other opcodes, except that CondModifier
+ * becomes FC[3:0] and ThreadCtrl becomes FC[5:4].
+ */
+ __gen8_set_cond_modifier(insn, function);
+ __gen8_set_saturate(insn, saturate);
+
+ __gen8_set_dst(p, insn, dst);
+ __gen8_set_src0(insn, src);
+ __gen8_set_src1(insn, brw_null_reg());
+}
+
+static inline void gen8_math_invert(struct brw_compile *p,
+ struct brw_reg dst,
+ struct brw_reg src)
+{
+ gen8_math(p,
+ dst,
+ BRW_MATH_FUNCTION_INV,
+ BRW_MATH_SATURATE_NONE,
+ 0,
+ src,
+ BRW_MATH_PRECISION_FULL,
+ BRW_MATH_DATA_VECTOR);
+
+}
+
+/* Helpers for regular instructions: */
+static inline struct gen8_instruction *gen8_alu1(struct brw_compile *p,
+ unsigned opcode,
+ struct brw_reg dst,
+ struct brw_reg src)
+{
+ struct gen8_instruction *insn = gen8_next_insn(p, opcode);
+ __gen8_set_dst(p, insn, dst);
+ __gen8_set_src0(insn, src);
+ return insn;
+}
+
+static inline struct gen8_instruction *gen8_alu2(struct brw_compile *p,
+ unsigned opcode,
+ struct brw_reg dst,
+ struct brw_reg src0,
+ struct brw_reg src1)
+{
+ struct gen8_instruction *insn = gen8_next_insn(p, opcode);
+ __gen8_set_dst(p, insn, dst);
+ __gen8_set_src0(insn, src0);
+ __gen8_set_src1(insn, src1);
+ return insn;
+}
+
+#define ALU1(OP) \
+static inline struct gen8_instruction *gen8_##OP(struct brw_compile *p, \
+ struct brw_reg dst, \
+ struct brw_reg src0) \
+{ \
+ return gen8_alu1(p, BRW_OPCODE_##OP, dst, src0); \
+}
+
+#define ALU2(OP) \
+static inline struct gen8_instruction *gen8_##OP(struct brw_compile *p, \
+ struct brw_reg dst, \
+ struct brw_reg src0, \
+ struct brw_reg src1) \
+{ \
+ return gen8_alu2(p, BRW_OPCODE_##OP, dst, src0, src1); \
+}
+
+static inline struct gen8_instruction *gen8_ADD(struct brw_compile *p,
+ struct brw_reg dst,
+ struct brw_reg src0,
+ struct brw_reg src1)
+{
+ /* 6.2.2: add */
+ if (src0.type == BRW_REGISTER_TYPE_F ||
+ (src0.file == BRW_IMMEDIATE_VALUE &&
+ src0.type == BRW_REGISTER_TYPE_VF)) {
+ assert(src1.type != BRW_REGISTER_TYPE_UD);
+ assert(src1.type != BRW_REGISTER_TYPE_D);
+ }
+
+ if (src1.type == BRW_REGISTER_TYPE_F ||
+ (src1.file == BRW_IMMEDIATE_VALUE &&
+ src1.type == BRW_REGISTER_TYPE_VF)) {
+ assert(src0.type != BRW_REGISTER_TYPE_UD);
+ assert(src0.type != BRW_REGISTER_TYPE_D);
+ }
+
+ return gen8_alu2(p, BRW_OPCODE_ADD, dst, src0, src1);
+}
+
+static inline struct gen8_instruction *gen8_MUL(struct brw_compile *p,
+ struct brw_reg dst,
+ struct brw_reg src0,
+ struct brw_reg src1)
+{
+ /* 6.32.38: mul */
+ if (src0.type == BRW_REGISTER_TYPE_D ||
+ src0.type == BRW_REGISTER_TYPE_UD ||
+ src1.type == BRW_REGISTER_TYPE_D ||
+ src1.type == BRW_REGISTER_TYPE_UD) {
+ assert(dst.type != BRW_REGISTER_TYPE_F);
+ }
+
+ if (src0.type == BRW_REGISTER_TYPE_F ||
+ (src0.file == BRW_IMMEDIATE_VALUE &&
+ src0.type == BRW_REGISTER_TYPE_VF)) {
+ assert(src1.type != BRW_REGISTER_TYPE_UD);
+ assert(src1.type != BRW_REGISTER_TYPE_D);
+ }
+
+ if (src1.type == BRW_REGISTER_TYPE_F ||
+ (src1.file == BRW_IMMEDIATE_VALUE &&
+ src1.type == BRW_REGISTER_TYPE_VF)) {
+ assert(src0.type != BRW_REGISTER_TYPE_UD);
+ assert(src0.type != BRW_REGISTER_TYPE_D);
+ }
+
+ assert(src0.file != BRW_ARCHITECTURE_REGISTER_FILE ||
+ src0.nr != BRW_ARF_ACCUMULATOR);
+ assert(src1.file != BRW_ARCHITECTURE_REGISTER_FILE ||
+ src1.nr != BRW_ARF_ACCUMULATOR);
+
+ return gen8_alu2(p, BRW_OPCODE_MUL, dst, src0, src1);
+}
+
+ALU1(MOV);
+ALU2(SEL);
+ALU1(NOT);
+ALU2(AND);
+ALU2(OR);
+ALU2(XOR);
+ALU2(SHR);
+ALU2(SHL);
+ALU2(RSR);
+ALU2(RSL);
+ALU2(ASR);
+ALU1(FRC);
+ALU1(RNDD);
+ALU2(MAC);
+ALU2(MACH);
+ALU1(LZD);
+ALU2(DP4);
+ALU2(DPH);
+ALU2(DP3);
+ALU2(DP2);
+ALU2(LINE);
+ALU2(PLN);
+
+ALU1(RNDZ);
+ALU1(RNDE);
+
+#undef ALU1
+#undef ALU2
+
+static void gen8_set_compression_control(struct brw_compile *p,
+ enum brw_compression compression_control)
+{
+ unsigned v;
+
+ p->compressed = compression_control == BRW_COMPRESSION_COMPRESSED;
+
+ switch (compression_control) {
+ default: assert(0);
+ case BRW_COMPRESSION_NONE: v = GEN6_COMPRESSION_1Q; break;
+ case BRW_COMPRESSION_2NDHALF: v = GEN6_COMPRESSION_2Q; break;
+ case BRW_COMPRESSION_COMPRESSED: v = GEN6_COMPRESSION_1H; break;
+ }
+ __gen8_set_cmpt_control((struct gen8_instruction *)p->current, v);
+}
+
+static inline void gen8_set_mask_control(struct brw_compile *p, unsigned value)
+{
+ __gen8_set_mask_control((struct gen8_instruction *)p->current, value);
+}
+
+static inline void gen8_set_saturate(struct brw_compile *p, unsigned value)
+{
+ __gen8_set_saturate((struct gen8_instruction *)p->current, value);
+}
+
+static inline void gen8_set_acc_write_control(struct brw_compile *p, unsigned value)
+{
+ __gen8_set_acc_wr_control((struct gen8_instruction *)p->current, value);
+}
+
+static void gen8_SAMPLE(struct brw_compile *p,
+ struct brw_reg dst,
+ unsigned msg_reg_nr,
+ unsigned binding_table_index,
+ unsigned sampler,
+ unsigned writemask,
+ unsigned msg_type,
+ unsigned response_length,
+ unsigned msg_length,
+ bool header_present,
+ unsigned simd_mode)
+{
+ struct brw_reg src0 = brw_message_reg(msg_reg_nr);
+
+ assert(writemask);
+
+ if (writemask != WRITEMASK_XYZW) {
+ writemask = ~writemask & WRITEMASK_XYZW;
+
+ brw_push_insn_state(p);
+
+ gen8_set_compression_control(p, BRW_COMPRESSION_NONE);
+ gen8_set_mask_control(p, BRW_MASK_DISABLE);
+
+ gen8_MOV(p, __retype_ud(src0), __retype_ud(brw_vec8_grf(0,0)));
+ gen8_MOV(p, get_element_ud(src0, 2), brw_imm_ud(writemask << 12));
+
+ brw_pop_insn_state(p);
+ }
+
+ {
+ struct gen8_instruction *insn;
+
+ insn = gen8_next_insn(p, BRW_OPCODE_SEND);
+ __gen8_set_pred_control(insn, 0); /* XXX */
+ __gen8_set_cmpt_control(insn, GEN6_COMPRESSION_1Q);
+
+ __gen8_set_dst(p, insn, dst);
+ __gen8_set_src0(insn, src0);
+ __gen8_set_sampler_message(insn,
+ binding_table_index,
+ sampler,
+ msg_type,
+ response_length,
+ msg_length,
+ header_present,
+ simd_mode);
+ }
+}
+
+/* shader logic */
+
+static void wm_affine_st(struct brw_compile *p, int dw, int channel, int msg)
+{
+ int uv;
+
+ if (dw == 16) {
+ gen8_set_compression_control(p, BRW_COMPRESSION_COMPRESSED);
+ uv = 6;
+ } else {
+ gen8_set_compression_control(p, BRW_COMPRESSION_NONE);
+ uv = 4;
+ }
+ uv += 2*channel;
+
+ msg++;
+ gen8_PLN(p,
+ brw_message_reg(msg),
+ brw_vec1_grf(uv, 0),
+ brw_vec8_grf(2, 0));
+ msg += dw/8;
+
+ gen8_PLN(p,
+ brw_message_reg(msg),
+ brw_vec1_grf(uv, 4),
+ brw_vec8_grf(2, 0));
+}
+
+static inline unsigned simd(int dw)
+{
+ return dw == 16 ? BRW_SAMPLER_SIMD_MODE_SIMD16 : BRW_SAMPLER_SIMD_MODE_SIMD8;
+}
+
+static inline struct brw_reg sample_result(int dw, int result)
+{
+ return brw_reg(BRW_GENERAL_REGISTER_FILE, result, 0,
+ BRW_REGISTER_TYPE_UW,
+ dw == 16 ? BRW_VERTICAL_STRIDE_16 : BRW_VERTICAL_STRIDE_8,
+ dw == 16 ? BRW_WIDTH_16 : BRW_WIDTH_8,
+ BRW_HORIZONTAL_STRIDE_1,
+ BRW_SWIZZLE_XYZW,
+ WRITEMASK_XYZW);
+}
+
+static int wm_sample(struct brw_compile *p, int dw,
+ int channel, int msg, int result)
+{
+ int len = dw == 16 ? 4 : 2;
+ gen8_SAMPLE(p, sample_result(dw, result), ++msg,
+ channel+1, channel, WRITEMASK_XYZW, 0,
+ 2*len, len, false, simd(dw));
+ return result;
+}
+
+static int wm_sample__alpha(struct brw_compile *p, int dw,
+ int channel, int msg, int result)
+{
+ int mlen, rlen;
+
+ if (dw == 8) {
+ mlen = 3;
+ rlen = 1;
+ } else {
+ mlen = 5;
+ rlen = 2;
+ }
+
+ gen8_SAMPLE(p, sample_result(dw, result), msg,
+ channel+1, channel, WRITEMASK_W, 0,
+ rlen, mlen, true, simd(dw));
+
+ return result;
+}
+
+static int wm_affine(struct brw_compile *p, int dw,
+ int channel, int msg, int result)
+{
+ wm_affine_st(p, dw, channel, msg);
+ return wm_sample(p, dw, channel, msg, result);
+}
+
+static int wm_affine__alpha(struct brw_compile *p, int dw,
+ int channel, int msg, int result)
+{
+ wm_affine_st(p, dw, channel, msg);
+ return wm_sample__alpha(p, dw, channel, msg, result);
+}
+
+static inline struct brw_reg null_result(int dw)
+{
+ return brw_reg(BRW_ARCHITECTURE_REGISTER_FILE, BRW_ARF_NULL, 0,
+ BRW_REGISTER_TYPE_UW,
+ dw == 16 ? BRW_VERTICAL_STRIDE_16 : BRW_VERTICAL_STRIDE_8,
+ dw == 16 ? BRW_WIDTH_16 : BRW_WIDTH_8,
+ BRW_HORIZONTAL_STRIDE_1,
+ BRW_SWIZZLE_XYZW,
+ WRITEMASK_XYZW);
+}
+
+static void fb_write(struct brw_compile *p, int dw)
+{
+ struct gen8_instruction *insn;
+ unsigned msg_control, msg_len;
+ struct brw_reg src0;
+
+ if (dw == 16) {
+ msg_control = BRW_DATAPORT_RENDER_TARGET_WRITE_SIMD16_SINGLE_SOURCE;
+ msg_len = 8;
+ } else {
+ msg_control = BRW_DATAPORT_RENDER_TARGET_WRITE_SIMD8_SINGLE_SOURCE_SUBSPAN01;
+ msg_len = 4;
+ }
+ msg_control |= 1 << 4; /* Last Render Target */
+
+ /* The execution mask is ignored for render target writes. */
+ insn = gen8_next_insn(p, BRW_OPCODE_SEND);
+ __gen8_set_pred_control(insn, 0);
+ __gen8_set_cmpt_control(insn, GEN6_COMPRESSION_1Q);
+
+ src0 = brw_message_reg(2);
+
+ __gen8_set_dst(p, insn, null_result(dw));
+ __gen8_set_src0(insn, src0);
+ __gen8_set_dp_message(insn,
+ GEN6_SFID_DATAPORT_RENDER_CACHE,
+ 0,
+ GEN6_DATAPORT_WRITE_MESSAGE_RENDER_TARGET_WRITE,
+ msg_control,
+ msg_len, 0,
+ false, true);
+}
+
+static void wm_write(struct brw_compile *p, int dw, int src)
+{
+ int n;
+
+ if (dw == 8) {
+ /* XXX pixel execution mask? */
+ gen8_set_compression_control(p, BRW_COMPRESSION_NONE);
+ for (n = 0; n < 4; n++)
+ gen8_MOV(p,
+ brw_message_reg(2 + n),
+ brw_vec8_grf(src + n, 0));
+ } else {
+ gen8_set_compression_control(p, BRW_COMPRESSION_COMPRESSED);
+ for (n = 0; n < 4; n++)
+ gen8_MOV(p,
+ brw_message_reg(2 + 2*n),
+ brw_vec8_grf(src + 2*n, 0));
+ }
+
+ fb_write(p, dw);
+}
+
+static void wm_write__mask(struct brw_compile *p, int dw,
+ int src, int mask)
+{
+ int n;
+
+ if (dw == 8) {
+ gen8_set_compression_control(p, BRW_COMPRESSION_NONE);
+ for (n = 0; n < 4; n++)
+ gen8_MUL(p,
+ brw_message_reg(2 + n),
+ brw_vec8_grf(src + n, 0),
+ brw_vec8_grf(mask, 0));
+ } else {
+ gen8_set_compression_control(p, BRW_COMPRESSION_COMPRESSED);
+ for (n = 0; n < 4; n++)
+ gen8_MUL(p,
+ brw_message_reg(2 + 2*n),
+ brw_vec8_grf(src + 2*n, 0),
+ brw_vec8_grf(mask, 0));
+ }
+
+ fb_write(p, dw);
+}
+
+static void wm_write__opacity(struct brw_compile *p, int dw, int src, int mask)
+{
+ int n;
+
+ if (dw == 8) {
+ gen8_set_compression_control(p, BRW_COMPRESSION_NONE);
+ for (n = 0; n < 4; n++)
+ gen8_MUL(p,
+ brw_message_reg(2 + n),
+ brw_vec8_grf(src + n, 0),
+ brw_vec1_grf(mask, 3));
+ } else {
+ gen8_set_compression_control(p, BRW_COMPRESSION_COMPRESSED);
+ for (n = 0; n < 4; n++)
+ gen8_MUL(p,
+ brw_message_reg(2 + 2*n),
+ brw_vec8_grf(src + 2*n, 0),
+ brw_vec1_grf(mask, 3));
+ }
+
+ fb_write(p, dw);
+}
+
+static void wm_write__mask_ca(struct brw_compile *p, int dw,
+ int src, int mask)
+{
+ int n;
+
+ if (dw == 8) {
+ gen8_set_compression_control(p, BRW_COMPRESSION_NONE);
+ for (n = 0; n < 4; n++)
+ gen8_MUL(p,
+ brw_message_reg(2 + n),
+ brw_vec8_grf(src + n, 0),
+ brw_vec8_grf(mask + n, 0));
+ } else {
+ gen8_set_compression_control(p, BRW_COMPRESSION_COMPRESSED);
+ for (n = 0; n < 4; n++)
+ gen8_MUL(p,
+ brw_message_reg(2 + 2*n),
+ brw_vec8_grf(src + 2*n, 0),
+ brw_vec8_grf(mask + 2*n, 0));
+ }
+
+ fb_write(p, dw);
+}
+
+static void gen8_compile_init(struct brw_compile *p)
+{
+ struct gen8_instruction *insn = memset(p->current, 0, sizeof(*insn));
+ COMPILE_TIME_ASSERT(sizeof(*insn) == sizeof(*p->current));
+ __gen8_set_mask_control(insn, BRW_MASK_ENABLE);
+ __gen8_set_saturate(insn, 0);
+ __gen8_set_cmpt_control(insn, GEN6_COMPRESSION_1Q);
+ //__gen8_set_pred_control(insn, 0xf);
+}
+
+bool
+gen8_wm_kernel__affine(struct brw_compile *p, int dispatch)
+{
+ gen8_compile_init(p);
+
+ wm_write(p, dispatch, wm_affine(p, dispatch, 0, 1, 12));
+ return true;
+}
+
+bool
+gen8_wm_kernel__affine_mask(struct brw_compile *p, int dispatch)
+{
+ int src, mask;
+
+ gen8_compile_init(p);
+
+ src = wm_affine(p, dispatch, 0, 1, 12);
+ mask = wm_affine__alpha(p, dispatch, 1, 6, 20);
+ wm_write__mask(p, dispatch, src, mask);
+
+ return true;
+}
+
+bool
+gen8_wm_kernel__affine_mask_ca(struct brw_compile *p, int dispatch)
+{
+ int src, mask;
+
+ gen8_compile_init(p);
+
+ src = wm_affine(p, dispatch, 0, 1, 12);
+ mask = wm_affine(p, dispatch, 1, 6, 20);
+ wm_write__mask_ca(p, dispatch, src, mask);
+
+ return true;
+}
+
+bool
+gen8_wm_kernel__affine_mask_sa(struct brw_compile *p, int dispatch)
+{
+ int src, mask;
+
+ gen8_compile_init(p);
+
+ src = wm_affine__alpha(p, dispatch, 0, 1, 12);
+ mask = wm_affine(p, dispatch, 1, 6, 16);
+ wm_write__mask(p, dispatch, mask, src);
+
+ return true;
+}
+
+/* Projective variants */
+
+static void wm_projective_st(struct brw_compile *p, int dw,
+ int channel, int msg)
+{
+ int uv;
+
+ gen8_compile_init(p);
+
+ if (dw == 16) {
+ gen8_set_compression_control(p, BRW_COMPRESSION_COMPRESSED);
+ uv = 6;
+ } else {
+ gen8_set_compression_control(p, BRW_COMPRESSION_NONE);
+ uv = 4;
+ }
+ uv += 2*channel;
+
+ msg++;
+ /* First compute 1/z */
+ gen8_PLN(p,
+ brw_vec8_grf(30, 0),
+ brw_vec1_grf(uv+1, 0),
+ brw_vec8_grf(2, 0));
+
+ if (dw == 16) {
+ gen8_set_compression_control(p, BRW_COMPRESSION_NONE);
+ gen8_math_invert(p, brw_vec8_grf(30, 0), brw_vec8_grf(30, 0));
+ gen8_math_invert(p, brw_vec8_grf(31, 0), brw_vec8_grf(31, 0));
+ gen8_set_compression_control(p, BRW_COMPRESSION_COMPRESSED);
+ } else
+ gen8_math_invert(p, brw_vec8_grf(30, 0), brw_vec8_grf(30, 0));
+
+ gen8_PLN(p,
+ brw_vec8_grf(26, 0),
+ brw_vec1_grf(uv, 0),
+ brw_vec8_grf(2, 0));
+ gen8_PLN(p,
+ brw_vec8_grf(28, 0),
+ brw_vec1_grf(uv, 0),
+ brw_vec8_grf(4, 0));
+
+ gen8_MUL(p,
+ brw_message_reg(msg),
+ brw_vec8_grf(26, 0),
+ brw_vec8_grf(30, 0));
+ gen8_MUL(p,
+ brw_message_reg(msg + dw/8),
+ brw_vec8_grf(28, 0),
+ brw_vec8_grf(30, 0));
+}
+
+static int wm_projective(struct brw_compile *p, int dw,
+ int channel, int msg, int result)
+{
+ gen8_compile_init(p);
+
+ wm_projective_st(p, dw, channel, msg);
+ return wm_sample(p, dw, channel, msg, result);
+}
+
+static int wm_projective__alpha(struct brw_compile *p, int dw,
+ int channel, int msg, int result)
+{
+ gen8_compile_init(p);
+
+ wm_projective_st(p, dw, channel, msg);
+ return wm_sample__alpha(p, dw, channel, msg, result);
+}
+
+bool
+gen8_wm_kernel__projective(struct brw_compile *p, int dispatch)
+{
+ gen8_compile_init(p);
+
+ wm_write(p, dispatch, wm_projective(p, dispatch, 0, 1, 12));
+ return true;
+}
+
+bool
+gen8_wm_kernel__projective_mask(struct brw_compile *p, int dispatch)
+{
+ int src, mask;
+
+ gen8_compile_init(p);
+
+ src = wm_projective(p, dispatch, 0, 1, 12);
+ mask = wm_projective__alpha(p, dispatch, 1, 6, 20);
+ wm_write__mask(p, dispatch, src, mask);
+
+ return true;
+}
+
+bool
+gen8_wm_kernel__projective_mask_ca(struct brw_compile *p, int dispatch)
+{
+ int src, mask;
+
+ gen8_compile_init(p);
+
+ src = wm_projective(p, dispatch, 0, 1, 12);
+ mask = wm_projective(p, dispatch, 1, 6, 20);
+ wm_write__mask_ca(p, dispatch, src, mask);
+
+ return true;
+}
+
+bool
+gen8_wm_kernel__projective_mask_sa(struct brw_compile *p, int dispatch)
+{
+ int src, mask;
+
+ gen8_compile_init(p);
+
+ src = wm_projective__alpha(p, dispatch, 0, 1, 12);
+ mask = wm_projective(p, dispatch, 1, 6, 16);
+ wm_write__mask(p, dispatch, mask, src);
+
+ return true;
+}
+
+bool
+gen8_wm_kernel__affine_opacity(struct brw_compile *p, int dispatch)
+{
+ int src, mask;
+
+ gen8_compile_init(p);
+
+ src = wm_affine(p, dispatch, 0, 1, 12);
+ mask = dispatch == 16 ? 8 : 6;
+ wm_write__opacity(p, dispatch, src, mask);
+
+ return true;
+}
+
+bool
+gen8_wm_kernel__projective_opacity(struct brw_compile *p, int dispatch)
+{
+ int src, mask;
+
+ gen8_compile_init(p);
+
+ mask = dispatch == 16 ? 8 : 6;
+ src = wm_projective(p, dispatch, 0, 1, 12);
+ wm_write__opacity(p, dispatch, src, mask);
+
+ return true;
+}
diff --git a/src/sna/gen8_eu.h b/src/sna/gen8_eu.h
new file mode 100644
index 0000000..e348a8e
--- /dev/null
+++ b/src/sna/gen8_eu.h
@@ -0,0 +1,19 @@
+#ifndef GEN8_EU_H
+#define GEN8_EU_H
+
+#include "brw/brw_eu.h"
+
+bool gen8_wm_kernel__affine(struct brw_compile *p, int dispatch_width);
+bool gen8_wm_kernel__affine_mask(struct brw_compile *p, int dispatch_width);
+bool gen8_wm_kernel__affine_mask_ca(struct brw_compile *p, int dispatch_width);
+bool gen8_wm_kernel__affine_mask_sa(struct brw_compile *p, int dispatch_width);
+
+bool gen8_wm_kernel__projective(struct brw_compile *p, int dispatch_width);
+bool gen8_wm_kernel__projective_mask(struct brw_compile *p, int dispatch_width);
+bool gen8_wm_kernel__projective_mask_ca(struct brw_compile *p, int dispatch_width);
+bool gen8_wm_kernel__projective_mask_sa(struct brw_compile *p, int dispatch_width);
+
+bool gen8_wm_kernel__affine_opacity(struct brw_compile *p, int dispatch_width);
+bool gen8_wm_kernel__projective_opacity(struct brw_compile *p, int dispatch_width);
+
+#endif /* GEN8_EU_H */
diff --git a/src/sna/gen8_render.c b/src/sna/gen8_render.c
new file mode 100644
index 0000000..a8b4ea8
--- /dev/null
+++ b/src/sna/gen8_render.c
@@ -0,0 +1,3910 @@
+/*
+ * Copyright © 2012,2013 Intel Corporation
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+ * SOFTWARE.
+ *
+ * Authors:
+ * Chris Wilson <chris at chris-wilson.co.uk>
+ *
+ */
+
+#ifdef HAVE_CONFIG_H
+#include "config.h"
+#endif
+
+#include "sna.h"
+#include "sna_reg.h"
+#include "sna_render.h"
+#include "sna_render_inline.h"
+#include "sna_video.h"
+
+#include "gen8_render.h"
+#include "gen8_eu.h"
+#include "gen4_common.h"
+#include "gen4_source.h"
+#include "gen4_vertex.h"
+#include "gen6_common.h"
+#include "gen8_vertex.h"
+
+#define SIM 1
+
+#define ALWAYS_INVALIDATE 0
+#define ALWAYS_FLUSH 0
+#define ALWAYS_STALL 0
+
+#define NO_COMPOSITE 0
+#define NO_COMPOSITE_SPANS 0
+#define NO_COPY 0
+#define NO_COPY_BOXES 0
+#define NO_FILL 0
+#define NO_FILL_BOXES 0
+#define NO_FILL_ONE 0
+#define NO_FILL_CLEAR 0
+#define NO_VIDEO 0
+
+#define USE_8_PIXEL_DISPATCH 1
+#define USE_16_PIXEL_DISPATCH 1
+#define USE_32_PIXEL_DISPATCH 0
+
+#if !USE_8_PIXEL_DISPATCH && !USE_16_PIXEL_DISPATCH && !USE_32_PIXEL_DISPATCH
+#error "Must select at least 8, 16 or 32 pixel dispatch"
+#endif
+
+#define GEN8_MAX_SIZE 16384
+
+/* XXX Todo
+ *
+ * STR (software tiled rendering) mode. No, really.
+ * 64x32 pixel blocks align with the rendering cache. Worth considering.
+ */
+
+#define is_aligned(x, y) (((x) & ((y) - 1)) == 0)
+
+/* Pipeline stages:
+ * 1. Command Streamer (CS)
+ * 2. Vertex Fetch (VF)
+ * 3. Vertex Shader (VS)
+ * 4. Hull Shader (HS)
+ * 5. Tesselation Engine (TE)
+ * 6. Domain Shader (DS)
+ * 7. Geometry Shader (GS)
+ * 8. Stream Output Logic (SOL)
+ * 9. Clipper (CLIP)
+ * 10. Strip/Fan (SF)
+ * 11. Windower/Masker (WM)
+ * 12. Color Calculator (CC)
+ */
+
+#if !NO_VIDEO
+static const uint32_t ps_kernel_packed[][4] = {
+#include "exa_wm_src_affine.g8b"
+#include "exa_wm_src_sample_argb.g8b"
+#include "exa_wm_yuv_rgb.g8b"
+#include "exa_wm_write.g8b"
+};
+
+static const uint32_t ps_kernel_planar[][4] = {
+#include "exa_wm_src_affine.g8b"
+#include "exa_wm_src_sample_planar.g8b"
+#include "exa_wm_yuv_rgb.g8b"
+#include "exa_wm_write.g8b"
+};
+#endif
+
+#define SURFACE_DW (64 / sizeof(uint32_t));
+
+#define KERNEL(kernel_enum, kernel, num_surfaces) \
+ [GEN8_WM_KERNEL_##kernel_enum] = {#kernel_enum, kernel, sizeof(kernel), num_surfaces}
+#define NOKERNEL(kernel_enum, func, num_surfaces) \
+ [GEN8_WM_KERNEL_##kernel_enum] = {#kernel_enum, (void *)func, 0, num_surfaces}
+static const struct wm_kernel_info {
+ const char *name;
+ const void *data;
+ unsigned int size;
+ int num_surfaces;
+} wm_kernels[] = {
+ NOKERNEL(NOMASK, gen8_wm_kernel__affine, 2),
+ NOKERNEL(NOMASK_P, gen8_wm_kernel__projective, 2),
+
+ NOKERNEL(MASK, gen8_wm_kernel__affine_mask, 3),
+ NOKERNEL(MASK_P, gen8_wm_kernel__projective_mask, 3),
+
+ NOKERNEL(MASKCA, gen8_wm_kernel__affine_mask_ca, 3),
+ NOKERNEL(MASKCA_P, gen8_wm_kernel__projective_mask_ca, 3),
+
+ NOKERNEL(MASKSA, gen8_wm_kernel__affine_mask_sa, 3),
+ NOKERNEL(MASKSA_P, gen8_wm_kernel__projective_mask_sa, 3),
+
+ NOKERNEL(OPACITY, gen8_wm_kernel__affine_opacity, 2),
+ NOKERNEL(OPACITY_P, gen8_wm_kernel__projective_opacity, 2),
+
+#if !NO_VIDEO
+ KERNEL(VIDEO_PLANAR, ps_kernel_planar, 7),
+ KERNEL(VIDEO_PACKED, ps_kernel_packed, 2),
+#endif
+};
+#undef KERNEL
+
+static const struct blendinfo {
+ uint8_t src_alpha;
+ uint8_t src_blend;
+ uint8_t dst_blend;
+} gen8_blend_op[] = {
+ /* Clear */ {0, BLENDFACTOR_ZERO, BLENDFACTOR_ZERO},
+ /* Src */ {0, BLENDFACTOR_ONE, BLENDFACTOR_ZERO},
+ /* Dst */ {0, BLENDFACTOR_ZERO, BLENDFACTOR_ONE},
+ /* Over */ {1, BLENDFACTOR_ONE, BLENDFACTOR_INV_SRC_ALPHA},
+ /* OverReverse */ {0, BLENDFACTOR_INV_DST_ALPHA, BLENDFACTOR_ONE},
+ /* In */ {0, BLENDFACTOR_DST_ALPHA, BLENDFACTOR_ZERO},
+ /* InReverse */ {1, BLENDFACTOR_ZERO, BLENDFACTOR_SRC_ALPHA},
+ /* Out */ {0, BLENDFACTOR_INV_DST_ALPHA, BLENDFACTOR_ZERO},
+ /* OutReverse */ {1, BLENDFACTOR_ZERO, BLENDFACTOR_INV_SRC_ALPHA},
+ /* Atop */ {1, BLENDFACTOR_DST_ALPHA, BLENDFACTOR_INV_SRC_ALPHA},
+ /* AtopReverse */ {1, BLENDFACTOR_INV_DST_ALPHA, BLENDFACTOR_SRC_ALPHA},
+ /* Xor */ {1, BLENDFACTOR_INV_DST_ALPHA, BLENDFACTOR_INV_SRC_ALPHA},
+ /* Add */ {0, BLENDFACTOR_ONE, BLENDFACTOR_ONE},
+};
+
+/**
+ * Highest-valued BLENDFACTOR used in gen8_blend_op.
+ *
+ * This leaves out GEN8_BLENDFACTOR_INV_DST_COLOR,
+ * GEN8_BLENDFACTOR_INV_CONST_{COLOR,ALPHA},
+ * GEN8_BLENDFACTOR_INV_SRC1_{COLOR,ALPHA}
+ */
+#define GEN8_BLENDFACTOR_COUNT (BLENDFACTOR_INV_DST_ALPHA + 1)
+
+#define GEN8_BLEND_STATE_PADDED_SIZE ALIGN(sizeof(struct gen8_blend_state), 64)
+
+#define BLEND_OFFSET(s, d) \
+ ((d != BLENDFACTOR_ZERO) << 15 | ((s) * GEN8_BLENDFACTOR_COUNT + (d)) << 4)
+
+#define NO_BLEND BLEND_OFFSET(BLENDFACTOR_ONE, BLENDFACTOR_ZERO)
+#define CLEAR BLEND_OFFSET(BLENDFACTOR_ZERO, BLENDFACTOR_ZERO)
+
+#define SAMPLER_OFFSET(sf, se, mf, me) \
+ (((((sf) * EXTEND_COUNT + (se)) * FILTER_COUNT + (mf)) * EXTEND_COUNT + (me)) + 2)
+
+#define VERTEX_2s2s 0
+
+#define COPY_SAMPLER 0
+#define COPY_VERTEX VERTEX_2s2s
+#define COPY_FLAGS(a) GEN8_SET_FLAGS(COPY_SAMPLER, (a) == GXcopy ? NO_BLEND : CLEAR, GEN8_WM_KERNEL_NOMASK, COPY_VERTEX)
+
+#define FILL_SAMPLER 1
+#define FILL_VERTEX VERTEX_2s2s
+#define FILL_FLAGS(op, format) GEN8_SET_FLAGS(FILL_SAMPLER, gen8_get_blend((op), false, (format)), GEN8_WM_KERNEL_NOMASK, FILL_VERTEX)
+#define FILL_FLAGS_NOBLEND GEN8_SET_FLAGS(FILL_SAMPLER, NO_BLEND, GEN8_WM_KERNEL_NOMASK, FILL_VERTEX)
+
+#define VIDEO_SAMPLER \
+ SAMPLER_OFFSET(SAMPLER_FILTER_BILINEAR, SAMPLER_EXTEND_PAD, \
+ SAMPLER_FILTER_NEAREST, SAMPLER_EXTEND_NONE)
+
+#define GEN8_SAMPLER(f) (((f) >> 20) & 0xfff)
+#define GEN8_BLEND(f) (((f) >> 4) & 0x7ff)
+#define GEN8_READS_DST(f) (((f) >> 15) & 1)
+#define GEN8_KERNEL(f) (((f) >> 16) & 0xf)
+#define GEN8_VERTEX(f) (((f) >> 0) & 0xf)
+#define GEN8_SET_FLAGS(S, B, K, V) ((S) << 20 | (K) << 16 | (B) | (V))
+
+#define OUT_BATCH(v) batch_emit(sna, v)
+#define OUT_BATCH64(v) batch_emit64(sna, v)
+#define OUT_VERTEX(x,y) vertex_emit_2s(sna, x,y)
+#define OUT_VERTEX_F(v) vertex_emit(sna, v)
+
+static inline bool too_large(int width, int height)
+{
+ return width > GEN8_MAX_SIZE || height > GEN8_MAX_SIZE;
+}
+
+static uint32_t gen8_get_blend(int op,
+ bool has_component_alpha,
+ uint32_t dst_format)
+{
+ uint32_t src, dst;
+
+ COMPILE_TIME_ASSERT(BLENDFACTOR_INV_DST_ALPHA*GEN8_BLENDFACTOR_COUNT + BLENDFACTOR_INV_DST_ALPHA <= 0x7ff);
+
+ src = gen8_blend_op[op].src_blend;
+ dst = gen8_blend_op[op].dst_blend;
+
+ /* If there's no dst alpha channel, adjust the blend op so that
+ * we'll treat it always as 1.
+ */
+ if (PICT_FORMAT_A(dst_format) == 0) {
+ if (src == BLENDFACTOR_DST_ALPHA)
+ src = BLENDFACTOR_ONE;
+ else if (src == BLENDFACTOR_INV_DST_ALPHA)
+ src = BLENDFACTOR_ZERO;
+ }
+
+ /* If the source alpha is being used, then we should only be in a
+ * case where the source blend factor is 0, and the source blend
+ * value is the mask channels multiplied by the source picture's alpha.
+ */
+ if (has_component_alpha && gen8_blend_op[op].src_alpha) {
+ if (dst == BLENDFACTOR_SRC_ALPHA)
+ dst = BLENDFACTOR_SRC_COLOR;
+ else if (dst == BLENDFACTOR_INV_SRC_ALPHA)
+ dst = BLENDFACTOR_INV_SRC_COLOR;
+ }
+
+ DBG(("blend op=%d, dst=%x [A=%d] => src=%d, dst=%d => offset=%x\n",
+ op, dst_format, PICT_FORMAT_A(dst_format),
+ src, dst, (int)(BLEND_OFFSET(src, dst)>>4)));
+ assert(BLEND_OFFSET(src, dst) >> 4 <= 0xfff);
+ return BLEND_OFFSET(src, dst);
+}
+
+static uint32_t gen8_get_card_format(PictFormat format)
+{
+ switch (format) {
+ default:
+ return -1;
+ case PICT_a8r8g8b8:
+ return SURFACEFORMAT_B8G8R8A8_UNORM;
+ case PICT_x8r8g8b8:
+ return SURFACEFORMAT_B8G8R8X8_UNORM;
+ case PICT_a8b8g8r8:
+ return SURFACEFORMAT_R8G8B8A8_UNORM;
+ case PICT_x8b8g8r8:
+ return SURFACEFORMAT_R8G8B8X8_UNORM;
+#ifdef PICT_a2r10g10b10
+ case PICT_a2r10g10b10:
+ return SURFACEFORMAT_B10G10R10A2_UNORM;
+ case PICT_x2r10g10b10:
+ return SURFACEFORMAT_B10G10R10X2_UNORM;
+#endif
+ case PICT_r8g8b8:
+ return SURFACEFORMAT_R8G8B8_UNORM;
+ case PICT_r5g6b5:
+ return SURFACEFORMAT_B5G6R5_UNORM;
+ case PICT_a1r5g5b5:
+ return SURFACEFORMAT_B5G5R5A1_UNORM;
+ case PICT_a8:
+ return SURFACEFORMAT_A8_UNORM;
+ case PICT_a4r4g4b4:
+ return SURFACEFORMAT_B4G4R4A4_UNORM;
+ }
+}
+
+static uint32_t gen8_get_dest_format(PictFormat format)
+{
+ switch (format) {
+ default:
+ return -1;
+ case PICT_a8r8g8b8:
+ case PICT_x8r8g8b8:
+ return SURFACEFORMAT_B8G8R8A8_UNORM;
+ case PICT_a8b8g8r8:
+ case PICT_x8b8g8r8:
+ return SURFACEFORMAT_R8G8B8A8_UNORM;
+#ifdef PICT_a2r10g10b10
+ case PICT_a2r10g10b10:
+ case PICT_x2r10g10b10:
+ return SURFACEFORMAT_B10G10R10A2_UNORM;
+#endif
+ case PICT_r5g6b5:
+ return SURFACEFORMAT_B5G6R5_UNORM;
+ case PICT_x1r5g5b5:
+ case PICT_a1r5g5b5:
+ return SURFACEFORMAT_B5G5R5A1_UNORM;
+ case PICT_a8:
+ return SURFACEFORMAT_A8_UNORM;
+ case PICT_a4r4g4b4:
+ case PICT_x4r4g4b4:
+ return SURFACEFORMAT_B4G4R4A4_UNORM;
+ }
+}
+
+static bool gen8_check_dst_format(PictFormat format)
+{
+ if (gen8_get_dest_format(format) != -1)
+ return true;
+
+ DBG(("%s: unhandled format: %x\n", __FUNCTION__, (int)format));
+ return false;
+}
+
+static bool gen8_check_format(uint32_t format)
+{
+ if (gen8_get_card_format(format) != -1)
+ return true;
+
+ DBG(("%s: unhandled format: %x\n", __FUNCTION__, (int)format));
+ return false;
+}
+
+static uint32_t gen8_filter(uint32_t filter)
+{
+ switch (filter) {
+ default:
+ assert(0);
+ case PictFilterNearest:
+ return SAMPLER_FILTER_NEAREST;
+ case PictFilterBilinear:
+ return SAMPLER_FILTER_BILINEAR;
+ }
+}
+
+static uint32_t gen8_check_filter(PicturePtr picture)
+{
+ switch (picture->filter) {
+ case PictFilterNearest:
+ case PictFilterBilinear:
+ return true;
+ default:
+ return false;
+ }
+}
+
+static uint32_t gen8_repeat(uint32_t repeat)
+{
+ switch (repeat) {
+ default:
+ assert(0);
+ case RepeatNone:
+ return SAMPLER_EXTEND_NONE;
+ case RepeatNormal:
+ return SAMPLER_EXTEND_REPEAT;
+ case RepeatPad:
+ return SAMPLER_EXTEND_PAD;
+ case RepeatReflect:
+ return SAMPLER_EXTEND_REFLECT;
+ }
+}
+
+static bool gen8_check_repeat(PicturePtr picture)
+{
+ if (!picture->repeat)
+ return true;
+
+ switch (picture->repeatType) {
+ case RepeatNone:
+ case RepeatNormal:
+ case RepeatPad:
+ case RepeatReflect:
+ return true;
+ default:
+ return false;
+ }
+}
+
+static int
+gen8_choose_composite_kernel(int op, bool has_mask, bool is_ca, bool is_affine)
+{
+ int base;
+
+ if (has_mask) {
+ if (is_ca) {
+ if (gen8_blend_op[op].src_alpha)
+ base = GEN8_WM_KERNEL_MASKSA;
+ else
+ base = GEN8_WM_KERNEL_MASKCA;
+ } else
+ base = GEN8_WM_KERNEL_MASK;
+ } else
+ base = GEN8_WM_KERNEL_NOMASK;
+
+ return base + !is_affine;
+}
+
+static void
+gen8_emit_urb(struct sna *sna)
+{
+#if SIM
+ OUT_BATCH(GEN8_3DSTATE_PUSH_CONSTANT_ALLOC_PS | (2 - 2));
+ OUT_BATCH(0 << PUSH_CONSTANT_BUFFER_OFFSET_SHIFT |
+ 4 << PUSH_CONSTANT_BUFFER_SIZE_SHIFT); /* 8KiB */
+#endif
+
+ /* num of VS entries must be divisible by 8 if size < 9 */
+ OUT_BATCH(GEN8_3DSTATE_URB_VS | (2 - 2));
+ OUT_BATCH(960 << URB_ENTRY_NUMBER_SHIFT |
+ (2 - 1) << URB_ENTRY_SIZE_SHIFT |
+ 1 << URB_STARTING_ADDRESS_SHIFT);
+
+ OUT_BATCH(GEN8_3DSTATE_URB_HS | (2 - 2));
+ OUT_BATCH(0 << URB_ENTRY_SIZE_SHIFT |
+ 0 << URB_STARTING_ADDRESS_SHIFT);
+
+ OUT_BATCH(GEN8_3DSTATE_URB_DS | (2 - 2));
+ OUT_BATCH(0 << URB_ENTRY_SIZE_SHIFT |
+ 0 << URB_STARTING_ADDRESS_SHIFT);
+
+ OUT_BATCH(GEN8_3DSTATE_URB_GS | (2 - 2));
+ OUT_BATCH(0 << URB_ENTRY_SIZE_SHIFT |
+ 0 << URB_STARTING_ADDRESS_SHIFT);
+}
+
+static void
+gen8_emit_state_base_address(struct sna *sna)
+{
+ uint32_t num_pages;
+
+ assert(sna->kgem.surface - sna->kgem.nbatch <= 16384);
+
+ OUT_BATCH(GEN8_STATE_BASE_ADDRESS | (16 - 2));
+ OUT_BATCH64(0); /* general */
+ OUT_BATCH(0); /* stateless dataport */
+ OUT_BATCH64(kgem_add_reloc64(&sna->kgem, /* surface */
+ sna->kgem.nbatch,
+ NULL,
+ I915_GEM_DOMAIN_INSTRUCTION << 16,
+ BASE_ADDRESS_MODIFY));
+ OUT_BATCH64(kgem_add_reloc64(&sna->kgem, /* dynamic */
+ sna->kgem.nbatch,
+ sna->render_state.gen8.general_bo,
+ I915_GEM_DOMAIN_INSTRUCTION << 16,
+ BASE_ADDRESS_MODIFY));
+ OUT_BATCH64(0); /* indirect */
+ OUT_BATCH64(kgem_add_reloc64(&sna->kgem, /* instruction */
+ sna->kgem.nbatch,
+ sna->render_state.gen8.general_bo,
+ I915_GEM_DOMAIN_INSTRUCTION << 16,
+ BASE_ADDRESS_MODIFY));
+ /* upper bounds */
+ num_pages = sna->render_state.gen8.general_bo->size.pages.count;
+ OUT_BATCH(0); /* general */
+ OUT_BATCH(num_pages << 12 | 1); /* dynamic */
+ OUT_BATCH(0); /* indirect */
+ OUT_BATCH(num_pages << 12 | 1); /* instruction */
+}
+
+static void
+gen8_emit_vs_invariant(struct sna *sna)
+{
+ OUT_BATCH(GEN8_3DSTATE_VS | (9 - 2));
+ OUT_BATCH64(0); /* no VS kernel */
+ OUT_BATCH(0);
+ OUT_BATCH64(0);
+ OUT_BATCH(0);
+ OUT_BATCH(1 << 1); /* pass-through */
+ OUT_BATCH(1 << 16 | 1 << 21); /* urb write to SBE */
+
+#if SIM
+ OUT_BATCH(GEN8_3DSTATE_CONSTANT_VS | (11 - 2));
+ OUT_BATCH(0);
+ OUT_BATCH(0);
+ OUT_BATCH64(0);
+ OUT_BATCH64(0);
+ OUT_BATCH64(0);
+ OUT_BATCH64(0);
+
+ OUT_BATCH(GEN8_3DSTATE_BINDING_TABLE_POINTERS_VS | (2 - 2));
+ OUT_BATCH(0);
+
+ OUT_BATCH(GEN8_3DSTATE_SAMPLER_STATE_POINTERS_VS | (2 - 2));
+ OUT_BATCH(0);
+#endif
+}
+
+static void
+gen8_emit_hs_invariant(struct sna *sna)
+{
+ OUT_BATCH(GEN8_3DSTATE_HS | (9 - 2));
+ OUT_BATCH(0); /* no HS kernel */
+ OUT_BATCH(0);
+ OUT_BATCH(0);
+ OUT_BATCH(0);
+ OUT_BATCH(0);
+ OUT_BATCH(0);
+ OUT_BATCH(0);
+ OUT_BATCH(0); /* pass-through */
+
+#if SIM
+ OUT_BATCH(GEN8_3DSTATE_CONSTANT_HS | (11 - 2));
+ OUT_BATCH(0);
+ OUT_BATCH(0);
+ OUT_BATCH64(0);
+ OUT_BATCH64(0);
+ OUT_BATCH64(0);
+ OUT_BATCH64(0);
+
+#if 1
+ OUT_BATCH(GEN8_3DSTATE_BINDING_TABLE_POINTERS_HS | (2 - 2));
+ OUT_BATCH(0);
+
+ OUT_BATCH(GEN8_3DSTATE_SAMPLER_STATE_POINTERS_HS | (2 - 2));
+ OUT_BATCH(0);
+#endif
+#endif
+}
+
+static void
+gen8_emit_te_invariant(struct sna *sna)
+{
+ OUT_BATCH(GEN8_3DSTATE_TE | (4 - 2));
+ OUT_BATCH(0);
+ OUT_BATCH(0);
+ OUT_BATCH(0);
+}
+
+static void
+gen8_emit_ds_invariant(struct sna *sna)
+{
+ OUT_BATCH(GEN8_3DSTATE_DS | (9 - 2));
+ OUT_BATCH(0);
+ OUT_BATCH(0);
+ OUT_BATCH(0);
+ OUT_BATCH(0);
+ OUT_BATCH(0);
+ OUT_BATCH(0);
+ OUT_BATCH(0);
+ OUT_BATCH(0);
+
+#if SIM
+ OUT_BATCH(GEN8_3DSTATE_CONSTANT_DS | (11 - 2));
+ OUT_BATCH(0);
+ OUT_BATCH(0);
+ OUT_BATCH64(0);
+ OUT_BATCH64(0);
+ OUT_BATCH64(0);
+ OUT_BATCH64(0);
+
+#if 1
+ OUT_BATCH(GEN8_3DSTATE_BINDING_TABLE_POINTERS_DS | (2 - 2));
+ OUT_BATCH(0);
+
+ OUT_BATCH(GEN8_3DSTATE_SAMPLER_STATE_POINTERS_DS | (2 - 2));
+ OUT_BATCH(0);
+#endif
+#endif
+}
+
+static void
+gen8_emit_gs_invariant(struct sna *sna)
+{
+ OUT_BATCH(GEN8_3DSTATE_GS | (10 - 2));
+ OUT_BATCH(0); /* no GS kernel */
+ OUT_BATCH(0);
+ OUT_BATCH(0);
+ OUT_BATCH(0);
+ OUT_BATCH(0);
+ OUT_BATCH(0);
+ OUT_BATCH(0);
+ OUT_BATCH(0);
+ OUT_BATCH(0); /* pass-through */
+
+#if SIM
+ OUT_BATCH(GEN8_3DSTATE_CONSTANT_GS | (11 - 2));
+ OUT_BATCH(0);
+ OUT_BATCH(0);
+ OUT_BATCH64(0);
+ OUT_BATCH64(0);
+ OUT_BATCH64(0);
+ OUT_BATCH64(0);
+
+#if 1
+ OUT_BATCH(GEN8_3DSTATE_BINDING_TABLE_POINTERS_GS | (2 - 2));
+ OUT_BATCH(0);
+
+ OUT_BATCH(GEN8_3DSTATE_SAMPLER_STATE_POINTERS_GS | (2 - 2));
+ OUT_BATCH(0);
+#endif
+#endif
+}
+
+static void
+gen8_emit_sol_invariant(struct sna *sna)
+{
+ OUT_BATCH(GEN8_3DSTATE_STREAMOUT | (5 - 2));
+ OUT_BATCH(0);
+ OUT_BATCH(0);
+ OUT_BATCH(0);
+ OUT_BATCH(0);
+}
+
+static void
+gen8_emit_sf_invariant(struct sna *sna)
+{
+ OUT_BATCH(GEN8_3DSTATE_SF | (4 - 2));
+ OUT_BATCH(0);
+ OUT_BATCH(0);
+ OUT_BATCH(0);
+}
+
+static void
+gen8_emit_clip_invariant(struct sna *sna)
+{
+ OUT_BATCH(GEN8_3DSTATE_CLIP | (4 - 2));
+ OUT_BATCH(0);
+ OUT_BATCH(0); /* pass-through */
+ OUT_BATCH(0);
+
+ OUT_BATCH(GEN8_3DSTATE_VIEWPORT_STATE_POINTERS_SF_CLIP | (2 - 2));
+ OUT_BATCH(0);
+
+ OUT_BATCH(GEN8_3DSTATE_VIEWPORT_STATE_POINTERS_CC | (2 - 2));
+ OUT_BATCH(0);
+}
+
+static void
+gen8_emit_null_depth_buffer(struct sna *sna)
+{
+ OUT_BATCH(GEN8_3DSTATE_DEPTH_BUFFER | (8 - 2));
+ OUT_BATCH(SURFACE_NULL << DEPTH_BUFFER_TYPE_SHIFT |
+ DEPTHFORMAT_D32_FLOAT << DEPTH_BUFFER_FORMAT_SHIFT);
+ OUT_BATCH64(0);
+ OUT_BATCH(0);
+ OUT_BATCH(0);
+ OUT_BATCH(0);
+ OUT_BATCH(0);
+
+#if SIM
+ OUT_BATCH(GEN8_3DSTATE_HIER_DEPTH_BUFFER | (5 - 2));
+ OUT_BATCH(0);
+ OUT_BATCH64(0);
+ OUT_BATCH(0);
+#endif
+
+#if SIM
+ OUT_BATCH(GEN8_3DSTATE_STENCIL_BUFFER | (5 - 2));
+ OUT_BATCH(0);
+ OUT_BATCH64(0);
+ OUT_BATCH(0);
+#endif
+
+#if SIM
+ OUT_BATCH(GEN8_3DSTATE_WM_DEPTH_STENCIL | (3 - 2));
+ OUT_BATCH(0);
+ OUT_BATCH(0);
+#endif
+
+#if SIM
+ OUT_BATCH(GEN8_3DSTATE_CLEAR_PARAMS | (3 - 2));
+ OUT_BATCH(0);
+ OUT_BATCH(0);
+#endif
+}
+
+static void
+gen8_emit_wm_invariant(struct sna *sna)
+{
+ gen8_emit_null_depth_buffer(sna);
+
+#if SIM
+ OUT_BATCH(GEN8_3DSTATE_SCISSOR_STATE_POINTERS | (2 - 2));
+ OUT_BATCH(0);
+#endif
+
+ OUT_BATCH(GEN8_3DSTATE_WM | (2 - 2));
+ //OUT_BATCH(WM_NONPERSPECTIVE_PIXEL_BARYCENTRIC); /* XXX */
+ OUT_BATCH(WM_PERSPECTIVE_PIXEL_BARYCENTRIC);
+
+#if SIM
+ OUT_BATCH(GEN8_3DSTATE_WM_HZ_OP | (5 - 2));
+ OUT_BATCH(0);
+ OUT_BATCH(0);
+ OUT_BATCH(0);
+ OUT_BATCH(0);
+
+ OUT_BATCH(GEN8_3DSTATE_WM_CHROMAKEY | (2 - 2));
+ OUT_BATCH(0);
+#endif
+
+ OUT_BATCH(GEN8_3DSTATE_PS_EXTRA | (2 - 2));
+ OUT_BATCH(PSX_PIXEL_SHADER_VALID |
+ PSX_ATTRIBUTE_ENABLE);
+
+ OUT_BATCH(GEN8_3DSTATE_RASTER | (5 - 2));
+ OUT_BATCH(RASTER_FRONT_WINDING_CCW |
+ RASTER_CULL_NONE);
+ OUT_BATCH(0);
+ OUT_BATCH(0);
+ OUT_BATCH(0);
+
+ OUT_BATCH(GEN8_3DSTATE_SBE_SWIZ | (11 - 2));
+ OUT_BATCH(0);
+ OUT_BATCH(0);
+ OUT_BATCH(0);
+ OUT_BATCH(0);
+ OUT_BATCH(0);
+ OUT_BATCH(0);
+ OUT_BATCH(0);
+ OUT_BATCH(0);
+ OUT_BATCH(0);
+ OUT_BATCH(0);
+
+#if SIM
+ OUT_BATCH(GEN8_3DSTATE_CONSTANT_PS | (11 - 2));
+ OUT_BATCH(0);
+ OUT_BATCH(0);
+ OUT_BATCH64(0);
+ OUT_BATCH64(0);
+ OUT_BATCH64(0);
+ OUT_BATCH64(0);
+#endif
+}
+
+static void
+gen8_emit_cc_invariant(struct sna *sna)
+{
+}
+
+static void
+gen8_emit_vf_invariant(struct sna *sna)
+{
+#if 1
+ OUT_BATCH(GEN8_3DSTATE_VF | (2 - 2));
+ OUT_BATCH(0);
+#endif
+
+ OUT_BATCH(GEN8_3DSTATE_VF_SGVS | (2 - 2));
+ OUT_BATCH(0);
+
+ OUT_BATCH(GEN8_3DSTATE_VF_TOPOLOGY | (2 - 2));
+ OUT_BATCH(RECTLIST);
+
+ OUT_BATCH(GEN8_3DSTATE_VF_STATISTICS | 0);
+}
+
+static void
+gen8_emit_invariant(struct sna *sna)
+{
+ OUT_BATCH(GEN8_PIPELINE_SELECT | PIPELINE_SELECT_3D);
+
+ OUT_BATCH(GEN8_3DSTATE_MULTISAMPLE | (2 - 2));
+ OUT_BATCH(MULTISAMPLE_PIXEL_LOCATION_CENTER |
+ MULTISAMPLE_NUMSAMPLES_1); /* 1 sample/pixel */
+
+ OUT_BATCH(GEN8_3DSTATE_SAMPLE_MASK | (2 - 2));
+ OUT_BATCH(1);
+
+#if SIM
+ OUT_BATCH(GEN8_3DSTATE_SAMPLE_PATTERN | (9 - 2));
+ OUT_BATCH(0);
+ OUT_BATCH(0);
+ OUT_BATCH(0);
+ OUT_BATCH(0);
+ OUT_BATCH(0);
+ OUT_BATCH(0);
+ OUT_BATCH(0);
+ //OUT_BATCH(8<<20 | 8<<16);
+ OUT_BATCH(0);
+#endif
+
+ gen8_emit_urb(sna);
+
+ gen8_emit_state_base_address(sna);
+
+ gen8_emit_vf_invariant(sna);
+ gen8_emit_vs_invariant(sna);
+ gen8_emit_hs_invariant(sna);
+ gen8_emit_te_invariant(sna);
+ gen8_emit_ds_invariant(sna);
+ gen8_emit_gs_invariant(sna);
+ gen8_emit_sol_invariant(sna);
+ gen8_emit_clip_invariant(sna);
+ gen8_emit_sf_invariant(sna);
+ gen8_emit_wm_invariant(sna);
+ gen8_emit_cc_invariant(sna);
+
+ sna->render_state.gen8.needs_invariant = false;
+}
+
+static void
+gen8_emit_cc(struct sna *sna, uint32_t blend)
+{
+ struct gen8_render_state *render = &sna->render_state.gen8;
+
+ if (render->blend == blend)
+ return;
+
+ DBG(("%s: blend=%x (current=%x), src=%d, dst=%d\n",
+ __FUNCTION__, blend, render->blend,
+ blend / GEN8_BLENDFACTOR_COUNT,
+ blend % GEN8_BLENDFACTOR_COUNT));
+
+ assert(blend < GEN8_BLENDFACTOR_COUNT * GEN8_BLENDFACTOR_COUNT);
+ assert(blend / GEN8_BLENDFACTOR_COUNT > 0);
+ assert(blend % GEN8_BLENDFACTOR_COUNT > 0);
+
+ /* XXX can have upto 8 blend states preload, selectable via
+ * Render Target Index. What other side-effects of Render Target Index?
+ */
+
+ OUT_BATCH(GEN8_3DSTATE_PS_BLEND | (2 - 2));
+ if (blend != GEN8_BLEND(NO_BLEND)) {
+ uint32_t src = blend / GEN8_BLENDFACTOR_COUNT;
+ uint32_t dst = blend % GEN8_BLENDFACTOR_COUNT;
+ OUT_BATCH(PS_BLEND_HAS_WRITEABLE_RT |
+ PS_BLEND_COLOR_BLEND_ENABLE |
+ src << PS_BLEND_SRC_ALPHA_SHIFT |
+ dst << PS_BLEND_DST_ALPHA_SHIFT |
+ src << PS_BLEND_SRC_SHIFT |
+ dst << PS_BLEND_DST_SHIFT);
+ } else
+ OUT_BATCH(PS_BLEND_HAS_WRITEABLE_RT);
+
+ OUT_BATCH(GEN8_3DSTATE_BLEND_STATE_POINTERS | (2 - 2));
+ OUT_BATCH((render->cc_blend + blend * GEN8_BLEND_STATE_PADDED_SIZE) | 1);
+
+ /* Force a CC_STATE pointer change to improve blend performance */
+ OUT_BATCH(GEN8_3DSTATE_CC_STATE_POINTERS | (2 - 2));
+ OUT_BATCH(0);
+
+ render->blend = blend;
+}
+
+static void
+gen8_emit_sampler(struct sna *sna, uint32_t state)
+{
+ if (sna->render_state.gen8.samplers == state)
+ return;
+
+ sna->render_state.gen8.samplers = state;
+
+ DBG(("%s: sampler = %x\n", __FUNCTION__, state));
+
+ assert(2 * sizeof(struct gen8_sampler_state) == 32);
+ OUT_BATCH(GEN8_3DSTATE_SAMPLER_STATE_POINTERS_PS | (2 - 2));
+ OUT_BATCH(sna->render_state.gen8.wm_state + state * 2 * sizeof(struct gen8_sampler_state));
+}
+
+static void
+gen8_emit_sf(struct sna *sna, bool has_mask)
+{
+ int num_sf_outputs = has_mask ? 2 : 1;
+
+ if (sna->render_state.gen8.num_sf_outputs == num_sf_outputs)
+ return;
+
+ DBG(("%s: num_sf_outputs=%d\n", __FUNCTION__, num_sf_outputs));
+
+ sna->render_state.gen8.num_sf_outputs = num_sf_outputs;
+
+ OUT_BATCH(GEN8_3DSTATE_SBE | (4 - 2));
+ OUT_BATCH(num_sf_outputs << SBE_NUM_OUTPUTS_SHIFT |
+ 1 << SBE_URB_ENTRY_READ_LENGTH_SHIFT |
+ 1 << SBE_URB_ENTRY_READ_OFFSET_SHIFT);
+ OUT_BATCH(0);
+ OUT_BATCH(0);
+}
+
+static void
+gen8_emit_wm(struct sna *sna, int kernel)
+{
+ const uint32_t *kernels;
+
+ assert(kernel < ARRAY_SIZE(wm_kernels));
+ if (sna->render_state.gen8.kernel == kernel)
+ return;
+
+ sna->render_state.gen8.kernel = kernel;
+ kernels = sna->render_state.gen8.wm_kernel[kernel];
+
+ DBG(("%s: switching to %s, num_surfaces=%d (8-wide? %d, 16-wide? %d, 32-wide? %d)\n",
+ __FUNCTION__,
+ wm_kernels[kernel].name,
+ wm_kernels[kernel].num_surfaces,
+ kernels[0], kernels[1], kernels[2]));
+
+ OUT_BATCH(GEN8_3DSTATE_PS | (12 - 2));
+ OUT_BATCH64(kernels[0] ?: kernels[1] ?: kernels[2]);
+ OUT_BATCH(1 << PS_SAMPLER_COUNT_SHIFT |
+ //PS_VECTOR_MASK_ENABLE |
+ wm_kernels[kernel].num_surfaces << PS_BINDING_TABLE_ENTRY_COUNT_SHIFT);
+ OUT_BATCH64(0); /* scratch address */
+ OUT_BATCH(PS_MAX_THREADS |
+ (kernels[0] ? PS_8_DISPATCH_ENABLE : 0) |
+ (kernels[1] ? PS_16_DISPATCH_ENABLE : 0) |
+ (kernels[2] ? PS_32_DISPATCH_ENABLE : 0));
+ OUT_BATCH((kernels[0] ? 4 : kernels[1] ? 6 : 8) << PS_DISPATCH_START_GRF_SHIFT_0 |
+ 8 << PS_DISPATCH_START_GRF_SHIFT_1 |
+ 6 << PS_DISPATCH_START_GRF_SHIFT_2);
+ OUT_BATCH64(kernels[2]);
+ OUT_BATCH64(kernels[1]);
+}
+
+static bool
+gen8_emit_binding_table(struct sna *sna, uint16_t offset)
+{
+ if (sna->render_state.gen8.surface_table == offset)
+ return false;
+
+ /* Binding table pointers */
+ assert(is_aligned(4*offset, 32));
+ OUT_BATCH(GEN8_3DSTATE_BINDING_TABLE_POINTERS_PS | (2 - 2));
+ OUT_BATCH(offset*4);
+
+ sna->render_state.gen8.surface_table = offset;
+ return true;
+}
+
+static bool
+gen8_emit_drawing_rectangle(struct sna *sna,
+ const struct sna_composite_op *op)
+{
+ uint32_t limit = (op->dst.height - 1) << 16 | (op->dst.width - 1);
+ uint32_t offset = (uint16_t)op->dst.y << 16 | (uint16_t)op->dst.x;
+
+ assert(!too_large(op->dst.x, op->dst.y));
+ assert(!too_large(op->dst.width, op->dst.height));
+
+ if (sna->render_state.gen8.drawrect_limit == limit &&
+ sna->render_state.gen8.drawrect_offset == offset)
+ return true;
+
+ sna->render_state.gen8.drawrect_offset = offset;
+ sna->render_state.gen8.drawrect_limit = limit;
+
+ OUT_BATCH(GEN8_3DSTATE_DRAWING_RECTANGLE | (4 - 2));
+ OUT_BATCH(0);
+ OUT_BATCH(limit);
+ OUT_BATCH(offset);
+ return false;
+}
+
+static void
+gen8_emit_vertex_elements(struct sna *sna,
+ const struct sna_composite_op *op)
+{
+ /*
+ * vertex data in vertex buffer
+ * position: (x, y)
+ * texture coordinate 0: (u0, v0) if (is_affine is true) else (u0, v0, w0)
+ * texture coordinate 1 if (has_mask is true): same as above
+ */
+ struct gen8_render_state *render = &sna->render_state.gen8;
+ uint32_t src_format, dw;
+ int id = GEN8_VERTEX(op->u.gen8.flags);
+ bool has_mask;
+
+ DBG(("%s: setup id=%d\n", __FUNCTION__, id));
+
+ if (render->ve_id == id)
+ return;
+ render->ve_id = id;
+
+ /* The VUE layout
+ * dword 0-3: pad (0.0, 0.0, 0.0. 0.0)
+ * dword 4-7: position (x, y, 1.0, 1.0),
+ * dword 8-11: texture coordinate 0 (u0, v0, w0, 1.0)
+ * dword 12-15: texture coordinate 1 (u1, v1, w1, 1.0)
+ *
+ * dword 4-15 are fetched from vertex buffer
+ */
+ has_mask = (id >> 2) != 0;
+ OUT_BATCH(GEN8_3DSTATE_VERTEX_ELEMENTS |
+ ((2 * (3 + has_mask)) + 1 - 2));
+
+ OUT_BATCH(id << VE_INDEX_SHIFT | VE_VALID |
+ SURFACEFORMAT_R32G32B32A32_FLOAT << VE_FORMAT_SHIFT |
+ 0 << VE_OFFSET_SHIFT);
+ OUT_BATCH(COMPONENT_STORE_0 << VE_COMPONENT_0_SHIFT |
+ COMPONENT_STORE_0 << VE_COMPONENT_1_SHIFT |
+ COMPONENT_STORE_0 << VE_COMPONENT_2_SHIFT |
+ COMPONENT_STORE_0 << VE_COMPONENT_3_SHIFT);
+
+ /* x,y */
+ OUT_BATCH(id << VE_INDEX_SHIFT | VE_VALID |
+ SURFACEFORMAT_R16G16_SSCALED << VE_FORMAT_SHIFT |
+ 0 << VE_OFFSET_SHIFT);
+ OUT_BATCH(COMPONENT_STORE_SRC << VE_COMPONENT_0_SHIFT |
+ COMPONENT_STORE_SRC << VE_COMPONENT_1_SHIFT |
+ COMPONENT_STORE_0 << VE_COMPONENT_2_SHIFT |
+ COMPONENT_STORE_1_FLT << VE_COMPONENT_3_SHIFT);
+
+ /* u0, v0, w0 */
+ DBG(("%s: first channel %d floats, offset=4\n", __FUNCTION__, id & 3));
+ dw = COMPONENT_STORE_1_FLT << VE_COMPONENT_3_SHIFT;
+ switch (id & 3) {
+ default:
+ assert(0);
+ case 0:
+ src_format = SURFACEFORMAT_R16G16_SSCALED;
+ dw |= COMPONENT_STORE_SRC << VE_COMPONENT_0_SHIFT;
+ dw |= COMPONENT_STORE_SRC << VE_COMPONENT_1_SHIFT;
+ dw |= COMPONENT_STORE_0 << VE_COMPONENT_2_SHIFT;
+ break;
+ case 1:
+ src_format = SURFACEFORMAT_R32_FLOAT;
+ dw |= COMPONENT_STORE_SRC << VE_COMPONENT_0_SHIFT;
+ dw |= COMPONENT_STORE_0 << VE_COMPONENT_1_SHIFT;
+ dw |= COMPONENT_STORE_0 << VE_COMPONENT_2_SHIFT;
+ break;
+ case 2:
+ src_format = SURFACEFORMAT_R32G32_FLOAT;
+ dw |= COMPONENT_STORE_SRC << VE_COMPONENT_0_SHIFT;
+ dw |= COMPONENT_STORE_SRC << VE_COMPONENT_1_SHIFT;
+ dw |= COMPONENT_STORE_0 << VE_COMPONENT_2_SHIFT;
+ break;
+ case 3:
+ src_format = SURFACEFORMAT_R32G32B32_FLOAT;
+ dw |= COMPONENT_STORE_SRC << VE_COMPONENT_0_SHIFT;
+ dw |= COMPONENT_STORE_SRC << VE_COMPONENT_1_SHIFT;
+ dw |= COMPONENT_STORE_SRC << VE_COMPONENT_2_SHIFT;
+ break;
+ }
+ OUT_BATCH(id << VE_INDEX_SHIFT | VE_VALID |
+ src_format << VE_FORMAT_SHIFT |
+ 4 << VE_OFFSET_SHIFT);
+ OUT_BATCH(dw);
+
+ /* u1, v1, w1 */
+ if (has_mask) {
+ unsigned offset = 4 + ((id & 3) ?: 1) * sizeof(float);
+ DBG(("%s: second channel %d floats, offset=%d\n", __FUNCTION__, (id >> 2) & 3, offset));
+ dw = COMPONENT_STORE_1_FLT << VE_COMPONENT_3_SHIFT;
+ switch (id >> 2) {
+ case 1:
+ src_format = SURFACEFORMAT_R32_FLOAT;
+ dw |= COMPONENT_STORE_SRC << VE_COMPONENT_0_SHIFT;
+ dw |= COMPONENT_STORE_0 << VE_COMPONENT_1_SHIFT;
+ dw |= COMPONENT_STORE_0 << VE_COMPONENT_2_SHIFT;
+ break;
+ default:
+ assert(0);
+ case 2:
+ src_format = SURFACEFORMAT_R32G32_FLOAT;
+ dw |= COMPONENT_STORE_SRC << VE_COMPONENT_0_SHIFT;
+ dw |= COMPONENT_STORE_SRC << VE_COMPONENT_1_SHIFT;
+ dw |= COMPONENT_STORE_0 << VE_COMPONENT_2_SHIFT;
+ break;
+ case 3:
+ src_format = SURFACEFORMAT_R32G32B32_FLOAT;
+ dw |= COMPONENT_STORE_SRC << VE_COMPONENT_0_SHIFT;
+ dw |= COMPONENT_STORE_SRC << VE_COMPONENT_1_SHIFT;
+ dw |= COMPONENT_STORE_SRC << VE_COMPONENT_2_SHIFT;
+ break;
+ }
+ OUT_BATCH(id << VE_INDEX_SHIFT | VE_VALID |
+ src_format << VE_FORMAT_SHIFT |
+ offset << VE_OFFSET_SHIFT);
+ OUT_BATCH(dw);
+ }
+}
+
+inline static void
+gen8_emit_pipe_invalidate(struct sna *sna)
+{
+ OUT_BATCH(GEN8_PIPE_CONTROL | (6 - 2));
+ OUT_BATCH(PIPE_CONTROL_WC_FLUSH |
+ PIPE_CONTROL_TC_FLUSH |
+ PIPE_CONTROL_CS_STALL);
+ OUT_BATCH64(0);
+ OUT_BATCH64(0);
+}
+
+inline static void
+gen8_emit_pipe_flush(struct sna *sna, bool need_stall)
+{
+ unsigned stall;
+
+ stall = 0;
+ if (need_stall)
+ stall = (PIPE_CONTROL_CS_STALL |
+ PIPE_CONTROL_STALL_AT_SCOREBOARD);
+
+ OUT_BATCH(GEN8_PIPE_CONTROL | (6 - 2));
+ OUT_BATCH(PIPE_CONTROL_WC_FLUSH | stall);
+ OUT_BATCH64(0);
+ OUT_BATCH64(0);
+}
+
+inline static void
+gen8_emit_pipe_stall(struct sna *sna)
+{
+ OUT_BATCH(GEN8_PIPE_CONTROL | (6 - 2));
+ OUT_BATCH(PIPE_CONTROL_CS_STALL |
+ PIPE_CONTROL_STALL_AT_SCOREBOARD);
+ OUT_BATCH64(0);
+ OUT_BATCH64(0);
+}
+
+static void
+gen8_emit_state(struct sna *sna,
+ const struct sna_composite_op *op,
+ uint16_t wm_binding_table)
+{
+ bool need_invalidate;
+ bool need_flush;
+ bool need_stall;
+
+ assert(op->dst.bo->exec);
+
+ need_flush = wm_binding_table & 1 ||
+ (sna->render_state.gen8.emit_flush && GEN8_READS_DST(op->u.gen8.flags));
+ if (ALWAYS_FLUSH)
+ need_flush = true;
+
+ wm_binding_table &= ~1;
+
+ need_stall = sna->render_state.gen8.surface_table != wm_binding_table;
+
+ need_invalidate = need_stall &&
+ (kgem_bo_is_dirty(op->src.bo) || kgem_bo_is_dirty(op->mask.bo));
+ if (ALWAYS_INVALIDATE)
+ need_invalidate = true;
+
+ need_stall &= gen8_emit_drawing_rectangle(sna, op);
+ if (ALWAYS_STALL)
+ need_stall = true;
+
+ if (need_invalidate) {
+ gen8_emit_pipe_invalidate(sna);
+ kgem_clear_dirty(&sna->kgem);
+ assert(op->dst.bo->exec);
+ kgem_bo_mark_dirty(op->dst.bo);
+
+ need_flush = false;
+ need_stall = false;
+ }
+ if (need_flush) {
+ gen8_emit_pipe_flush(sna, need_stall);
+ need_stall = false;
+ }
+ if (need_stall)
+ gen8_emit_pipe_stall(sna);
+
+ gen8_emit_cc(sna, GEN8_BLEND(op->u.gen8.flags));
+ gen8_emit_sampler(sna, GEN8_SAMPLER(op->u.gen8.flags));
+ gen8_emit_sf(sna, GEN8_VERTEX(op->u.gen8.flags) >> 2);
+ gen8_emit_wm(sna, GEN8_KERNEL(op->u.gen8.flags));
+ gen8_emit_vertex_elements(sna, op);
+ gen8_emit_binding_table(sna, wm_binding_table);
+
+ sna->render_state.gen8.emit_flush = GEN8_READS_DST(op->u.gen8.flags);
+}
+
+static bool gen8_magic_ca_pass(struct sna *sna,
+ const struct sna_composite_op *op)
+{
+ struct gen8_render_state *state = &sna->render_state.gen8;
+
+ if (!op->need_magic_ca_pass)
+ return false;
+
+ DBG(("%s: CA fixup (%d -> %d)\n", __FUNCTION__,
+ sna->render.vertex_start, sna->render.vertex_index));
+
+ gen8_emit_pipe_stall(sna);
+
+ gen8_emit_cc(sna,
+ GEN8_BLEND(gen8_get_blend(PictOpAdd, true,
+ op->dst.format)));
+ gen8_emit_wm(sna,
+ gen8_choose_composite_kernel(PictOpAdd,
+ true, true,
+ op->is_affine));
+
+ OUT_BATCH(GEN8_3DPRIMITIVE | (7- 2));
+ OUT_BATCH(RECTLIST); /* ignored, see VF_TOPOLOGY */
+ OUT_BATCH(sna->render.vertex_index - sna->render.vertex_start);
+ OUT_BATCH(sna->render.vertex_start);
+ OUT_BATCH(1); /* single instance */
+ OUT_BATCH(0); /* start instance location */
+ OUT_BATCH(0); /* index buffer offset, ignored */
+
+ state->last_primitive = sna->kgem.nbatch;
+ return true;
+}
+
+static void null_create(struct sna_static_stream *stream)
+{
+ /* A bunch of zeros useful for legacy border color and depth-stencil */
+ sna_static_stream_map(stream, 64, 64);
+}
+
+static void
+sampler_state_init(struct gen8_sampler_state *sampler_state,
+ sampler_filter_t filter,
+ sampler_extend_t extend)
+{
+ COMPILE_TIME_ASSERT(sizeof(*sampler_state) == 4*sizeof(uint32_t));
+
+ sampler_state->ss0.lod_preclamp = 2; /* GL mode */
+ sampler_state->ss0.default_color_mode = 1;
+
+ switch (filter) {
+ default:
+ case SAMPLER_FILTER_NEAREST:
+ sampler_state->ss0.min_filter = MAPFILTER_NEAREST;
+ sampler_state->ss0.mag_filter = MAPFILTER_NEAREST;
+ break;
+ case SAMPLER_FILTER_BILINEAR:
+ sampler_state->ss0.min_filter = MAPFILTER_LINEAR;
+ sampler_state->ss0.mag_filter = MAPFILTER_LINEAR;
+ break;
+ }
+
+ /* XXX bicubic filter using MAPFILTER_FLEXIBLE */
+
+ switch (extend) {
+ default:
+ case SAMPLER_EXTEND_NONE:
+ sampler_state->ss3.r_wrap_mode = TEXCOORDMODE_CLAMP_BORDER;
+ sampler_state->ss3.s_wrap_mode = TEXCOORDMODE_CLAMP_BORDER;
+ sampler_state->ss3.t_wrap_mode = TEXCOORDMODE_CLAMP_BORDER;
+ break;
+ case SAMPLER_EXTEND_REPEAT:
+ sampler_state->ss3.r_wrap_mode = TEXCOORDMODE_WRAP;
+ sampler_state->ss3.s_wrap_mode = TEXCOORDMODE_WRAP;
+ sampler_state->ss3.t_wrap_mode = TEXCOORDMODE_WRAP;
+ break;
+ case SAMPLER_EXTEND_PAD:
+ sampler_state->ss3.r_wrap_mode = TEXCOORDMODE_CLAMP;
+ sampler_state->ss3.s_wrap_mode = TEXCOORDMODE_CLAMP;
+ sampler_state->ss3.t_wrap_mode = TEXCOORDMODE_CLAMP;
+ break;
+ case SAMPLER_EXTEND_REFLECT:
+ sampler_state->ss3.r_wrap_mode = TEXCOORDMODE_MIRROR;
+ sampler_state->ss3.s_wrap_mode = TEXCOORDMODE_MIRROR;
+ sampler_state->ss3.t_wrap_mode = TEXCOORDMODE_MIRROR;
+ break;
+ }
+}
+
+static void
+sampler_copy_init(struct gen8_sampler_state *ss)
+{
+ sampler_state_init(ss, SAMPLER_FILTER_NEAREST, SAMPLER_EXTEND_NONE);
+ ss->ss3.non_normalized_coord = 1;
+
+ sampler_state_init(ss+1, SAMPLER_FILTER_NEAREST, SAMPLER_EXTEND_NONE);
+}
+
+static void
+sampler_fill_init(struct gen8_sampler_state *ss)
+{
+ sampler_state_init(ss, SAMPLER_FILTER_NEAREST, SAMPLER_EXTEND_REPEAT);
+ ss->ss3.non_normalized_coord = 1;
+
+ sampler_state_init(ss+1, SAMPLER_FILTER_NEAREST, SAMPLER_EXTEND_NONE);
+}
+
+static uint32_t
+gen8_tiling_bits(uint32_t tiling)
+{
+ switch (tiling) {
+ default: assert(0);
+ case I915_TILING_NONE: return 0;
+ case I915_TILING_X: return SURFACE_TILED;
+ case I915_TILING_Y: return SURFACE_TILED | SURFACE_TILED_Y;
+ }
+}
+
+/**
+ * Sets up the common fields for a surface state buffer for the given
+ * picture in the given surface state buffer.
+ */
+static uint32_t
+gen8_bind_bo(struct sna *sna,
+ struct kgem_bo *bo,
+ uint32_t width,
+ uint32_t height,
+ uint32_t format,
+ bool is_dst)
+{
+ uint32_t *ss;
+ uint32_t domains;
+ int offset;
+ uint32_t is_scanout = is_dst && bo->scanout;
+
+ /* After the first bind, we manage the cache domains within the batch */
+ offset = kgem_bo_get_binding(bo, format | is_dst << 30 | is_scanout << 31);
+ if (offset) {
+ if (is_dst)
+ kgem_bo_mark_dirty(bo);
+ return offset * sizeof(uint32_t);
+ }
+
+ offset = sna->kgem.surface -= SURFACE_DW;
+ ss = sna->kgem.batch + offset;
+ ss[0] = (SURFACE_2D << SURFACE_TYPE_SHIFT |
+ gen8_tiling_bits(bo->tiling) |
+ format << SURFACE_FORMAT_SHIFT |
+ SURFACE_VALIGN_4 | SURFACE_HALIGN_4);
+ if (is_dst) {
+ ss[0] |= SURFACE_RC_READ_WRITE;
+ domains = I915_GEM_DOMAIN_RENDER << 16 |I915_GEM_DOMAIN_RENDER;
+ } else
+ domains = I915_GEM_DOMAIN_SAMPLER << 16;
+ ss[1] = (is_scanout || bo->io) ? 0 : 3 << 24;
+ ss[2] = ((width - 1) << SURFACE_WIDTH_SHIFT |
+ (height - 1) << SURFACE_HEIGHT_SHIFT);
+ ss[3] = (bo->pitch - 1) << SURFACE_PITCH_SHIFT;
+ ss[4] = 0;
+ ss[5] = 0;
+ ss[6] = 0;
+ ss[7] = SURFACE_SWIZZLE(RED, GREEN, BLUE, ALPHA);
+ *(uint64_t *)(ss+8) = kgem_add_reloc64(&sna->kgem, offset + 8, bo, domains, 0);
+ ss[10] = 0;
+ ss[11] = 0;
+ ss[12] = 0;
+ ss[13] = 0;
+ ss[14] = 0;
+ ss[15] = 0;
+
+ kgem_bo_set_binding(bo, format | is_dst << 30 | is_scanout << 31, offset);
+
+ DBG(("[%x] bind bo(handle=%d, addr=%d), format=%d, width=%d, height=%d, pitch=%d, tiling=%d -> %s\n",
+ offset, bo->handle, ss[1],
+ format, width, height, bo->pitch, bo->tiling,
+ domains & 0xffff ? "render" : "sampler"));
+
+ return offset * sizeof(uint32_t);
+}
+
+static void gen8_emit_vertex_buffer(struct sna *sna,
+ const struct sna_composite_op *op)
+{
+ int id = GEN8_VERTEX(op->u.gen8.flags);
+
+ OUT_BATCH(GEN8_3DSTATE_VERTEX_BUFFERS | (5 - 2));
+ OUT_BATCH(id << VB_INDEX_SHIFT | VB_MODIFY_ENABLE |
+ 4*op->floats_per_vertex);
+ sna->render.vertex_reloc[sna->render.nvertex_reloc++] = sna->kgem.nbatch;
+ OUT_BATCH64(0);
+ OUT_BATCH(~0); /* buffer size: disabled */
+
+ OUT_BATCH(GEN8_3DSTATE_VF_INSTANCING | (3 - 2));
+ OUT_BATCH(id);
+ OUT_BATCH(0);
+
+ sna->render.vb_id |= 1 << id;
+}
+
+static void gen8_emit_primitive(struct sna *sna)
+{
+ if (sna->kgem.nbatch == sna->render_state.gen8.last_primitive) {
+ sna->render.vertex_offset = sna->kgem.nbatch - 5;
+ return;
+ }
+
+ OUT_BATCH(GEN8_3DPRIMITIVE | (7 - 2));
+ OUT_BATCH(RECTLIST); /* ignored, see VF_TOPOLOGY */
+ sna->render.vertex_offset = sna->kgem.nbatch;
+ OUT_BATCH(0); /* vertex count, to be filled in later */
+ OUT_BATCH(sna->render.vertex_index);
+ OUT_BATCH(1); /* single instance */
+ OUT_BATCH(0); /* start instance location */
+ OUT_BATCH(0); /* index buffer offset, ignored */
+ sna->render.vertex_start = sna->render.vertex_index;
+
+ sna->render_state.gen8.last_primitive = sna->kgem.nbatch;
+}
+
+static bool gen8_rectangle_begin(struct sna *sna,
+ const struct sna_composite_op *op)
+{
+ int id = 1 << GEN8_VERTEX(op->u.gen8.flags);
+ int ndwords;
+
+ if (sna_vertex_wait__locked(&sna->render) && sna->render.vertex_offset)
+ return true;
+
+ ndwords = op->need_magic_ca_pass ? 60 : 6;
+ if ((sna->render.vb_id & id) == 0)
+ ndwords += 5;
+ if (!kgem_check_batch(&sna->kgem, ndwords))
+ return false;
+
+ if ((sna->render.vb_id & id) == 0)
+ gen8_emit_vertex_buffer(sna, op);
+
+ gen8_emit_primitive(sna);
+ return true;
+}
+
+static int gen8_get_rectangles__flush(struct sna *sna,
+ const struct sna_composite_op *op)
+{
+ /* Preventing discarding new vbo after lock contention */
+ if (sna_vertex_wait__locked(&sna->render)) {
+ int rem = vertex_space(sna);
+ if (rem > op->floats_per_rect)
+ return rem;
+ }
+
+ if (!kgem_check_batch(&sna->kgem, op->need_magic_ca_pass ? 65 : 6))
+ return 0;
+ if (!kgem_check_reloc_and_exec(&sna->kgem, 2))
+ return 0;
+
+ if (sna->render.vertex_offset) {
+ gen8_vertex_flush(sna);
+ if (gen8_magic_ca_pass(sna, op)) {
+ gen8_emit_pipe_invalidate(sna);
+ gen8_emit_cc(sna, GEN8_BLEND(op->u.gen8.flags));
+ gen8_emit_wm(sna, GEN8_KERNEL(op->u.gen8.flags));
+ }
+ }
+
+ return gen8_vertex_finish(sna);
+}
+
+inline static int gen8_get_rectangles(struct sna *sna,
+ const struct sna_composite_op *op,
+ int want,
+ void (*emit_state)(struct sna *sna, const struct sna_composite_op *op))
+{
+ int rem;
+
+ assert(want);
+
+start:
+ rem = vertex_space(sna);
+ if (unlikely(rem < op->floats_per_rect)) {
+ DBG(("flushing vbo for %s: %d < %d\n",
+ __FUNCTION__, rem, op->floats_per_rect));
+ rem = gen8_get_rectangles__flush(sna, op);
+ if (unlikely(rem == 0))
+ goto flush;
+ }
+
+ if (unlikely(sna->render.vertex_offset == 0)) {
+ if (!gen8_rectangle_begin(sna, op))
+ goto flush;
+ else
+ goto start;
+ }
+
+ assert(rem <= vertex_space(sna));
+ assert(op->floats_per_rect <= rem);
+ if (want > 1 && want * op->floats_per_rect > rem)
+ want = rem / op->floats_per_rect;
+
+ assert(want > 0);
+ sna->render.vertex_index += 3*want;
+ return want;
+
+flush:
+ if (sna->render.vertex_offset) {
+ gen8_vertex_flush(sna);
+ gen8_magic_ca_pass(sna, op);
+ }
+ sna_vertex_wait__locked(&sna->render);
+ _kgem_submit(&sna->kgem);
+ emit_state(sna, op);
+ goto start;
+}
+
+inline static uint32_t *gen8_composite_get_binding_table(struct sna *sna,
+ uint16_t *offset)
+{
+ uint32_t *table;
+
+ assert(sna->kgem.surface <= 16384);
+ sna->kgem.surface -= SURFACE_DW;
+ /* Clear all surplus entries to zero in case of prefetch */
+ table = memset(sna->kgem.batch + sna->kgem.surface, 0, 64);
+
+ DBG(("%s(%x)\n", __FUNCTION__, 4*sna->kgem.surface));
+
+ *offset = sna->kgem.surface;
+ return table;
+}
+
+static void
+gen8_get_batch(struct sna *sna, const struct sna_composite_op *op)
+{
+ kgem_set_mode(&sna->kgem, KGEM_RENDER, op->dst.bo);
+
+ if (!kgem_check_batch_with_surfaces(&sna->kgem, 150, 2*(1+3))) {
+ DBG(("%s: flushing batch: %d < %d+%d\n",
+ __FUNCTION__, sna->kgem.surface - sna->kgem.nbatch,
+ 150, 4*8*2));
+ _kgem_submit(&sna->kgem);
+ _kgem_set_mode(&sna->kgem, KGEM_RENDER);
+ }
+
+ assert(sna->kgem.mode == KGEM_RENDER);
+ assert(sna->kgem.ring == KGEM_RENDER);
+
+ if (sna->render_state.gen8.needs_invariant)
+ gen8_emit_invariant(sna);
+}
+
+static void gen8_emit_composite_state(struct sna *sna,
+ const struct sna_composite_op *op)
+{
+ uint32_t *binding_table;
+ uint16_t offset, dirty;
+
+ gen8_get_batch(sna, op);
+
+ binding_table = gen8_composite_get_binding_table(sna, &offset);
+
+ dirty = kgem_bo_is_dirty(op->dst.bo);
+
+ binding_table[0] =
+ gen8_bind_bo(sna,
+ op->dst.bo, op->dst.width, op->dst.height,
+ gen8_get_dest_format(op->dst.format),
+ true);
+ binding_table[1] =
+ gen8_bind_bo(sna,
+ op->src.bo, op->src.width, op->src.height,
+ op->src.card_format,
+ false);
+ if (op->mask.bo) {
+ binding_table[2] =
+ gen8_bind_bo(sna,
+ op->mask.bo,
+ op->mask.width,
+ op->mask.height,
+ op->mask.card_format,
+ false);
+ }
+
+ if (sna->kgem.surface == offset &&
+ *(uint64_t *)(sna->kgem.batch + sna->render_state.gen8.surface_table) == *(uint64_t*)binding_table &&
+ (op->mask.bo == NULL ||
+ sna->kgem.batch[sna->render_state.gen8.surface_table+2] == binding_table[2])) {
+ sna->kgem.surface += SURFACE_DW;
+ offset = sna->render_state.gen8.surface_table;
+ }
+
+ if (sna->kgem.batch[sna->render_state.gen8.surface_table] == binding_table[0])
+ dirty = 0;
+
+ gen8_emit_state(sna, op, offset | dirty);
+}
+
+static void
+gen8_align_vertex(struct sna *sna, const struct sna_composite_op *op)
+{
+ if (op->floats_per_vertex != sna->render_state.gen8.floats_per_vertex) {
+ DBG(("aligning vertex: was %d, now %d floats per vertex\n",
+ sna->render_state.gen8.floats_per_vertex, op->floats_per_vertex));
+ gen8_vertex_align(sna, op);
+ sna->render_state.gen8.floats_per_vertex = op->floats_per_vertex;
+ }
+}
+
+fastcall static void
+gen8_render_composite_blt(struct sna *sna,
+ const struct sna_composite_op *op,
+ const struct sna_composite_rectangles *r)
+{
+ gen8_get_rectangles(sna, op, 1, gen8_emit_composite_state);
+ op->prim_emit(sna, op, r);
+}
+
+fastcall static void
+gen8_render_composite_box(struct sna *sna,
+ const struct sna_composite_op *op,
+ const BoxRec *box)
+{
+ struct sna_composite_rectangles r;
+
+ gen8_get_rectangles(sna, op, 1, gen8_emit_composite_state);
+
+ DBG((" %s: (%d, %d), (%d, %d)\n",
+ __FUNCTION__,
+ box->x1, box->y1, box->x2, box->y2));
+
+ r.dst.x = box->x1;
+ r.dst.y = box->y1;
+ r.width = box->x2 - box->x1;
+ r.height = box->y2 - box->y1;
+ r.src = r.mask = r.dst;
+
+ op->prim_emit(sna, op, &r);
+}
+
+static void
+gen8_render_composite_boxes__blt(struct sna *sna,
+ const struct sna_composite_op *op,
+ const BoxRec *box, int nbox)
+{
+ DBG(("composite_boxes(%d)\n", nbox));
+
+ do {
+ int nbox_this_time;
+
+ nbox_this_time = gen8_get_rectangles(sna, op, nbox,
+ gen8_emit_composite_state);
+ nbox -= nbox_this_time;
+
+ do {
+ struct sna_composite_rectangles r;
+
+ DBG((" %s: (%d, %d), (%d, %d)\n",
+ __FUNCTION__,
+ box->x1, box->y1, box->x2, box->y2));
+
+ r.dst.x = box->x1;
+ r.dst.y = box->y1;
+ r.width = box->x2 - box->x1;
+ r.height = box->y2 - box->y1;
+ r.src = r.mask = r.dst;
+
+ op->prim_emit(sna, op, &r);
+ box++;
+ } while (--nbox_this_time);
+ } while (nbox);
+}
+
+static void
+gen8_render_composite_boxes(struct sna *sna,
+ const struct sna_composite_op *op,
+ const BoxRec *box, int nbox)
+{
+ DBG(("%s: nbox=%d\n", __FUNCTION__, nbox));
+
+ do {
+ int nbox_this_time;
+ float *v;
+
+ nbox_this_time = gen8_get_rectangles(sna, op, nbox,
+ gen8_emit_composite_state);
+ assert(nbox_this_time);
+ nbox -= nbox_this_time;
+
+ v = sna->render.vertices + sna->render.vertex_used;
+ sna->render.vertex_used += nbox_this_time * op->floats_per_rect;
+
+ op->emit_boxes(op, box, nbox_this_time, v);
+ box += nbox_this_time;
+ } while (nbox);
+}
+
+static void
+gen8_render_composite_boxes__thread(struct sna *sna,
+ const struct sna_composite_op *op,
+ const BoxRec *box, int nbox)
+{
+ DBG(("%s: nbox=%d\n", __FUNCTION__, nbox));
+
+ sna_vertex_lock(&sna->render);
+ do {
+ int nbox_this_time;
+ float *v;
+
+ nbox_this_time = gen8_get_rectangles(sna, op, nbox,
+ gen8_emit_composite_state);
+ assert(nbox_this_time);
+ nbox -= nbox_this_time;
+
+ v = sna->render.vertices + sna->render.vertex_used;
+ sna->render.vertex_used += nbox_this_time * op->floats_per_rect;
+
+ sna_vertex_acquire__locked(&sna->render);
+ sna_vertex_unlock(&sna->render);
+
+ op->emit_boxes(op, box, nbox_this_time, v);
+ box += nbox_this_time;
+
+ sna_vertex_lock(&sna->render);
+ sna_vertex_release__locked(&sna->render);
+ } while (nbox);
+ sna_vertex_unlock(&sna->render);
+}
+
+static uint32_t
+gen8_create_blend_state(struct sna_static_stream *stream)
+{
+ char *base, *ptr;
+ int src, dst;
+
+ COMPILE_TIME_ASSERT(((GEN8_BLENDFACTOR_COUNT * GEN8_BLENDFACTOR_COUNT << 4) & (1 << 15)) == 0);
+
+ base = sna_static_stream_map(stream,
+ GEN8_BLENDFACTOR_COUNT * GEN8_BLENDFACTOR_COUNT * GEN8_BLEND_STATE_PADDED_SIZE,
+ 64);
+
+ ptr = base;
+ for (src = 0; src < GEN8_BLENDFACTOR_COUNT; src++) {
+ for (dst = 0; dst < GEN8_BLENDFACTOR_COUNT; dst++) {
+ struct gen8_blend_state *blend =
+ (struct gen8_blend_state *)ptr;
+
+ assert(((ptr - base) & 63) == 0);
+ COMPILE_TIME_ASSERT(sizeof(blend->common) == 4);
+ COMPILE_TIME_ASSERT(sizeof(blend->rt) == 8);
+
+ blend->rt.post_blend_clamp = 1;
+ blend->rt.pre_blend_clamp = 1;
+
+ blend->rt.color_blend =
+ !(dst == BLENDFACTOR_ZERO && src == BLENDFACTOR_ONE);
+ blend->rt.dest_blend_factor = dst;
+ blend->rt.source_blend_factor = src;
+ blend->rt.color_blend_function = BLENDFUNCTION_ADD;
+
+ blend->rt.dest_alpha_blend_factor = dst;
+ blend->rt.source_alpha_blend_factor = src;
+ blend->rt.alpha_blend_function = BLENDFUNCTION_ADD;
+
+ ptr += GEN8_BLEND_STATE_PADDED_SIZE;
+ }
+ }
+
+ return sna_static_stream_offsetof(stream, base);
+}
+
+static int
+gen8_composite_picture(struct sna *sna,
+ PicturePtr picture,
+ struct sna_composite_channel *channel,
+ int x, int y,
+ int w, int h,
+ int dst_x, int dst_y,
+ bool precise)
+{
+ PixmapPtr pixmap;
+ uint32_t color;
+ int16_t dx, dy;
+
+ DBG(("%s: (%d, %d)x(%d, %d), dst=(%d, %d)\n",
+ __FUNCTION__, x, y, w, h, dst_x, dst_y));
+
+ channel->is_solid = false;
+ channel->card_format = -1;
+
+ if (sna_picture_is_solid(picture, &color))
+ return gen4_channel_init_solid(sna, channel, color);
+
+ if (picture->pDrawable == NULL) {
+ int ret;
+
+ if (picture->pSourcePict->type == SourcePictTypeLinear)
+ return gen4_channel_init_linear(sna, picture, channel,
+ x, y,
+ w, h,
+ dst_x, dst_y);
+
+ DBG(("%s -- fixup, gradient\n", __FUNCTION__));
+ ret = -1;
+ if (!precise)
+ ret = sna_render_picture_approximate_gradient(sna, picture, channel,
+ x, y, w, h, dst_x, dst_y);
+ if (ret == -1)
+ ret = sna_render_picture_fixup(sna, picture, channel,
+ x, y, w, h, dst_x, dst_y);
+ return ret;
+ }
+
+ if (picture->alphaMap) {
+ DBG(("%s -- fallback, alphamap\n", __FUNCTION__));
+ return sna_render_picture_fixup(sna, picture, channel,
+ x, y, w, h, dst_x, dst_y);
+ }
+
+ if (!gen8_check_repeat(picture))
+ return sna_render_picture_fixup(sna, picture, channel,
+ x, y, w, h, dst_x, dst_y);
+
+ if (!gen8_check_filter(picture))
+ return sna_render_picture_fixup(sna, picture, channel,
+ x, y, w, h, dst_x, dst_y);
+
+ channel->repeat = picture->repeat ? picture->repeatType : RepeatNone;
+ channel->filter = picture->filter;
+
+ pixmap = get_drawable_pixmap(picture->pDrawable);
+ get_drawable_deltas(picture->pDrawable, pixmap, &dx, &dy);
+
+ x += dx + picture->pDrawable->x;
+ y += dy + picture->pDrawable->y;
+
+ channel->is_affine = sna_transform_is_affine(picture->transform);
+ if (sna_transform_is_integer_translation(picture->transform, &dx, &dy)) {
+ DBG(("%s: integer translation (%d, %d), removing\n",
+ __FUNCTION__, dx, dy));
+ x += dx;
+ y += dy;
+ channel->transform = NULL;
+ channel->filter = PictFilterNearest;
+ } else
+ channel->transform = picture->transform;
+
+ channel->pict_format = picture->format;
+ channel->card_format = gen8_get_card_format(picture->format);
+ if (channel->card_format == (unsigned)-1)
+ return sna_render_picture_convert(sna, picture, channel, pixmap,
+ x, y, w, h, dst_x, dst_y,
+ false);
+
+ if (too_large(pixmap->drawable.width, pixmap->drawable.height)) {
+ DBG(("%s: extracting from pixmap %dx%d\n", __FUNCTION__,
+ pixmap->drawable.width, pixmap->drawable.height));
+ return sna_render_picture_extract(sna, picture, channel,
+ x, y, w, h, dst_x, dst_y);
+ }
+
+ return sna_render_pixmap_bo(sna, channel, pixmap,
+ x, y, w, h, dst_x, dst_y);
+}
+
+static void gen8_composite_channel_convert(struct sna_composite_channel *channel)
+{
+ channel->repeat = gen8_repeat(channel->repeat);
+ channel->filter = gen8_filter(channel->filter);
+ if (channel->card_format == (unsigned)-1)
+ channel->card_format = gen8_get_card_format(channel->pict_format);
+ assert(channel->card_format != (unsigned)-1);
+}
+
+static void gen8_render_composite_done(struct sna *sna,
+ const struct sna_composite_op *op)
+{
+ if (sna->render.vertex_offset) {
+ gen8_vertex_flush(sna);
+ gen8_magic_ca_pass(sna, op);
+ }
+
+ if (op->mask.bo)
+ kgem_bo_destroy(&sna->kgem, op->mask.bo);
+ if (op->src.bo)
+ kgem_bo_destroy(&sna->kgem, op->src.bo);
+
+ sna_render_composite_redirect_done(sna, op);
+}
+
+static bool
+gen8_composite_set_target(struct sna *sna,
+ struct sna_composite_op *op,
+ PicturePtr dst,
+ int x, int y, int w, int h,
+ bool partial)
+{
+ BoxRec box;
+
+ op->dst.pixmap = get_drawable_pixmap(dst->pDrawable);
+ op->dst.format = dst->format;
+ op->dst.width = op->dst.pixmap->drawable.width;
+ op->dst.height = op->dst.pixmap->drawable.height;
+
+ if (w | h) {
+ assert(w && h);
+ box.x1 = x;
+ box.y1 = y;
+ box.x2 = x + w;
+ box.y2 = y + h;
+ } else
+ sna_render_picture_extents(dst, &box);
+
+ op->dst.bo = sna_drawable_use_bo(dst->pDrawable,
+ PREFER_GPU | FORCE_GPU | RENDER_GPU,
+ &box, &op->damage);
+ if (op->dst.bo == NULL)
+ return false;
+
+ get_drawable_deltas(dst->pDrawable, op->dst.pixmap,
+ &op->dst.x, &op->dst.y);
+
+ DBG(("%s: pixmap=%p, format=%08x, size=%dx%d, pitch=%d, delta=(%d,%d),damage=%p\n",
+ __FUNCTION__,
+ op->dst.pixmap, (int)op->dst.format,
+ op->dst.width, op->dst.height,
+ op->dst.bo->pitch,
+ op->dst.x, op->dst.y,
+ op->damage ? *op->damage : (void *)-1));
+
+ assert(op->dst.bo->proxy == NULL);
+
+ if (too_large(op->dst.width, op->dst.height) &&
+ !sna_render_composite_redirect(sna, op, x, y, w, h, partial))
+ return false;
+
+ return true;
+}
+
+static bool
+try_blt(struct sna *sna,
+ PicturePtr dst, PicturePtr src,
+ int width, int height)
+{
+ struct kgem_bo *bo;
+
+ if (sna->kgem.mode == KGEM_BLT) {
+ DBG(("%s: already performing BLT\n", __FUNCTION__));
+ return true;
+ }
+
+ if (too_large(width, height)) {
+ DBG(("%s: operation too large for 3D pipe (%d, %d)\n",
+ __FUNCTION__, width, height));
+ return true;
+ }
+
+ bo = __sna_drawable_peek_bo(dst->pDrawable);
+ if (bo && bo->rq)
+ return RQ_IS_BLT(bo->rq);
+
+ if (sna_picture_is_solid(src, NULL) && can_switch_to_blt(sna, NULL, 0))
+ return true;
+
+ if (src->pDrawable) {
+ bo = __sna_drawable_peek_bo(src->pDrawable);
+ if (bo && bo->rq)
+ return RQ_IS_BLT(bo->rq);
+ }
+
+ if (sna->kgem.ring == KGEM_BLT) {
+ DBG(("%s: already performing BLT\n", __FUNCTION__));
+ return true;
+ }
+
+ return false;
+}
+
+static bool
+check_gradient(PicturePtr picture, bool precise)
+{
+ if (picture->pDrawable)
+ return false;
+
+ switch (picture->pSourcePict->type) {
+ case SourcePictTypeSolidFill:
+ case SourcePictTypeLinear:
+ return false;
+ default:
+ return precise;
+ }
+}
+
+static bool
+has_alphamap(PicturePtr p)
+{
+ return p->alphaMap != NULL;
+}
+
+static bool
+need_upload(PicturePtr p)
+{
+ return p->pDrawable && unattached(p->pDrawable) && untransformed(p);
+}
+
+static bool
+source_is_busy(PixmapPtr pixmap)
+{
+ struct sna_pixmap *priv = sna_pixmap(pixmap);
+ if (priv == NULL || priv->clear)
+ return false;
+
+ if (priv->gpu_bo && kgem_bo_is_busy(priv->gpu_bo))
+ return true;
+
+ if (priv->cpu_bo && kgem_bo_is_busy(priv->cpu_bo))
+ return true;
+
+ return priv->gpu_damage && !priv->cpu_damage;
+}
+
+static bool
+source_fallback(PicturePtr p, PixmapPtr pixmap, bool precise)
+{
+ if (sna_picture_is_solid(p, NULL))
+ return false;
+
+ if (p->pSourcePict)
+ return check_gradient(p, precise);
+
+ if (!gen8_check_repeat(p) || !gen8_check_format(p->format))
+ return true;
+
+ if (pixmap && source_is_busy(pixmap))
+ return false;
+
+ return has_alphamap(p) || !gen8_check_filter(p) || need_upload(p);
+}
+
+static bool
+gen8_composite_fallback(struct sna *sna,
+ PicturePtr src,
+ PicturePtr mask,
+ PicturePtr dst)
+{
+ PixmapPtr src_pixmap;
+ PixmapPtr mask_pixmap;
+ PixmapPtr dst_pixmap;
+ bool src_fallback, mask_fallback;
+
+ if (!gen8_check_dst_format(dst->format)) {
+ DBG(("%s: unknown destination format: %d\n",
+ __FUNCTION__, dst->format));
+ return true;
+ }
+
+ dst_pixmap = get_drawable_pixmap(dst->pDrawable);
+
+ src_pixmap = src->pDrawable ? get_drawable_pixmap(src->pDrawable) : NULL;
+ src_fallback = source_fallback(src, src_pixmap,
+ dst->polyMode == PolyModePrecise);
+
+ if (mask) {
+ mask_pixmap = mask->pDrawable ? get_drawable_pixmap(mask->pDrawable) : NULL;
+ mask_fallback = source_fallback(mask, mask_pixmap,
+ dst->polyMode == PolyModePrecise);
+ } else {
+ mask_pixmap = NULL;
+ mask_fallback = false;
+ }
+
+ /* If we are using the destination as a source and need to
+ * readback in order to upload the source, do it all
+ * on the cpu.
+ */
+ if (src_pixmap == dst_pixmap && src_fallback) {
+ DBG(("%s: src is dst and will fallback\n",__FUNCTION__));
+ return true;
+ }
+ if (mask_pixmap == dst_pixmap && mask_fallback) {
+ DBG(("%s: mask is dst and will fallback\n",__FUNCTION__));
+ return true;
+ }
+
+ /* If anything is on the GPU, push everything out to the GPU */
+ if (dst_use_gpu(dst_pixmap)) {
+ DBG(("%s: dst is already on the GPU, try to use GPU\n",
+ __FUNCTION__));
+ return false;
+ }
+
+ if (src_pixmap && !src_fallback) {
+ DBG(("%s: src is already on the GPU, try to use GPU\n",
+ __FUNCTION__));
+ return false;
+ }
+ if (mask_pixmap && !mask_fallback) {
+ DBG(("%s: mask is already on the GPU, try to use GPU\n",
+ __FUNCTION__));
+ return false;
+ }
+
+ /* However if the dst is not on the GPU and we need to
+ * render one of the sources using the CPU, we may
+ * as well do the entire operation in place onthe CPU.
+ */
+ if (src_fallback) {
+ DBG(("%s: dst is on the CPU and src will fallback\n",
+ __FUNCTION__));
+ return true;
+ }
+
+ if (mask && mask_fallback) {
+ DBG(("%s: dst is on the CPU and mask will fallback\n",
+ __FUNCTION__));
+ return true;
+ }
+
+ if (too_large(dst_pixmap->drawable.width,
+ dst_pixmap->drawable.height) &&
+ dst_is_cpu(dst_pixmap)) {
+ DBG(("%s: dst is on the CPU and too large\n", __FUNCTION__));
+ return true;
+ }
+
+ DBG(("%s: dst is not on the GPU and the operation should not fallback\n",
+ __FUNCTION__));
+ return dst_use_cpu(dst_pixmap);
+}
+
+static int
+reuse_source(struct sna *sna,
+ PicturePtr src, struct sna_composite_channel *sc, int src_x, int src_y,
+ PicturePtr mask, struct sna_composite_channel *mc, int msk_x, int msk_y)
+{
+ uint32_t color;
+
+ if (src_x != msk_x || src_y != msk_y)
+ return false;
+
+ if (src == mask) {
+ DBG(("%s: mask is source\n", __FUNCTION__));
+ *mc = *sc;
+ mc->bo = kgem_bo_reference(mc->bo);
+ return true;
+ }
+
+ if (sna_picture_is_solid(mask, &color))
+ return gen4_channel_init_solid(sna, mc, color);
+
+ if (sc->is_solid)
+ return false;
+
+ if (src->pDrawable == NULL || mask->pDrawable != src->pDrawable)
+ return false;
+
+ DBG(("%s: mask reuses source drawable\n", __FUNCTION__));
+
+ if (!sna_transform_equal(src->transform, mask->transform))
+ return false;
+
+ if (!sna_picture_alphamap_equal(src, mask))
+ return false;
+
+ if (!gen8_check_repeat(mask))
+ return false;
+
+ if (!gen8_check_filter(mask))
+ return false;
+
+ if (!gen8_check_format(mask->format))
+ return false;
+
+ DBG(("%s: reusing source channel for mask with a twist\n",
+ __FUNCTION__));
+
+ *mc = *sc;
+ mc->repeat = gen8_repeat(mask->repeat ? mask->repeatType : RepeatNone);
+ mc->filter = gen8_filter(mask->filter);
+ mc->pict_format = mask->format;
+ mc->card_format = gen8_get_card_format(mask->format);
+ mc->bo = kgem_bo_reference(mc->bo);
+ return true;
+}
+
+static bool
+gen8_render_composite(struct sna *sna,
+ uint8_t op,
+ PicturePtr src,
+ PicturePtr mask,
+ PicturePtr dst,
+ int16_t src_x, int16_t src_y,
+ int16_t msk_x, int16_t msk_y,
+ int16_t dst_x, int16_t dst_y,
+ int16_t width, int16_t height,
+ struct sna_composite_op *tmp)
+{
+ if (op >= ARRAY_SIZE(gen8_blend_op))
+ return false;
+
+ DBG(("%s: %dx%d, current mode=%d/%d\n", __FUNCTION__,
+ width, height, sna->kgem.mode, sna->kgem.ring));
+
+ if (mask == NULL &&
+ try_blt(sna, dst, src, width, height) &&
+ sna_blt_composite(sna, op,
+ src, dst,
+ src_x, src_y,
+ dst_x, dst_y,
+ width, height,
+ tmp, false))
+ return true;
+
+ if (gen8_composite_fallback(sna, src, mask, dst))
+ goto fallback;
+
+ if (need_tiling(sna, width, height))
+ return sna_tiling_composite(op, src, mask, dst,
+ src_x, src_y,
+ msk_x, msk_y,
+ dst_x, dst_y,
+ width, height,
+ tmp);
+
+ if (op == PictOpClear && src == sna->clear)
+ op = PictOpSrc;
+ tmp->op = op;
+ if (!gen8_composite_set_target(sna, tmp, dst,
+ dst_x, dst_y, width, height,
+ op > PictOpSrc || dst->pCompositeClip->data))
+ goto fallback;
+
+ switch (gen8_composite_picture(sna, src, &tmp->src,
+ src_x, src_y,
+ width, height,
+ dst_x, dst_y,
+ dst->polyMode == PolyModePrecise)) {
+ case -1:
+ goto cleanup_dst;
+ case 0:
+ if (!gen4_channel_init_solid(sna, &tmp->src, 0))
+ goto cleanup_dst;
+ /* fall through to fixup */
+ case 1:
+ /* Did we just switch rings to prepare the source? */
+ if (mask == NULL &&
+ prefer_blt_composite(sna, tmp) &&
+ sna_blt_composite__convert(sna,
+ dst_x, dst_y, width, height,
+ tmp))
+ return true;
+
+ gen8_composite_channel_convert(&tmp->src);
+ break;
+ }
+
+ tmp->is_affine = tmp->src.is_affine;
+ tmp->has_component_alpha = false;
+ tmp->need_magic_ca_pass = false;
+
+ tmp->mask.bo = NULL;
+ tmp->mask.filter = SAMPLER_FILTER_NEAREST;
+ tmp->mask.repeat = SAMPLER_EXTEND_NONE;
+
+ if (mask) {
+ if (mask->componentAlpha && PICT_FORMAT_RGB(mask->format)) {
+ tmp->has_component_alpha = true;
+
+ /* Check if it's component alpha that relies on a source alpha and on
+ * the source value. We can only get one of those into the single
+ * source value that we get to blend with.
+ */
+ if (gen8_blend_op[op].src_alpha &&
+ (gen8_blend_op[op].src_blend != BLENDFACTOR_ZERO)) {
+ if (op != PictOpOver)
+ goto cleanup_src;
+
+ tmp->need_magic_ca_pass = true;
+ tmp->op = PictOpOutReverse;
+ }
+ }
+
+ if (!reuse_source(sna,
+ src, &tmp->src, src_x, src_y,
+ mask, &tmp->mask, msk_x, msk_y)) {
+ switch (gen8_composite_picture(sna, mask, &tmp->mask,
+ msk_x, msk_y,
+ width, height,
+ dst_x, dst_y,
+ dst->polyMode == PolyModePrecise)) {
+ case -1:
+ goto cleanup_src;
+ case 0:
+ if (!gen4_channel_init_solid(sna, &tmp->mask, 0))
+ goto cleanup_src;
+ /* fall through to fixup */
+ case 1:
+ gen8_composite_channel_convert(&tmp->mask);
+ break;
+ }
+ }
+
+ tmp->is_affine &= tmp->mask.is_affine;
+ }
+
+ tmp->u.gen8.flags =
+ GEN8_SET_FLAGS(SAMPLER_OFFSET(tmp->src.filter,
+ tmp->src.repeat,
+ tmp->mask.filter,
+ tmp->mask.repeat),
+ gen8_get_blend(tmp->op,
+ tmp->has_component_alpha,
+ tmp->dst.format),
+ gen8_choose_composite_kernel(tmp->op,
+ tmp->mask.bo != NULL,
+ tmp->has_component_alpha,
+ tmp->is_affine),
+ gen4_choose_composite_emitter(sna, tmp));
+
+ tmp->blt = gen8_render_composite_blt;
+ tmp->box = gen8_render_composite_box;
+ tmp->boxes = gen8_render_composite_boxes__blt;
+ if (tmp->emit_boxes){
+ tmp->boxes = gen8_render_composite_boxes;
+ tmp->thread_boxes = gen8_render_composite_boxes__thread;
+ }
+ tmp->done = gen8_render_composite_done;
+
+ kgem_set_mode(&sna->kgem, KGEM_RENDER, tmp->dst.bo);
+ if (!kgem_check_bo(&sna->kgem,
+ tmp->dst.bo, tmp->src.bo, tmp->mask.bo,
+ NULL)) {
+ kgem_submit(&sna->kgem);
+ if (!kgem_check_bo(&sna->kgem,
+ tmp->dst.bo, tmp->src.bo, tmp->mask.bo,
+ NULL))
+ goto cleanup_mask;
+ _kgem_set_mode(&sna->kgem, KGEM_RENDER);
+ }
+
+ gen8_align_vertex(sna, tmp);
+ gen8_emit_composite_state(sna, tmp);
+ return true;
+
+cleanup_mask:
+ if (tmp->mask.bo) {
+ kgem_bo_destroy(&sna->kgem, tmp->mask.bo);
+ tmp->mask.bo = NULL;
+ }
+cleanup_src:
+ if (tmp->src.bo) {
+ kgem_bo_destroy(&sna->kgem, tmp->src.bo);
+ tmp->src.bo = NULL;
+ }
+cleanup_dst:
+ if (tmp->redirect.real_bo) {
+ kgem_bo_destroy(&sna->kgem, tmp->dst.bo);
+ tmp->redirect.real_bo = NULL;
+ }
+fallback:
+ return (mask == NULL &&
+ sna_blt_composite(sna, op,
+ src, dst,
+ src_x, src_y,
+ dst_x, dst_y,
+ width, height,
+ tmp, true));
+}
+
+#if !NO_COMPOSITE_SPANS
+fastcall static void
+gen8_render_composite_spans_box(struct sna *sna,
+ const struct sna_composite_spans_op *op,
+ const BoxRec *box, float opacity)
+{
+ DBG(("%s: src=+(%d, %d), opacity=%f, dst=+(%d, %d), box=(%d, %d) x (%d, %d)\n",
+ __FUNCTION__,
+ op->base.src.offset[0], op->base.src.offset[1],
+ opacity,
+ op->base.dst.x, op->base.dst.y,
+ box->x1, box->y1,
+ box->x2 - box->x1,
+ box->y2 - box->y1));
+
+ gen8_get_rectangles(sna, &op->base, 1, gen8_emit_composite_state);
+ op->prim_emit(sna, op, box, opacity);
+}
+
+static void
+gen8_render_composite_spans_boxes(struct sna *sna,
+ const struct sna_composite_spans_op *op,
+ const BoxRec *box, int nbox,
+ float opacity)
+{
+ DBG(("%s: nbox=%d, src=+(%d, %d), opacity=%f, dst=+(%d, %d)\n",
+ __FUNCTION__, nbox,
+ op->base.src.offset[0], op->base.src.offset[1],
+ opacity,
+ op->base.dst.x, op->base.dst.y));
+
+ do {
+ int nbox_this_time;
+
+ nbox_this_time = gen8_get_rectangles(sna, &op->base, nbox,
+ gen8_emit_composite_state);
+ nbox -= nbox_this_time;
+
+ do {
+ DBG((" %s: (%d, %d) x (%d, %d)\n", __FUNCTION__,
+ box->x1, box->y1,
+ box->x2 - box->x1,
+ box->y2 - box->y1));
+
+ op->prim_emit(sna, op, box++, opacity);
+ } while (--nbox_this_time);
+ } while (nbox);
+}
+
+fastcall static void
+gen8_render_composite_spans_boxes__thread(struct sna *sna,
+ const struct sna_composite_spans_op *op,
+ const struct sna_opacity_box *box,
+ int nbox)
+{
+ DBG(("%s: nbox=%d, src=+(%d, %d), dst=+(%d, %d)\n",
+ __FUNCTION__, nbox,
+ op->base.src.offset[0], op->base.src.offset[1],
+ op->base.dst.x, op->base.dst.y));
+
+ sna_vertex_lock(&sna->render);
+ do {
+ int nbox_this_time;
+ float *v;
+
+ nbox_this_time = gen8_get_rectangles(sna, &op->base, nbox,
+ gen8_emit_composite_state);
+ assert(nbox_this_time);
+ nbox -= nbox_this_time;
+
+ v = sna->render.vertices + sna->render.vertex_used;
+ sna->render.vertex_used += nbox_this_time * op->base.floats_per_rect;
+
+ sna_vertex_acquire__locked(&sna->render);
+ sna_vertex_unlock(&sna->render);
+
+ op->emit_boxes(op, box, nbox_this_time, v);
+ box += nbox_this_time;
+
+ sna_vertex_lock(&sna->render);
+ sna_vertex_release__locked(&sna->render);
+ } while (nbox);
+ sna_vertex_unlock(&sna->render);
+}
+
+fastcall static void
+gen8_render_composite_spans_done(struct sna *sna,
+ const struct sna_composite_spans_op *op)
+{
+ if (sna->render.vertex_offset)
+ gen8_vertex_flush(sna);
+
+ DBG(("%s()\n", __FUNCTION__));
+
+ if (op->base.src.bo)
+ kgem_bo_destroy(&sna->kgem, op->base.src.bo);
+
+ sna_render_composite_redirect_done(sna, &op->base);
+}
+
+static bool
+gen8_check_composite_spans(struct sna *sna,
+ uint8_t op, PicturePtr src, PicturePtr dst,
+ int16_t width, int16_t height, unsigned flags)
+{
+ if (op >= ARRAY_SIZE(gen8_blend_op))
+ return false;
+
+ if (gen8_composite_fallback(sna, src, NULL, dst))
+ return false;
+
+ if (need_tiling(sna, width, height) &&
+ !is_gpu(sna, dst->pDrawable, PREFER_GPU_SPANS)) {
+ DBG(("%s: fallback, tiled operation not on GPU\n",
+ __FUNCTION__));
+ return false;
+ }
+
+ return true;
+}
+
+static bool
+gen8_render_composite_spans(struct sna *sna,
+ uint8_t op,
+ PicturePtr src,
+ PicturePtr dst,
+ int16_t src_x, int16_t src_y,
+ int16_t dst_x, int16_t dst_y,
+ int16_t width, int16_t height,
+ unsigned flags,
+ struct sna_composite_spans_op *tmp)
+{
+ DBG(("%s: %dx%d with flags=%x, current mode=%d\n", __FUNCTION__,
+ width, height, flags, sna->kgem.ring));
+
+ assert(gen8_check_composite_spans(sna, op, src, dst, width, height, flags));
+
+ if (need_tiling(sna, width, height)) {
+ DBG(("%s: tiling, operation (%dx%d) too wide for pipeline\n",
+ __FUNCTION__, width, height));
+ return sna_tiling_composite_spans(op, src, dst,
+ src_x, src_y, dst_x, dst_y,
+ width, height, flags, tmp);
+ }
+
+ tmp->base.op = op;
+ if (!gen8_composite_set_target(sna, &tmp->base, dst,
+ dst_x, dst_y, width, height, true))
+ return false;
+
+ switch (gen8_composite_picture(sna, src, &tmp->base.src,
+ src_x, src_y,
+ width, height,
+ dst_x, dst_y,
+ dst->polyMode == PolyModePrecise)) {
+ case -1:
+ goto cleanup_dst;
+ case 0:
+ if (!gen4_channel_init_solid(sna, &tmp->base.src, 0))
+ goto cleanup_dst;
+ /* fall through to fixup */
+ case 1:
+ gen8_composite_channel_convert(&tmp->base.src);
+ break;
+ }
+ tmp->base.mask.bo = NULL;
+
+ tmp->base.is_affine = tmp->base.src.is_affine;
+ tmp->base.need_magic_ca_pass = false;
+
+ tmp->base.u.gen8.flags =
+ GEN8_SET_FLAGS(SAMPLER_OFFSET(tmp->base.src.filter,
+ tmp->base.src.repeat,
+ SAMPLER_FILTER_NEAREST,
+ SAMPLER_EXTEND_PAD),
+ gen8_get_blend(tmp->base.op, false, tmp->base.dst.format),
+ GEN8_WM_KERNEL_OPACITY | !tmp->base.is_affine,
+ gen4_choose_spans_emitter(sna, tmp));
+
+ tmp->box = gen8_render_composite_spans_box;
+ tmp->boxes = gen8_render_composite_spans_boxes;
+ if (tmp->emit_boxes)
+ tmp->thread_boxes = gen8_render_composite_spans_boxes__thread;
+ tmp->done = gen8_render_composite_spans_done;
+
+ kgem_set_mode(&sna->kgem, KGEM_RENDER, tmp->base.dst.bo);
+ if (!kgem_check_bo(&sna->kgem,
+ tmp->base.dst.bo, tmp->base.src.bo,
+ NULL)) {
+ kgem_submit(&sna->kgem);
+ if (!kgem_check_bo(&sna->kgem,
+ tmp->base.dst.bo, tmp->base.src.bo,
+ NULL))
+ goto cleanup_src;
+ _kgem_set_mode(&sna->kgem, KGEM_RENDER);
+ }
+
+ gen8_align_vertex(sna, &tmp->base);
+ gen8_emit_composite_state(sna, &tmp->base);
+ return true;
+
+cleanup_src:
+ if (tmp->base.src.bo)
+ kgem_bo_destroy(&sna->kgem, tmp->base.src.bo);
+cleanup_dst:
+ if (tmp->base.redirect.real_bo)
+ kgem_bo_destroy(&sna->kgem, tmp->base.dst.bo);
+ return false;
+}
+#endif
+
+static void
+gen8_emit_copy_state(struct sna *sna,
+ const struct sna_composite_op *op)
+{
+ uint32_t *binding_table;
+ uint16_t offset, dirty;
+
+ gen8_get_batch(sna, op);
+
+ binding_table = gen8_composite_get_binding_table(sna, &offset);
+
+ dirty = kgem_bo_is_dirty(op->dst.bo);
+
+ binding_table[0] =
+ gen8_bind_bo(sna,
+ op->dst.bo, op->dst.width, op->dst.height,
+ gen8_get_dest_format(op->dst.format),
+ true);
+ binding_table[1] =
+ gen8_bind_bo(sna,
+ op->src.bo, op->src.width, op->src.height,
+ op->src.card_format,
+ false);
+
+ if (sna->kgem.surface == offset &&
+ *(uint64_t *)(sna->kgem.batch + sna->render_state.gen8.surface_table) == *(uint64_t*)binding_table) {
+ sna->kgem.surface += SURFACE_DW;
+ offset = sna->render_state.gen8.surface_table;
+ }
+
+ if (sna->kgem.batch[sna->render_state.gen8.surface_table] == binding_table[0])
+ dirty = 0;
+
+ assert(!GEN8_READS_DST(op->u.gen8.flags));
+ gen8_emit_state(sna, op, offset | dirty);
+}
+
+static inline bool
+prefer_blt_copy(struct sna *sna,
+ struct kgem_bo *src_bo,
+ struct kgem_bo *dst_bo,
+ unsigned flags)
+{
+ if (sna->kgem.mode == KGEM_BLT)
+ return true;
+
+ assert((flags & COPY_SYNC) == 0);
+
+ if (src_bo == dst_bo && can_switch_to_blt(sna, dst_bo, flags))
+ return true;
+
+ if (untiled_tlb_miss(src_bo) ||
+ untiled_tlb_miss(dst_bo))
+ return true;
+
+ if (force_blt_ring(sna))
+ return true;
+
+ if (kgem_bo_is_render(dst_bo) ||
+ kgem_bo_is_render(src_bo))
+ return false;
+
+ if (prefer_render_ring(sna, dst_bo))
+ return false;
+
+ if (!prefer_blt_ring(sna, dst_bo, flags))
+ return false;
+
+ return prefer_blt_bo(sna, src_bo) || prefer_blt_bo(sna, dst_bo);
+}
+
+inline static void boxes_extents(const BoxRec *box, int n, BoxRec *extents)
+{
+ *extents = box[0];
+ while (--n) {
+ box++;
+
+ if (box->x1 < extents->x1)
+ extents->x1 = box->x1;
+ if (box->x2 > extents->x2)
+ extents->x2 = box->x2;
+
+ if (box->y1 < extents->y1)
+ extents->y1 = box->y1;
+ if (box->y2 > extents->y2)
+ extents->y2 = box->y2;
+ }
+}
+
+static inline bool
+overlaps(struct sna *sna,
+ struct kgem_bo *src_bo, int16_t src_dx, int16_t src_dy,
+ struct kgem_bo *dst_bo, int16_t dst_dx, int16_t dst_dy,
+ const BoxRec *box, int n, BoxRec *extents)
+{
+ if (src_bo != dst_bo)
+ return false;
+
+ boxes_extents(box, n, extents);
+ return (extents->x2 + src_dx > extents->x1 + dst_dx &&
+ extents->x1 + src_dx < extents->x2 + dst_dx &&
+ extents->y2 + src_dy > extents->y1 + dst_dy &&
+ extents->y1 + src_dy < extents->y2 + dst_dy);
+}
+
+static bool
+gen8_render_copy_boxes(struct sna *sna, uint8_t alu,
+ PixmapPtr src, struct kgem_bo *src_bo, int16_t src_dx, int16_t src_dy,
+ PixmapPtr dst, struct kgem_bo *dst_bo, int16_t dst_dx, int16_t dst_dy,
+ const BoxRec *box, int n, unsigned flags)
+{
+ struct sna_composite_op tmp;
+ BoxRec extents;
+
+ DBG(("%s (%d, %d)->(%d, %d) x %d, alu=%x, flags=%x, self-copy=%d, overlaps? %d\n",
+ __FUNCTION__, src_dx, src_dy, dst_dx, dst_dy, n, alu, flags,
+ src_bo == dst_bo,
+ overlaps(sna,
+ src_bo, src_dx, src_dy,
+ dst_bo, dst_dx, dst_dy,
+ box, n, &extents)));
+
+ if (prefer_blt_copy(sna, src_bo, dst_bo, flags) &&
+ sna_blt_compare_depth(&src->drawable, &dst->drawable) &&
+ sna_blt_copy_boxes(sna, alu,
+ src_bo, src_dx, src_dy,
+ dst_bo, dst_dx, dst_dy,
+ dst->drawable.bitsPerPixel,
+ box, n))
+ return true;
+
+ if (!(alu == GXcopy || alu == GXclear)) {
+fallback_blt:
+ DBG(("%s: fallback blt\n", __FUNCTION__));
+ if (!sna_blt_compare_depth(&src->drawable, &dst->drawable))
+ return false;
+
+ return sna_blt_copy_boxes_fallback(sna, alu,
+ src, src_bo, src_dx, src_dy,
+ dst, dst_bo, dst_dx, dst_dy,
+ box, n);
+ }
+
+ if (overlaps(sna,
+ src_bo, src_dx, src_dy,
+ dst_bo, dst_dx, dst_dy,
+ box, n, &extents)) {
+ if (too_large(extents.x2-extents.x1, extents.y2-extents.y1))
+ goto fallback_blt;
+
+ if (can_switch_to_blt(sna, dst_bo, flags) &&
+ sna_blt_compare_depth(&src->drawable, &dst->drawable) &&
+ sna_blt_copy_boxes(sna, alu,
+ src_bo, src_dx, src_dy,
+ dst_bo, dst_dx, dst_dy,
+ dst->drawable.bitsPerPixel,
+ box, n))
+ return true;
+
+ return sna_render_copy_boxes__overlap(sna, alu,
+ src, src_bo, src_dx, src_dy,
+ dst, dst_bo, dst_dx, dst_dy,
+ box, n, &extents);
+ }
+
+ if (dst->drawable.depth == src->drawable.depth) {
+ tmp.dst.format = sna_render_format_for_depth(dst->drawable.depth);
+ tmp.src.pict_format = tmp.dst.format;
+ } else {
+ tmp.dst.format = sna_format_for_depth(dst->drawable.depth);
+ tmp.src.pict_format = sna_format_for_depth(src->drawable.depth);
+ }
+ if (!gen8_check_format(tmp.src.pict_format))
+ goto fallback_blt;
+
+ tmp.dst.pixmap = dst;
+ tmp.dst.width = dst->drawable.width;
+ tmp.dst.height = dst->drawable.height;
+ tmp.dst.bo = dst_bo;
+ tmp.dst.x = tmp.dst.y = 0;
+ tmp.damage = NULL;
+
+ sna_render_composite_redirect_init(&tmp);
+ if (too_large(tmp.dst.width, tmp.dst.height)) {
+ int i;
+
+ extents = box[0];
+ for (i = 1; i < n; i++) {
+ if (box[i].x1 < extents.x1)
+ extents.x1 = box[i].x1;
+ if (box[i].y1 < extents.y1)
+ extents.y1 = box[i].y1;
+
+ if (box[i].x2 > extents.x2)
+ extents.x2 = box[i].x2;
+ if (box[i].y2 > extents.y2)
+ extents.y2 = box[i].y2;
+ }
+
+ if (!sna_render_composite_redirect(sna, &tmp,
+ extents.x1 + dst_dx,
+ extents.y1 + dst_dy,
+ extents.x2 - extents.x1,
+ extents.y2 - extents.y1,
+ n > 1))
+ goto fallback_tiled;
+
+ dst_dx += tmp.dst.x;
+ dst_dy += tmp.dst.y;
+
+ tmp.dst.x = tmp.dst.y = 0;
+ }
+
+ tmp.src.card_format = gen8_get_card_format(tmp.src.pict_format);
+ if (too_large(src->drawable.width, src->drawable.height)) {
+ int i;
+
+ extents = box[0];
+ for (i = 1; i < n; i++) {
+ if (box[i].x1 < extents.x1)
+ extents.x1 = box[i].x1;
+ if (box[i].y1 < extents.y1)
+ extents.y1 = box[i].y1;
+
+ if (box[i].x2 > extents.x2)
+ extents.x2 = box[i].x2;
+ if (box[i].y2 > extents.y2)
+ extents.y2 = box[i].y2;
+ }
+
+ if (!sna_render_pixmap_partial(sna, src, src_bo, &tmp.src,
+ extents.x1 + src_dx,
+ extents.y1 + src_dy,
+ extents.x2 - extents.x1,
+ extents.y2 - extents.y1))
+ goto fallback_tiled_dst;
+
+ src_dx += tmp.src.offset[0];
+ src_dy += tmp.src.offset[1];
+ } else {
+ tmp.src.bo = src_bo;
+ tmp.src.width = src->drawable.width;
+ tmp.src.height = src->drawable.height;
+ }
+
+ tmp.mask.bo = NULL;
+
+ tmp.floats_per_vertex = 2;
+ tmp.floats_per_rect = 6;
+ tmp.need_magic_ca_pass = 0;
+
+ tmp.u.gen8.flags = COPY_FLAGS(alu);
+
+ kgem_set_mode(&sna->kgem, KGEM_RENDER, tmp.dst.bo);
+ if (!kgem_check_bo(&sna->kgem, tmp.dst.bo, tmp.src.bo, NULL)) {
+ kgem_submit(&sna->kgem);
+ if (!kgem_check_bo(&sna->kgem, tmp.dst.bo, tmp.src.bo, NULL)) {
+ if (tmp.src.bo != src_bo)
+ kgem_bo_destroy(&sna->kgem, tmp.src.bo);
+ if (tmp.redirect.real_bo)
+ kgem_bo_destroy(&sna->kgem, tmp.dst.bo);
+ goto fallback_blt;
+ }
+ _kgem_set_mode(&sna->kgem, KGEM_RENDER);
+ }
+
+ gen8_align_vertex(sna, &tmp);
+ gen8_emit_copy_state(sna, &tmp);
+
+ do {
+ int16_t *v;
+ int n_this_time;
+
+ n_this_time = gen8_get_rectangles(sna, &tmp, n,
+ gen8_emit_copy_state);
+ n -= n_this_time;
+
+ v = (int16_t *)(sna->render.vertices + sna->render.vertex_used);
+ sna->render.vertex_used += 6 * n_this_time;
+ assert(sna->render.vertex_used <= sna->render.vertex_size);
+ do {
+
+ DBG((" (%d, %d) -> (%d, %d) + (%d, %d)\n",
+ box->x1 + src_dx, box->y1 + src_dy,
+ box->x1 + dst_dx, box->y1 + dst_dy,
+ box->x2 - box->x1, box->y2 - box->y1));
+ v[0] = box->x2 + dst_dx;
+ v[2] = box->x2 + src_dx;
+ v[1] = v[5] = box->y2 + dst_dy;
+ v[3] = v[7] = box->y2 + src_dy;
+ v[8] = v[4] = box->x1 + dst_dx;
+ v[10] = v[6] = box->x1 + src_dx;
+ v[9] = box->y1 + dst_dy;
+ v[11] = box->y1 + src_dy;
+ v += 12; box++;
+ } while (--n_this_time);
+ } while (n);
+
+ gen8_vertex_flush(sna);
+ sna_render_composite_redirect_done(sna, &tmp);
+ if (tmp.src.bo != src_bo)
+ kgem_bo_destroy(&sna->kgem, tmp.src.bo);
+ return true;
+
+fallback_tiled_dst:
+ if (tmp.redirect.real_bo)
+ kgem_bo_destroy(&sna->kgem, tmp.dst.bo);
+fallback_tiled:
+ DBG(("%s: fallback tiled\n", __FUNCTION__));
+ if (sna_blt_compare_depth(&src->drawable, &dst->drawable) &&
+ sna_blt_copy_boxes(sna, alu,
+ src_bo, src_dx, src_dy,
+ dst_bo, dst_dx, dst_dy,
+ dst->drawable.bitsPerPixel,
+ box, n))
+ return true;
+
+ return sna_tiling_copy_boxes(sna, alu,
+ src, src_bo, src_dx, src_dy,
+ dst, dst_bo, dst_dx, dst_dy,
+ box, n);
+}
+
+static void
+gen8_render_copy_blt(struct sna *sna,
+ const struct sna_copy_op *op,
+ int16_t sx, int16_t sy,
+ int16_t w, int16_t h,
+ int16_t dx, int16_t dy)
+{
+ int16_t *v;
+
+ gen8_get_rectangles(sna, &op->base, 1, gen8_emit_copy_state);
+
+ v = (int16_t *)&sna->render.vertices[sna->render.vertex_used];
+ sna->render.vertex_used += 6;
+ assert(sna->render.vertex_used <= sna->render.vertex_size);
+
+ v[0] = dx+w; v[1] = dy+h;
+ v[2] = sx+w; v[3] = sy+h;
+ v[4] = dx; v[5] = dy+h;
+ v[6] = sx; v[7] = sy+h;
+ v[8] = dx; v[9] = dy;
+ v[10] = sx; v[11] = sy;
+}
+
+static void
+gen8_render_copy_done(struct sna *sna, const struct sna_copy_op *op)
+{
+ if (sna->render.vertex_offset)
+ gen8_vertex_flush(sna);
+}
+
+static bool
+gen8_render_copy(struct sna *sna, uint8_t alu,
+ PixmapPtr src, struct kgem_bo *src_bo,
+ PixmapPtr dst, struct kgem_bo *dst_bo,
+ struct sna_copy_op *op)
+{
+ DBG(("%s (alu=%d, src=(%dx%d), dst=(%dx%d))\n",
+ __FUNCTION__, alu,
+ src->drawable.width, src->drawable.height,
+ dst->drawable.width, dst->drawable.height));
+
+ if (prefer_blt_copy(sna, src_bo, dst_bo, 0) &&
+ sna_blt_compare_depth(&src->drawable, &dst->drawable) &&
+ sna_blt_copy(sna, alu,
+ src_bo, dst_bo,
+ dst->drawable.bitsPerPixel,
+ op))
+ return true;
+
+ if (!(alu == GXcopy || alu == GXclear) || src_bo == dst_bo ||
+ too_large(src->drawable.width, src->drawable.height) ||
+ too_large(dst->drawable.width, dst->drawable.height)) {
+fallback:
+ if (!sna_blt_compare_depth(&src->drawable, &dst->drawable))
+ return false;
+
+ return sna_blt_copy(sna, alu, src_bo, dst_bo,
+ dst->drawable.bitsPerPixel,
+ op);
+ }
+
+ if (dst->drawable.depth == src->drawable.depth) {
+ op->base.dst.format = sna_render_format_for_depth(dst->drawable.depth);
+ op->base.src.pict_format = op->base.dst.format;
+ } else {
+ op->base.dst.format = sna_format_for_depth(dst->drawable.depth);
+ op->base.src.pict_format = sna_format_for_depth(src->drawable.depth);
+ }
+ if (!gen8_check_format(op->base.src.pict_format))
+ goto fallback;
+
+ op->base.dst.pixmap = dst;
+ op->base.dst.width = dst->drawable.width;
+ op->base.dst.height = dst->drawable.height;
+ op->base.dst.bo = dst_bo;
+
+ op->base.src.bo = src_bo;
+ op->base.src.card_format =
+ gen8_get_card_format(op->base.src.pict_format);
+ op->base.src.width = src->drawable.width;
+ op->base.src.height = src->drawable.height;
+
+ op->base.mask.bo = NULL;
+
+ op->base.floats_per_vertex = 2;
+ op->base.floats_per_rect = 6;
+
+ op->base.u.gen8.flags = COPY_FLAGS(alu);
+
+ kgem_set_mode(&sna->kgem, KGEM_RENDER, dst_bo);
+ if (!kgem_check_bo(&sna->kgem, dst_bo, src_bo, NULL)) {
+ kgem_submit(&sna->kgem);
+ if (!kgem_check_bo(&sna->kgem, dst_bo, src_bo, NULL))
+ goto fallback;
+ _kgem_set_mode(&sna->kgem, KGEM_RENDER);
+ }
+
+ gen8_align_vertex(sna, &op->base);
+ gen8_emit_copy_state(sna, &op->base);
+
+ op->blt = gen8_render_copy_blt;
+ op->done = gen8_render_copy_done;
+ return true;
+}
+
+static void
+gen8_emit_fill_state(struct sna *sna, const struct sna_composite_op *op)
+{
+ uint32_t *binding_table;
+ uint16_t offset, dirty;
+
+ /* XXX Render Target Fast Clear
+ * Set RTFC Enable in PS and render a rectangle.
+ * Limited to a clearing the full MSC surface only with a
+ * specific kernel.
+ */
+
+ gen8_get_batch(sna, op);
+
+ binding_table = gen8_composite_get_binding_table(sna, &offset);
+
+ dirty = kgem_bo_is_dirty(op->dst.bo);
+
+ binding_table[0] =
+ gen8_bind_bo(sna,
+ op->dst.bo, op->dst.width, op->dst.height,
+ gen8_get_dest_format(op->dst.format),
+ true);
+ binding_table[1] =
+ gen8_bind_bo(sna,
+ op->src.bo, 1, 1,
+ SURFACEFORMAT_B8G8R8A8_UNORM,
+ false);
+
+ if (sna->kgem.surface == offset &&
+ *(uint64_t *)(sna->kgem.batch + sna->render_state.gen8.surface_table) == *(uint64_t*)binding_table) {
+ sna->kgem.surface += SURFACE_DW;
+ offset = sna->render_state.gen8.surface_table;
+ }
+
+ if (sna->kgem.batch[sna->render_state.gen8.surface_table] == binding_table[0])
+ dirty = 0;
+
+ gen8_emit_state(sna, op, offset | dirty);
+}
+
+static bool
+gen8_render_fill_boxes(struct sna *sna,
+ CARD8 op,
+ PictFormat format,
+ const xRenderColor *color,
+ PixmapPtr dst, struct kgem_bo *dst_bo,
+ const BoxRec *box, int n)
+{
+ struct sna_composite_op tmp;
+ uint32_t pixel;
+
+ DBG(("%s (op=%d, color=(%04x, %04x, %04x, %04x) [%08x])\n",
+ __FUNCTION__, op,
+ color->red, color->green, color->blue, color->alpha, (int)format));
+
+ if (op >= ARRAY_SIZE(gen8_blend_op)) {
+ DBG(("%s: fallback due to unhandled blend op: %d\n",
+ __FUNCTION__, op));
+ return false;
+ }
+
+ if (prefer_blt_fill(sna, dst_bo, FILL_BOXES) ||
+ !gen8_check_dst_format(format)) {
+ uint8_t alu = GXinvalid;
+
+ if (op <= PictOpSrc) {
+ pixel = 0;
+ if (op == PictOpClear)
+ alu = GXclear;
+ else if (sna_get_pixel_from_rgba(&pixel,
+ color->red,
+ color->green,
+ color->blue,
+ color->alpha,
+ format))
+ alu = GXcopy;
+ }
+
+ if (alu != GXinvalid &&
+ sna_blt_fill_boxes(sna, alu,
+ dst_bo, dst->drawable.bitsPerPixel,
+ pixel, box, n))
+ return true;
+
+ if (!gen8_check_dst_format(format))
+ return false;
+ }
+
+ if (op == PictOpClear) {
+ pixel = 0;
+ op = PictOpSrc;
+ } else if (!sna_get_pixel_from_rgba(&pixel,
+ color->red,
+ color->green,
+ color->blue,
+ color->alpha,
+ PICT_a8r8g8b8))
+ return false;
+
+ DBG(("%s(%08x x %d [(%d, %d), (%d, %d) ...])\n",
+ __FUNCTION__, pixel, n,
+ box[0].x1, box[0].y1, box[0].x2, box[0].y2));
+
+ tmp.dst.pixmap = dst;
+ tmp.dst.width = dst->drawable.width;
+ tmp.dst.height = dst->drawable.height;
+ tmp.dst.format = format;
+ tmp.dst.bo = dst_bo;
+ tmp.dst.x = tmp.dst.y = 0;
+ tmp.damage = NULL;
+
+ sna_render_composite_redirect_init(&tmp);
+ if (too_large(dst->drawable.width, dst->drawable.height)) {
+ BoxRec extents;
+
+ boxes_extents(box, n, &extents);
+ if (!sna_render_composite_redirect(sna, &tmp,
+ extents.x1, extents.y1,
+ extents.x2 - extents.x1,
+ extents.y2 - extents.y1,
+ n > 1))
+ return sna_tiling_fill_boxes(sna, op, format, color,
+ dst, dst_bo, box, n);
+ }
+
+ tmp.src.bo = sna_render_get_solid(sna, pixel);
+ tmp.mask.bo = NULL;
+
+ tmp.floats_per_vertex = 2;
+ tmp.floats_per_rect = 6;
+ tmp.need_magic_ca_pass = false;
+
+ tmp.u.gen8.flags = FILL_FLAGS(op, format);
+
+ kgem_set_mode(&sna->kgem, KGEM_RENDER, dst_bo);
+ if (!kgem_check_bo(&sna->kgem, dst_bo, NULL)) {
+ kgem_submit(&sna->kgem);
+ if (!kgem_check_bo(&sna->kgem, dst_bo, NULL)) {
+ kgem_bo_destroy(&sna->kgem, tmp.src.bo);
+ tmp.src.bo = NULL;
+
+ if (tmp.redirect.real_bo) {
+ kgem_bo_destroy(&sna->kgem, tmp.dst.bo);
+ tmp.redirect.real_bo = NULL;
+ }
+
+ return false;
+ }
+ _kgem_set_mode(&sna->kgem, KGEM_RENDER);
+ }
+
+ gen8_align_vertex(sna, &tmp);
+ gen8_emit_fill_state(sna, &tmp);
+
+ do {
+ int n_this_time;
+ int16_t *v;
+
+ n_this_time = gen8_get_rectangles(sna, &tmp, n,
+ gen8_emit_fill_state);
+ n -= n_this_time;
+
+ v = (int16_t *)(sna->render.vertices + sna->render.vertex_used);
+ sna->render.vertex_used += 6 * n_this_time;
+ assert(sna->render.vertex_used <= sna->render.vertex_size);
+ do {
+ DBG((" (%d, %d), (%d, %d)\n",
+ box->x1, box->y1, box->x2, box->y2));
+
+ v[0] = box->x2;
+ v[5] = v[1] = box->y2;
+ v[8] = v[4] = box->x1;
+ v[9] = box->y1;
+ v[2] = v[3] = v[7] = 1;
+ v[6] = v[10] = v[11] = 0;
+ v += 12; box++;
+ } while (--n_this_time);
+ } while (n);
+
+ gen8_vertex_flush(sna);
+ kgem_bo_destroy(&sna->kgem, tmp.src.bo);
+ sna_render_composite_redirect_done(sna, &tmp);
+ return true;
+}
+
+static void
+gen8_render_fill_op_blt(struct sna *sna,
+ const struct sna_fill_op *op,
+ int16_t x, int16_t y, int16_t w, int16_t h)
+{
+ int16_t *v;
+
+ DBG(("%s: (%d, %d)x(%d, %d)\n", __FUNCTION__, x, y, w, h));
+
+ gen8_get_rectangles(sna, &op->base, 1, gen8_emit_fill_state);
+
+ v = (int16_t *)&sna->render.vertices[sna->render.vertex_used];
+ sna->render.vertex_used += 6;
+ assert(sna->render.vertex_used <= sna->render.vertex_size);
+
+ v[0] = x+w;
+ v[4] = v[8] = x;
+ v[1] = v[5] = y+h;
+ v[9] = y;
+
+ v[2] = v[3] = v[7] = 1;
+ v[6] = v[10] = v[11] = 0;
+}
+
+fastcall static void
+gen8_render_fill_op_box(struct sna *sna,
+ const struct sna_fill_op *op,
+ const BoxRec *box)
+{
+ int16_t *v;
+
+ DBG(("%s: (%d, %d),(%d, %d)\n", __FUNCTION__,
+ box->x1, box->y1, box->x2, box->y2));
+
+ gen8_get_rectangles(sna, &op->base, 1, gen8_emit_fill_state);
+
+ v = (int16_t *)&sna->render.vertices[sna->render.vertex_used];
+ sna->render.vertex_used += 6;
+ assert(sna->render.vertex_used <= sna->render.vertex_size);
+
+ v[0] = box->x2;
+ v[8] = v[4] = box->x1;
+ v[5] = v[1] = box->y2;
+ v[9] = box->y1;
+
+ v[7] = v[2] = v[3] = 1;
+ v[6] = v[10] = v[11] = 0;
+}
+
+fastcall static void
+gen8_render_fill_op_boxes(struct sna *sna,
+ const struct sna_fill_op *op,
+ const BoxRec *box,
+ int nbox)
+{
+ DBG(("%s: (%d, %d),(%d, %d)... x %d\n", __FUNCTION__,
+ box->x1, box->y1, box->x2, box->y2, nbox));
+
+ do {
+ int nbox_this_time;
+ int16_t *v;
+
+ nbox_this_time = gen8_get_rectangles(sna, &op->base, nbox,
+ gen8_emit_fill_state);
+ nbox -= nbox_this_time;
+
+ v = (int16_t *)&sna->render.vertices[sna->render.vertex_used];
+ sna->render.vertex_used += 6 * nbox_this_time;
+ assert(sna->render.vertex_used <= sna->render.vertex_size);
+
+ do {
+ v[0] = box->x2;
+ v[8] = v[4] = box->x1;
+ v[5] = v[1] = box->y2;
+ v[9] = box->y1;
+ v[7] = v[2] = v[3] = 1;
+ v[6] = v[10] = v[11] = 0;
+ box++; v += 12;
+ } while (--nbox_this_time);
+ } while (nbox);
+}
+
+static void
+gen8_render_fill_op_done(struct sna *sna, const struct sna_fill_op *op)
+{
+ if (sna->render.vertex_offset)
+ gen8_vertex_flush(sna);
+ kgem_bo_destroy(&sna->kgem, op->base.src.bo);
+}
+
+static bool
+gen8_render_fill(struct sna *sna, uint8_t alu,
+ PixmapPtr dst, struct kgem_bo *dst_bo,
+ uint32_t color, unsigned flags,
+ struct sna_fill_op *op)
+{
+ DBG(("%s: (alu=%d, color=%x)\n", __FUNCTION__, alu, color));
+
+ if (prefer_blt_fill(sna, dst_bo, flags) &&
+ sna_blt_fill(sna, alu,
+ dst_bo, dst->drawable.bitsPerPixel,
+ color,
+ op))
+ return true;
+
+ if (!(alu == GXcopy || alu == GXclear) ||
+ too_large(dst->drawable.width, dst->drawable.height))
+ return sna_blt_fill(sna, alu,
+ dst_bo, dst->drawable.bitsPerPixel,
+ color,
+ op);
+
+ if (alu == GXclear)
+ color = 0;
+
+ op->base.dst.pixmap = dst;
+ op->base.dst.width = dst->drawable.width;
+ op->base.dst.height = dst->drawable.height;
+ op->base.dst.format = sna_format_for_depth(dst->drawable.depth);
+ op->base.dst.bo = dst_bo;
+ op->base.dst.x = op->base.dst.y = 0;
+
+ op->base.src.bo =
+ sna_render_get_solid(sna,
+ sna_rgba_for_color(color,
+ dst->drawable.depth));
+ op->base.mask.bo = NULL;
+
+ op->base.need_magic_ca_pass = false;
+ op->base.floats_per_vertex = 2;
+ op->base.floats_per_rect = 6;
+
+ op->base.u.gen8.flags = FILL_FLAGS_NOBLEND;
+
+ kgem_set_mode(&sna->kgem, KGEM_RENDER, dst_bo);
+ if (!kgem_check_bo(&sna->kgem, dst_bo, NULL)) {
+ kgem_submit(&sna->kgem);
+ if (!kgem_check_bo(&sna->kgem, dst_bo, NULL)) {
+ kgem_bo_destroy(&sna->kgem, op->base.src.bo);
+ return false;
+ }
+
+ _kgem_set_mode(&sna->kgem, KGEM_RENDER);
+ }
+
+ gen8_align_vertex(sna, &op->base);
+ gen8_emit_fill_state(sna, &op->base);
+
+ op->blt = gen8_render_fill_op_blt;
+ op->box = gen8_render_fill_op_box;
+ op->boxes = gen8_render_fill_op_boxes;
+ op->done = gen8_render_fill_op_done;
+ return true;
+}
+
+static bool
+gen8_render_fill_one_try_blt(struct sna *sna, PixmapPtr dst, struct kgem_bo *bo,
+ uint32_t color,
+ int16_t x1, int16_t y1, int16_t x2, int16_t y2,
+ uint8_t alu)
+{
+ BoxRec box;
+
+ box.x1 = x1;
+ box.y1 = y1;
+ box.x2 = x2;
+ box.y2 = y2;
+
+ return sna_blt_fill_boxes(sna, alu,
+ bo, dst->drawable.bitsPerPixel,
+ color, &box, 1);
+}
+
+static bool
+gen8_render_fill_one(struct sna *sna, PixmapPtr dst, struct kgem_bo *bo,
+ uint32_t color,
+ int16_t x1, int16_t y1,
+ int16_t x2, int16_t y2,
+ uint8_t alu)
+{
+ struct sna_composite_op tmp;
+ int16_t *v;
+
+ /* Prefer to use the BLT if already engaged */
+ if (prefer_blt_fill(sna, bo, FILL_BOXES) &&
+ gen8_render_fill_one_try_blt(sna, dst, bo, color,
+ x1, y1, x2, y2, alu))
+ return true;
+
+ /* Must use the BLT if we can't RENDER... */
+ if (!(alu == GXcopy || alu == GXclear) ||
+ too_large(dst->drawable.width, dst->drawable.height))
+ return gen8_render_fill_one_try_blt(sna, dst, bo, color,
+ x1, y1, x2, y2, alu);
+
+ if (alu == GXclear)
+ color = 0;
+
+ tmp.dst.pixmap = dst;
+ tmp.dst.width = dst->drawable.width;
+ tmp.dst.height = dst->drawable.height;
+ tmp.dst.format = sna_format_for_depth(dst->drawable.depth);
+ tmp.dst.bo = bo;
+ tmp.dst.x = tmp.dst.y = 0;
+
+ tmp.src.bo =
+ sna_render_get_solid(sna,
+ sna_rgba_for_color(color,
+ dst->drawable.depth));
+ tmp.mask.bo = NULL;
+
+ tmp.floats_per_vertex = 2;
+ tmp.floats_per_rect = 6;
+ tmp.need_magic_ca_pass = false;
+
+ tmp.u.gen8.flags = FILL_FLAGS_NOBLEND;
+
+ kgem_set_mode(&sna->kgem, KGEM_RENDER, bo);
+ if (!kgem_check_bo(&sna->kgem, bo, NULL)) {
+ kgem_submit(&sna->kgem);
+ if (kgem_check_bo(&sna->kgem, bo, NULL)) {
+ kgem_bo_destroy(&sna->kgem, tmp.src.bo);
+ return false;
+ }
+ _kgem_set_mode(&sna->kgem, KGEM_RENDER);
+ }
+
+ gen8_align_vertex(sna, &tmp);
+ gen8_emit_fill_state(sna, &tmp);
+
+ gen8_get_rectangles(sna, &tmp, 1, gen8_emit_fill_state);
+
+ DBG((" (%d, %d), (%d, %d)\n", x1, y1, x2, y2));
+
+ v = (int16_t *)&sna->render.vertices[sna->render.vertex_used];
+ sna->render.vertex_used += 6;
+ assert(sna->render.vertex_used <= sna->render.vertex_size);
+
+ v[0] = x2;
+ v[8] = v[4] = x1;
+ v[5] = v[1] = y2;
+ v[9] = y1;
+ v[7] = v[2] = v[3] = 1;
+ v[6] = v[10] = v[11] = 0;
+
+ gen8_vertex_flush(sna);
+ kgem_bo_destroy(&sna->kgem, tmp.src.bo);
+
+ return true;
+}
+
+static bool
+gen8_render_clear_try_blt(struct sna *sna, PixmapPtr dst, struct kgem_bo *bo)
+{
+ BoxRec box;
+
+ box.x1 = 0;
+ box.y1 = 0;
+ box.x2 = dst->drawable.width;
+ box.y2 = dst->drawable.height;
+
+ return sna_blt_fill_boxes(sna, GXclear,
+ bo, dst->drawable.bitsPerPixel,
+ 0, &box, 1);
+}
+
+static bool
+gen8_render_clear(struct sna *sna, PixmapPtr dst, struct kgem_bo *bo)
+{
+ struct sna_composite_op tmp;
+ int16_t *v;
+
+ DBG(("%s: %dx%d\n",
+ __FUNCTION__,
+ dst->drawable.width,
+ dst->drawable.height));
+
+ /* Prefer to use the BLT if already engaged */
+ if (sna->kgem.mode == KGEM_BLT &&
+ gen8_render_clear_try_blt(sna, dst, bo))
+ return true;
+
+ /* Must use the BLT if we can't RENDER... */
+ if (too_large(dst->drawable.width, dst->drawable.height))
+ return gen8_render_clear_try_blt(sna, dst, bo);
+
+ tmp.dst.pixmap = dst;
+ tmp.dst.width = dst->drawable.width;
+ tmp.dst.height = dst->drawable.height;
+ tmp.dst.format = sna_format_for_depth(dst->drawable.depth);
+ tmp.dst.bo = bo;
+ tmp.dst.x = tmp.dst.y = 0;
+
+ tmp.src.bo = sna_render_get_solid(sna, 0);
+ tmp.mask.bo = NULL;
+
+ tmp.floats_per_vertex = 2;
+ tmp.floats_per_rect = 6;
+ tmp.need_magic_ca_pass = false;
+
+ tmp.u.gen8.flags = FILL_FLAGS_NOBLEND;
+
+ kgem_set_mode(&sna->kgem, KGEM_RENDER, bo);
+ if (!kgem_check_bo(&sna->kgem, bo, NULL)) {
+ kgem_submit(&sna->kgem);
+ if (!kgem_check_bo(&sna->kgem, bo, NULL)) {
+ kgem_bo_destroy(&sna->kgem, tmp.src.bo);
+ return false;
+ }
+ _kgem_set_mode(&sna->kgem, KGEM_RENDER);
+ }
+
+ gen8_align_vertex(sna, &tmp);
+ gen8_emit_fill_state(sna, &tmp);
+
+ gen8_get_rectangles(sna, &tmp, 1, gen8_emit_fill_state);
+
+ v = (int16_t *)&sna->render.vertices[sna->render.vertex_used];
+ sna->render.vertex_used += 6;
+ assert(sna->render.vertex_used <= sna->render.vertex_size);
+
+ v[0] = dst->drawable.width;
+ v[5] = v[1] = dst->drawable.height;
+ v[8] = v[4] = 0;
+ v[9] = 0;
+
+ v[7] = v[2] = v[3] = 1;
+ v[6] = v[10] = v[11] = 0;
+
+ gen8_vertex_flush(sna);
+ kgem_bo_destroy(&sna->kgem, tmp.src.bo);
+
+ return true;
+}
+
+#if !NO_VIDEO
+static uint32_t gen8_bind_video_source(struct sna *sna,
+ struct kgem_bo *bo,
+ uint32_t delta,
+ int width,
+ int height,
+ int pitch,
+ uint32_t format)
+{
+ uint32_t *ss;
+ int offset;
+
+ offset = sna->kgem.surface -= SURFACE_DW;
+ ss = sna->kgem.batch + offset;
+ ss[0] = (SURFACE_2D << SURFACE_TYPE_SHIFT |
+ gen8_tiling_bits(bo->tiling) |
+ format << SURFACE_FORMAT_SHIFT |
+ SURFACE_VALIGN_4 | SURFACE_HALIGN_4);
+ ss[1] = 0;
+ ss[2] = ((width - 1) << SURFACE_WIDTH_SHIFT |
+ (height - 1) << SURFACE_HEIGHT_SHIFT);
+ ss[3] = (pitch - 1) << SURFACE_PITCH_SHIFT;
+ ss[4] = 0;
+ ss[5] = 0;
+ ss[6] = 0;
+ ss[7] = SURFACE_SWIZZLE(RED, GREEN, BLUE, ALPHA);
+ *(uint64_t *)(ss+8) =
+ kgem_add_reloc64(&sna->kgem, offset + 8, bo,
+ I915_GEM_DOMAIN_SAMPLER << 16,
+ delta);
+ ss[10] = 0;
+ ss[11] = 0;
+ ss[12] = 0;
+ ss[13] = 0;
+ ss[14] = 0;
+ ss[15] = 0;
+
+ DBG(("[%x] bind bo(handle=%d, addr=%d), format=%d, width=%d, height=%d, pitch=%d, tiling=%d -> sampler\n",
+ offset, bo->handle, ss[1],
+ format, width, height, bo->pitch, bo->tiling));
+
+ return offset * sizeof(uint32_t);
+}
+
+static void gen8_emit_video_state(struct sna *sna,
+ const struct sna_composite_op *op)
+{
+ struct sna_video_frame *frame = op->priv;
+ uint32_t src_surf_format;
+ uint32_t src_surf_base[6];
+ int src_width[6];
+ int src_height[6];
+ int src_pitch[6];
+ uint32_t *binding_table;
+ uint16_t offset;
+ int n_src, n;
+
+ /* XXX VeBox, bicubic */
+
+ gen8_get_batch(sna, op);
+
+ src_surf_base[0] = 0;
+ src_surf_base[1] = 0;
+ src_surf_base[2] = frame->VBufOffset;
+ src_surf_base[3] = frame->VBufOffset;
+ src_surf_base[4] = frame->UBufOffset;
+ src_surf_base[5] = frame->UBufOffset;
+
+ if (is_planar_fourcc(frame->id)) {
+ src_surf_format = SURFACEFORMAT_R8_UNORM;
+ src_width[1] = src_width[0] = frame->width;
+ src_height[1] = src_height[0] = frame->height;
+ src_pitch[1] = src_pitch[0] = frame->pitch[1];
+ src_width[4] = src_width[5] = src_width[2] = src_width[3] =
+ frame->width / 2;
+ src_height[4] = src_height[5] = src_height[2] = src_height[3] =
+ frame->height / 2;
+ src_pitch[4] = src_pitch[5] = src_pitch[2] = src_pitch[3] =
+ frame->pitch[0];
+ n_src = 6;
+ } else {
+ if (frame->id == FOURCC_UYVY)
+ src_surf_format = SURFACEFORMAT_YCRCB_SWAPY;
+ else
+ src_surf_format = SURFACEFORMAT_YCRCB_NORMAL;
+
+ src_width[0] = frame->width;
+ src_height[0] = frame->height;
+ src_pitch[0] = frame->pitch[0];
+ n_src = 1;
+ }
+
+ binding_table = gen8_composite_get_binding_table(sna, &offset);
+
+ binding_table[0] =
+ gen8_bind_bo(sna,
+ op->dst.bo, op->dst.width, op->dst.height,
+ gen8_get_dest_format(op->dst.format),
+ true);
+ for (n = 0; n < n_src; n++) {
+ binding_table[1+n] =
+ gen8_bind_video_source(sna,
+ frame->bo,
+ src_surf_base[n],
+ src_width[n],
+ src_height[n],
+ src_pitch[n],
+ src_surf_format);
+ }
+
+ gen8_emit_state(sna, op, offset);
+}
+
+static bool
+gen8_render_video(struct sna *sna,
+ struct sna_video *video,
+ struct sna_video_frame *frame,
+ RegionPtr dstRegion,
+ PixmapPtr pixmap)
+{
+ struct sna_composite_op tmp;
+ int dst_width = dstRegion->extents.x2 - dstRegion->extents.x1;
+ int dst_height = dstRegion->extents.y2 - dstRegion->extents.y1;
+ int src_width = frame->src.x2 - frame->src.x1;
+ int src_height = frame->src.y2 - frame->src.y1;
+ float src_offset_x, src_offset_y;
+ float src_scale_x, src_scale_y;
+ int nbox, pix_xoff, pix_yoff;
+ struct sna_pixmap *priv;
+ unsigned filter;
+ BoxPtr box;
+
+ DBG(("%s: src=(%d, %d), dst=(%d, %d), %ldx[(%d, %d), (%d, %d)...]\n",
+ __FUNCTION__,
+ src_width, src_height, dst_width, dst_height,
+ (long)REGION_NUM_RECTS(dstRegion),
+ REGION_EXTENTS(NULL, dstRegion)->x1,
+ REGION_EXTENTS(NULL, dstRegion)->y1,
+ REGION_EXTENTS(NULL, dstRegion)->x2,
+ REGION_EXTENTS(NULL, dstRegion)->y2));
+
+ priv = sna_pixmap_force_to_gpu(pixmap, MOVE_READ | MOVE_WRITE);
+ if (priv == NULL)
+ return false;
+
+ memset(&tmp, 0, sizeof(tmp));
+
+ tmp.dst.pixmap = pixmap;
+ tmp.dst.width = pixmap->drawable.width;
+ tmp.dst.height = pixmap->drawable.height;
+ tmp.dst.format = sna_render_format_for_depth(pixmap->drawable.depth);
+ tmp.dst.bo = priv->gpu_bo;
+
+ tmp.src.bo = frame->bo;
+ tmp.mask.bo = NULL;
+
+ tmp.floats_per_vertex = 3;
+ tmp.floats_per_rect = 9;
+
+ if (src_width == dst_width && src_height == dst_height)
+ filter = SAMPLER_FILTER_NEAREST;
+ else
+ filter = SAMPLER_FILTER_BILINEAR;
+
+ tmp.u.gen8.flags =
+ GEN8_SET_FLAGS(SAMPLER_OFFSET(filter, SAMPLER_EXTEND_PAD,
+ SAMPLER_FILTER_NEAREST, SAMPLER_EXTEND_NONE),
+ NO_BLEND,
+ is_planar_fourcc(frame->id) ?
+ GEN8_WM_KERNEL_VIDEO_PLANAR :
+ GEN8_WM_KERNEL_VIDEO_PACKED,
+ 2);
+ tmp.priv = frame;
+
+ kgem_set_mode(&sna->kgem, KGEM_RENDER, tmp.dst.bo);
+ if (!kgem_check_bo(&sna->kgem, tmp.dst.bo, frame->bo, NULL)) {
+ kgem_submit(&sna->kgem);
+ assert(kgem_check_bo(&sna->kgem, tmp.dst.bo, frame->bo, NULL));
+ _kgem_set_mode(&sna->kgem, KGEM_RENDER);
+ }
+
+ gen8_align_vertex(sna, &tmp);
+ gen8_emit_video_state(sna, &tmp);
+
+ /* Set up the offset for translating from the given region (in screen
+ * coordinates) to the backing pixmap.
+ */
+#ifdef COMPOSITE
+ pix_xoff = -pixmap->screen_x + pixmap->drawable.x;
+ pix_yoff = -pixmap->screen_y + pixmap->drawable.y;
+#else
+ pix_xoff = 0;
+ pix_yoff = 0;
+#endif
+
+ DBG(("%s: src=(%d, %d)x(%d, %d); frame=(%dx%d), dst=(%dx%d)\n",
+ __FUNCTION__,
+ frame->src.x1, frame->src.y1,
+ src_width, src_height,
+ dst_width, dst_height,
+ frame->width, frame->height));
+
+ src_scale_x = (float)src_width / dst_width / frame->width;
+ src_offset_x = (float)frame->src.x1 / frame->width - dstRegion->extents.x1 * src_scale_x;
+
+ src_scale_y = (float)src_height / dst_height / frame->height;
+ src_offset_y = (float)frame->src.y1 / frame->height - dstRegion->extents.y1 * src_scale_y;
+
+ DBG(("%s: scale=(%f, %f), offset=(%f, %f)\n",
+ __FUNCTION__,
+ src_scale_x, src_scale_y,
+ src_offset_x, src_offset_y));
+
+ box = REGION_RECTS(dstRegion);
+ nbox = REGION_NUM_RECTS(dstRegion);
+ while (nbox--) {
+ BoxRec r;
+
+ DBG(("%s: dst=(%d, %d), (%d, %d) + (%d, %d); src=(%f, %f), (%f, %f)\n",
+ __FUNCTION__,
+ box->x1, box->y1,
+ box->x2, box->y2,
+ pix_xoff, pix_yoff,
+ box->x1 * src_scale_x + src_offset_x,
+ box->y1 * src_scale_y + src_offset_y,
+ box->x2 * src_scale_x + src_offset_x,
+ box->y2 * src_scale_y + src_offset_y));
+
+ r.x1 = box->x1 + pix_xoff;
+ r.x2 = box->x2 + pix_xoff;
+ r.y1 = box->y1 + pix_yoff;
+ r.y2 = box->y2 + pix_yoff;
+
+ gen8_get_rectangles(sna, &tmp, 1, gen8_emit_video_state);
+
+ OUT_VERTEX(r.x2, r.y2);
+ OUT_VERTEX_F(box->x2 * src_scale_x + src_offset_x);
+ OUT_VERTEX_F(box->y2 * src_scale_y + src_offset_y);
+
+ OUT_VERTEX(r.x1, r.y2);
+ OUT_VERTEX_F(box->x1 * src_scale_x + src_offset_x);
+ OUT_VERTEX_F(box->y2 * src_scale_y + src_offset_y);
+
+ OUT_VERTEX(r.x1, r.y1);
+ OUT_VERTEX_F(box->x1 * src_scale_x + src_offset_x);
+ OUT_VERTEX_F(box->y1 * src_scale_y + src_offset_y);
+
+ if (!DAMAGE_IS_ALL(priv->gpu_damage)) {
+ sna_damage_add_box(&priv->gpu_damage, &r);
+ sna_damage_subtract_box(&priv->cpu_damage, &r);
+ }
+ box++;
+ }
+
+ gen8_vertex_flush(sna);
+ return true;
+}
+#endif
+
+static void gen8_render_flush(struct sna *sna)
+{
+ gen8_vertex_close(sna);
+
+ assert(sna->render.vb_id == 0);
+ assert(sna->render.vertex_offset == 0);
+}
+
+static void gen8_render_reset(struct sna *sna)
+{
+ sna->render_state.gen8.emit_flush = false;
+ sna->render_state.gen8.needs_invariant = true;
+ sna->render_state.gen8.ve_id = 3 << 2;
+ sna->render_state.gen8.last_primitive = -1;
+
+ sna->render_state.gen8.num_sf_outputs = 0;
+ sna->render_state.gen8.samplers = -1;
+ sna->render_state.gen8.blend = -1;
+ sna->render_state.gen8.kernel = -1;
+ sna->render_state.gen8.drawrect_offset = -1;
+ sna->render_state.gen8.drawrect_limit = -1;
+ sna->render_state.gen8.surface_table = 0;
+
+ if (sna->render.vbo && !kgem_bo_can_map(&sna->kgem, sna->render.vbo)) {
+ DBG(("%s: discarding unmappable vbo\n", __FUNCTION__));
+ discard_vbo(sna);
+ }
+
+ sna->render.vertex_offset = 0;
+ sna->render.nvertex_reloc = 0;
+ sna->render.vb_id = 0;
+}
+
+static void gen8_render_fini(struct sna *sna)
+{
+ kgem_bo_destroy(&sna->kgem, sna->render_state.gen8.general_bo);
+}
+
+static bool gen8_render_setup(struct sna *sna)
+{
+ struct gen8_render_state *state = &sna->render_state.gen8;
+ struct sna_static_stream general;
+ struct gen8_sampler_state *ss;
+ int i, j, k, l, m;
+
+ sna_static_stream_init(&general);
+
+ /* Zero pad the start. If you see an offset of 0x0 in the batchbuffer
+ * dumps, you know it points to zero.
+ */
+ null_create(&general);
+
+ for (m = 0; m < ARRAY_SIZE(wm_kernels); m++) {
+ if (wm_kernels[m].size) {
+ state->wm_kernel[m][1] =
+ sna_static_stream_add(&general,
+ wm_kernels[m].data,
+ wm_kernels[m].size,
+ 64);
+ } else {
+ if (USE_8_PIXEL_DISPATCH) {
+ state->wm_kernel[m][0] =
+ sna_static_stream_compile_wm(sna, &general,
+ wm_kernels[m].data, 8);
+ }
+
+ if (USE_16_PIXEL_DISPATCH) {
+ state->wm_kernel[m][1] =
+ sna_static_stream_compile_wm(sna, &general,
+ wm_kernels[m].data, 16);
+ }
+
+ if (USE_32_PIXEL_DISPATCH) {
+ state->wm_kernel[m][2] =
+ sna_static_stream_compile_wm(sna, &general,
+ wm_kernels[m].data, 32);
+ }
+ }
+ assert(state->wm_kernel[m][0]|state->wm_kernel[m][1]|state->wm_kernel[m][2]);
+ }
+
+ COMPILE_TIME_ASSERT(SAMPLER_OFFSET(FILTER_COUNT, EXTEND_COUNT, FILTER_COUNT, EXTEND_COUNT) <= 0x7ff);
+ ss = sna_static_stream_map(&general,
+ 2 * sizeof(*ss) *
+ (2 +
+ FILTER_COUNT * EXTEND_COUNT *
+ FILTER_COUNT * EXTEND_COUNT),
+ 32);
+ state->wm_state = sna_static_stream_offsetof(&general, ss);
+ sampler_copy_init(ss); ss += 2;
+ sampler_fill_init(ss); ss += 2;
+ for (i = 0; i < FILTER_COUNT; i++) {
+ for (j = 0; j < EXTEND_COUNT; j++) {
+ for (k = 0; k < FILTER_COUNT; k++) {
+ for (l = 0; l < EXTEND_COUNT; l++) {
+ sampler_state_init(ss++, i, j);
+ sampler_state_init(ss++, k, l);
+ }
+ }
+ }
+ }
+
+ state->cc_blend = gen8_create_blend_state(&general);
+
+ state->general_bo = sna_static_stream_fini(sna, &general);
+ return state->general_bo != NULL;
+}
+
+const char *gen8_render_init(struct sna *sna, const char *backend)
+{
+ if (!gen8_render_setup(sna))
+ return backend;
+
+ sna->kgem.context_switch = gen6_render_context_switch;
+ sna->kgem.retire = gen6_render_retire;
+ sna->kgem.expire = gen4_render_expire;
+
+#if !NO_COMPOSITE
+ sna->render.composite = gen8_render_composite;
+ sna->render.prefer_gpu |= PREFER_GPU_RENDER;
+#endif
+#if !NO_COMPOSITE_SPANS
+ sna->render.check_composite_spans = gen8_check_composite_spans;
+ sna->render.composite_spans = gen8_render_composite_spans;
+ sna->render.prefer_gpu |= PREFER_GPU_SPANS;
+#endif
+#if !NO_VIDEO
+ sna->render.video = gen8_render_video;
+#endif
+
+#if !NO_COPY_BOXES
+ sna->render.copy_boxes = gen8_render_copy_boxes;
+#endif
+#if !NO_COPY
+ sna->render.copy = gen8_render_copy;
+#endif
+
+#if !NO_FILL_BOXES
+ sna->render.fill_boxes = gen8_render_fill_boxes;
+#endif
+#if !NO_FILL
+ sna->render.fill = gen8_render_fill;
+#endif
+#if !NO_FILL_ONE
+ sna->render.fill_one = gen8_render_fill_one;
+#endif
+#if !NO_FILL_CLEAR
+ sna->render.clear = gen8_render_clear;
+#endif
+
+ sna->render.flush = gen8_render_flush;
+ sna->render.reset = gen8_render_reset;
+ sna->render.fini = gen8_render_fini;
+
+ sna->render.max_3d_size = GEN8_MAX_SIZE;
+ sna->render.max_3d_pitch = 1 << 18;
+ return "Broadwell";
+}
diff --git a/src/sna/gen8_render.h b/src/sna/gen8_render.h
new file mode 100644
index 0000000..0bcdf10
--- /dev/null
+++ b/src/sna/gen8_render.h
@@ -0,0 +1,1132 @@
+#ifndef GEN8_RENDER_H
+#define GEN8_RENDER_H
+
+#define INTEL_MASK(high, low) (((1 << ((high) - (low) + 1)) - 1) << (low))
+
+#define GEN8_3D(pipeline,op,sub) \
+ ((3 << 29) | ((pipeline) << 27) | ((op) << 24) | ((sub) << 16))
+
+#define GEN8_STATE_BASE_ADDRESS GEN8_3D(0, 1, 1)
+# define BASE_ADDRESS_MODIFY (1 << 0)
+
+#define GEN8_STATE_SIP GEN8_3D(0, 1, 2)
+
+#define GEN8_3DSTATE_VF_STATISTICS GEN8_3D(1, 0, 0xb)
+#define GEN8_PIPELINE_SELECT GEN8_3D(1, 1, 4)
+# define PIPELINE_SELECT_3D 0
+# define PIPELINE_SELECT_MEDIA 1
+
+#define GEN8_MEDIA_STATE_POINTERS GEN8_3D(2, 0, 0)
+#define GEN8_MEDIA_OBJECT GEN8_3D(2, 1, 0)
+
+#define GEN8_3DSTATE_CLEAR_PARAMS GEN8_3D(3, 0, 0x04)
+#define GEN8_3DSTATE_DEPTH_BUFFER GEN8_3D(3, 0, 0x05)
+# define DEPTH_BUFFER_TYPE_SHIFT 29
+# define DEPTH_BUFFER_FORMAT_SHIFT 18
+/* DW1 */
+# define DEPTH_CLEAR_VALID (1 << 15)
+#define GEN8_3DSTATE_STENCIL_BUFFER GEN8_3D(3, 0, 0x06)
+#define GEN8_3DSTATE_HIER_DEPTH_BUFFER GEN8_3D(3, 0, 0x07)
+#define GEN8_3DSTATE_VERTEX_BUFFERS GEN8_3D(3, 0, 0x08)
+# define VB_INDEX_SHIFT 26
+# define VB_MODIFY_ENABLE (1 << 14)
+#define GEN8_3DSTATE_VERTEX_ELEMENTS GEN8_3D(3, 0, 0x09)
+# define VE_INDEX_SHIFT 26
+# define VE_VALID (1 << 25)
+# define VE_FORMAT_SHIFT 16
+# define VE_OFFSET_SHIFT 0
+# define VE_COMPONENT_0_SHIFT 28
+# define VE_COMPONENT_1_SHIFT 24
+# define VE_COMPONENT_2_SHIFT 20
+# define VE_COMPONENT_3_SHIFT 16
+#define GEN8_3DSTATE_INDEX_BUFFER GEN8_3D(3, 0, 0x0a)
+#define GEN8_3DSTATE_VF GEN8_3D(3, 0, 0x0c)
+
+#define GEN8_3DSTATE_MULTISAMPLE GEN8_3D(3, 0, 0x0d)
+/* DW1 */
+# define MULTISAMPLE_PIXEL_LOCATION_CENTER (0 << 4)
+# define MULTISAMPLE_PIXEL_LOCATION_UPPER_LEFT (1 << 4)
+# define MULTISAMPLE_NUMSAMPLES_1 (0 << 1)
+# define MULTISAMPLE_NUMSAMPLES_4 (2 << 1)
+# define MULTISAMPLE_NUMSAMPLES_8 (3 << 1)
+
+#define GEN8_3DSTATE_CC_STATE_POINTERS GEN8_3D(3, 0, 0x0e)
+#define GEN8_3DSTATE_SCISSOR_STATE_POINTERS GEN8_3D(3, 0, 0x0f)
+
+#define GEN8_3DSTATE_VS GEN8_3D(3, 0, 0x10)
+#define GEN8_3DSTATE_GS GEN8_3D(3, 0, 0x11)
+#define GEN8_3DSTATE_CLIP GEN8_3D(3, 0, 0x12)
+#define GEN8_3DSTATE_SF GEN8_3D(3, 0, 0x13)
+# define SF_TRI_PROVOKE_SHIFT 29
+# define SF_LINE_PROVOKE_SHIFT 27
+# define SF_FAN_PROVOKE_SHIFT 25
+
+#define GEN8_3DSTATE_WM GEN8_3D(3, 0, 0x14)
+/* DW1 */
+# define WM_STATISTICS_ENABLE (1 << 31)
+# define WM_DEPTH_CLEAR (1 << 30)
+# define WM_DISPATCH_ENABLE (1 << 29)
+# define WM_DEPTH_RESOLVE (1 << 28)
+# define WM_HIERARCHICAL_DEPTH_RESOLVE (1 << 27)
+# define WM_KILL_ENABLE (1 << 25)
+# define WM_PSCDEPTH_OFF (0 << 23)
+# define WM_PSCDEPTH_ON (1 << 23)
+# define WM_PSCDEPTH_ON_GE (2 << 23)
+# define WM_PSCDEPTH_ON_LE (3 << 23)
+# define WM_USES_SOURCE_DEPTH (1 << 20)
+# define WM_USES_SOURCE_W (1 << 19)
+# define WM_POSITION_ZW_PIXEL (0 << 17)
+# define WM_POSITION_ZW_CENTROID (2 << 17)
+# define WM_POSITION_ZW_SAMPLE (3 << 17)
+# define WM_NONPERSPECTIVE_SAMPLE_BARYCENTRIC (1 << 16)
+# define WM_NONPERSPECTIVE_CENTROID_BARYCENTRIC (1 << 15)
+# define WM_NONPERSPECTIVE_PIXEL_BARYCENTRIC (1 << 14)
+# define WM_PERSPECTIVE_SAMPLE_BARYCENTRIC (1 << 13)
+# define WM_PERSPECTIVE_CENTROID_BARYCENTRIC (1 << 12)
+# define WM_PERSPECTIVE_PIXEL_BARYCENTRIC (1 << 11)
+# define WM_USES_INPUT_COVERAGE_MASK (1 << 10)
+# define WM_LINE_END_CAP_AA_WIDTH_0_5 (0 << 8)
+# define WM_LINE_END_CAP_AA_WIDTH_1_0 (1 << 8)
+# define WM_LINE_END_CAP_AA_WIDTH_2_0 (2 << 8)
+# define WM_LINE_END_CAP_AA_WIDTH_4_0 (3 << 8)
+# define WM_LINE_AA_WIDTH_0_5 (0 << 6)
+# define WM_LINE_AA_WIDTH_1_0 (1 << 6)
+# define WM_LINE_AA_WIDTH_2_0 (2 << 6)
+# define WM_LINE_AA_WIDTH_4_0 (3 << 6)
+# define WM_POLYGON_STIPPLE_ENABLE (1 << 4)
+# define WM_LINE_STIPPLE_ENABLE (1 << 3)
+# define WM_POINT_RASTRULE_UPPER_RIGHT (1 << 2)
+# define WM_MSRAST_OFF_PIXEL (0 << 0)
+# define WM_MSRAST_OFF_PATTERN (1 << 0)
+# define WM_MSRAST_ON_PIXEL (2 << 0)
+# define WM_MSRAST_ON_PATTERN (3 << 0)
+/* DW2 */
+# define WM_MSDISPMODE_PERPIXEL (1 << 31)
+
+#define GEN8_3DSTATE_CONSTANT_VS GEN8_3D(3, 0, 0x15)
+#define GEN8_3DSTATE_CONSTANT_GS GEN8_3D(3, 0, 0x16)
+#define GEN8_3DSTATE_CONSTANT_PS GEN8_3D(3, 0, 0x17)
+
+#define GEN8_3DSTATE_SAMPLE_MASK GEN8_3D(3, 0, 0x18)
+
+#define GEN8_3DSTATE_CONSTANT_HS GEN8_3D(3, 0, 0x19)
+#define GEN8_3DSTATE_CONSTANT_DS GEN8_3D(3, 0, 0x1a)
+
+#define GEN8_3DSTATE_HS GEN8_3D(3, 0, 0x1b)
+#define GEN8_3DSTATE_TE GEN8_3D(3, 0, 0x1c)
+#define GEN8_3DSTATE_DS GEN8_3D(3, 0, 0x1d)
+#define GEN8_3DSTATE_STREAMOUT GEN8_3D(3, 0, 0x1e)
+
+#define GEN8_3DSTATE_SBE GEN8_3D(3, 0, 0x1f)
+/* DW1 */
+# define SBE_FORCE_VERTEX_URB_READ_LENGTH (1<<29)
+# define SBE_FORCE_VERTEX_URB_READ_OFFSET (1<<28)
+# define SBE_NUM_OUTPUTS_SHIFT 22
+# define SBE_SWIZZLE_ENABLE (1 << 21)
+# define SBE_POINT_SPRITE_LOWERLEFT (1 << 20)
+# define SBE_URB_ENTRY_READ_LENGTH_SHIFT 11
+# define SBE_URB_ENTRY_READ_OFFSET_SHIFT 4
+
+#define GEN8_3DSTATE_PS GEN8_3D(3, 0, 0x20)
+/* DW1: kernel pointer */
+/* DW2 */
+# define PS_SPF_MODE (1 << 31)
+# define PS_VECTOR_MASK_ENABLE (1 << 30)
+# define PS_SAMPLER_COUNT_SHIFT 27
+# define PS_BINDING_TABLE_ENTRY_COUNT_SHIFT 18
+# define PS_FLOATING_POINT_MODE_IEEE_754 (0 << 16)
+# define PS_FLOATING_POINT_MODE_ALT (1 << 16)
+/* DW3: scratch space */
+/* DW4 */
+# define PS_MAX_THREADS_SHIFT 23
+# define PS_MAX_THREADS (62 << PS_MAX_THREADS_SHIFT)
+# define PS_SAMPLE_MASK_SHIFT 12
+# define PS_PUSH_CONSTANT_ENABLE (1 << 11)
+# define PS_RENDER_TARGET_CLEAR (1 << 8)
+# define PS_RENDER_TARGET_RESOLVE (1 << 6)
+# define PS_POSOFFSET_NONE (0 << 3)
+# define PS_POSOFFSET_CENTROID (2 << 3)
+# define PS_POSOFFSET_SAMPLE (3 << 3)
+# define PS_32_DISPATCH_ENABLE (1 << 2)
+# define PS_16_DISPATCH_ENABLE (1 << 1)
+# define PS_8_DISPATCH_ENABLE (1 << 0)
+/* DW5 */
+# define PS_DISPATCH_START_GRF_SHIFT_0 16
+# define PS_DISPATCH_START_GRF_SHIFT_1 8
+# define PS_DISPATCH_START_GRF_SHIFT_2 0
+/* DW6: kernel 1 pointer */
+/* DW7: kernel 2 pointer */
+
+#define GEN8_3DSTATE_VIEWPORT_STATE_POINTERS_SF_CLIP GEN8_3D(3, 0, 0x21)
+#define GEN8_3DSTATE_VIEWPORT_STATE_POINTERS_CC GEN8_3D(3, 0, 0x23)
+
+#define GEN8_3DSTATE_BLEND_STATE_POINTERS GEN8_3D(3, 0, 0x24)
+
+#define GEN8_3DSTATE_BINDING_TABLE_POINTERS_VS GEN8_3D(3, 0, 0x26)
+#define GEN8_3DSTATE_BINDING_TABLE_POINTERS_HS GEN8_3D(3, 0, 0x27)
+#define GEN8_3DSTATE_BINDING_TABLE_POINTERS_DS GEN8_3D(3, 0, 0x28)
+#define GEN8_3DSTATE_BINDING_TABLE_POINTERS_GS GEN8_3D(3, 0, 0x29)
+#define GEN8_3DSTATE_BINDING_TABLE_POINTERS_PS GEN8_3D(3, 0, 0x2a)
+
+#define GEN8_3DSTATE_SAMPLER_STATE_POINTERS_VS GEN8_3D(3, 0, 0x2b)
+#define GEN8_3DSTATE_SAMPLER_STATE_POINTERS_HS GEN8_3D(3, 0, 0x2c)
+#define GEN8_3DSTATE_SAMPLER_STATE_POINTERS_DS GEN8_3D(3, 0, 0x2d)
+#define GEN8_3DSTATE_SAMPLER_STATE_POINTERS_GS GEN8_3D(3, 0, 0x2e)
+#define GEN8_3DSTATE_SAMPLER_STATE_POINTERS_PS GEN8_3D(3, 0, 0x2f)
+
+#define GEN8_3DSTATE_URB_VS GEN8_3D(3, 0, 0x30)
+#define GEN8_3DSTATE_URB_HS GEN8_3D(3, 0, 0x31)
+#define GEN8_3DSTATE_URB_DS GEN8_3D(3, 0, 0x32)
+#define GEN8_3DSTATE_URB_GS GEN8_3D(3, 0, 0x33)
+/* DW1 */
+# define URB_ENTRY_NUMBER_SHIFT 0
+# define URB_ENTRY_SIZE_SHIFT 16
+# define URB_STARTING_ADDRESS_SHIFT 25
+
+#define GEN8_3DSTATE_GATHER_CONSTANT_VS GEN8_3D(3, 0, 0x34)
+#define GEN8_3DSTATE_GATHER_CONSTANT_GS GEN8_3D(3, 0, 0x35)
+#define GEN8_3DSTATE_GATHER_CONSTANT_HS GEN8_3D(3, 0, 0x36)
+#define GEN8_3DSTATE_GATHER_CONSTANT_DS GEN8_3D(3, 0, 0x37)
+#define GEN8_3DSTATE_GATHER_CONSTANT_PS GEN8_3D(3, 0, 0x38)
+
+#define GEN8_3DSTATE_DX9_CONSTANTF_VS GEN8_3D(3, 0, 0x39)
+#define GEN8_3DSTATE_DX9_CONSTANTF_PS GEN8_3D(3, 0, 0x3a)
+#define GEN8_3DSTATE_DX9_CONSTANTI_VS GEN8_3D(3, 0, 0x3b)
+#define GEN8_3DSTATE_DX9_CONSTANTI_PS GEN8_3D(3, 0, 0x3c)
+#define GEN8_3DSTATE_DX9_CONSTANTB_VS GEN8_3D(3, 0, 0x3d)
+#define GEN8_3DSTATE_DX9_CONSTANTB_PS GEN8_3D(3, 0, 0x3e)
+#define GEN8_3DSTATE_DX9_LOCAL_VALID_VS GEN8_3D(3, 0, 0x3f)
+#define GEN8_3DSTATE_DX9_LOCAL_VALID_PS GEN8_3D(3, 0, 0x40)
+#define GEN8_3DSTATE_DX9_GENERATE_ACTIVE_VS GEN8_3D(3, 0, 0x41)
+#define GEN8_3DSTATE_DX9_GENERATE_ACTIVE_PS GEN8_3D(3, 0, 0x42)
+
+#define GEN8_3DSTATE_BINDING_TABLE_EDIT_VS GEN8_3D(3, 0, 0x43)
+#define GEN8_3DSTATE_BINDING_TABLE_EDIT_GS GEN8_3D(3, 0, 0x44)
+#define GEN8_3DSTATE_BINDING_TABLE_EDIT_HS GEN8_3D(3, 0, 0x45)
+#define GEN8_3DSTATE_BINDING_TABLE_EDIT_DS GEN8_3D(3, 0, 0x46)
+#define GEN8_3DSTATE_BINDING_TABLE_EDIT_PS GEN8_3D(3, 0, 0x47)
+
+#define GEN8_3DSTATE_VF_INSTANCING GEN8_3D(3, 0, 0x49)
+#define GEN8_3DSTATE_VF_SGVS GEN8_3D(3, 0, 0x4a)
+# define SGVS_ENABLE_INSTANCE_ID (1 << 31)
+# define SGVS_INSTANCE_ID_COMPONENT_SHIFT 29
+# define SGVS_INSTANCE_ID_ELEMENT_OFFSET_SHIFT 16
+# define SGVS_ENABLE_VERTEX_ID (1 << 15)
+# define SGVS_VERTEX_ID_COMPONENT_SHIFT 13
+# define SGVS_VERTEX_ID_ELEMENT_OFFSET_SHIFT 0
+#define GEN8_3DSTATE_VF_TOPOLOGY GEN8_3D(3, 0, 0x4b)
+# define POINTLIST 0x01
+# define LINELIST 0x02
+# define LINESTRIP 0x03
+# define TRILIST 0x04
+# define TRISTRIP 0x05
+# define TRIFAN 0x06
+# define QUADLIST 0x07
+# define QUADSTRIP 0x08
+# define LINELIST_ADJ 0x09
+# define LINESTRIP_ADJ 0x0A
+# define TRILIST_ADJ 0x0B
+# define TRISTRIP_ADJ 0x0C
+# define TRISTRIP_REVERSE 0x0D
+# define POLYGON 0x0E
+# define RECTLIST 0x0F
+# define LINELOOP 0x10
+# define POINTLIST_BF 0x11
+# define LINESTRIP_CONT 0x12
+# define LINESTRIP_BF 0x13
+# define LINESTRIP_CONT_BF 0x14
+# define TRIFAN_NOSTIPPLE 0x15
+
+#define GEN8_3DSTATE_WM_CHROMAKEY GEN8_3D(3, 0, 0x4c)
+
+#define GEN8_3DSTATE_PS_BLEND GEN8_3D(3, 0, 0x4d)
+# define PS_BLEND_ALPHA_TO_COVERAGE_ENABLE (1 << 31)
+# define PS_BLEND_HAS_WRITEABLE_RT (1 << 30)
+# define PS_BLEND_COLOR_BLEND_ENABLE (1 << 29)
+# define PS_BLEND_SRC_ALPHA_SHIFT 24
+# define PS_BLEND_DST_ALPHA_SHIFT 19
+# define PS_BLEND_SRC_SHIFT 14
+# define PS_BLEND_DST_SHIFT 9
+# define PS_BLEND_ALPHA_TEST_ENABLE (1 << 8)
+# define PS_BLEND_INDEPENDENT_ALPHA_BLEND_ENABLE (1 << 7)
+
+#define GEN8_3DSTATE_WM_DEPTH_STENCIL GEN8_3D(3, 0, 0x4e)
+/* DW1 */
+# define WM_DS_STENCIL_TEST_MASK_MASK INTEL_MASK(31, 24)
+# define WM_DS_STENCIL_TEST_MASK_SHIFT 24
+# define WM_DS_STENCIL_WRITE_MASK_MASK INTEL_MASK(23, 16)
+# define WM_DS_STENCIL_WRITE_MASK_SHIFT 16
+# define WM_DS_BF_STENCIL_TEST_MASK_MASK INTEL_MASK(15, 8)
+# define WM_DS_BF_STENCIL_TEST_MASK_SHIFT 8
+# define WM_DS_BF_STENCIL_WRITE_MASK_MASK INTEL_MASK(7, 0)
+# define WM_DS_DEPTH_FUNC_SHIFT 5
+# define WM_DS_DOUBLE_SIDED_STENCIL_ENABLE (1 << 4)
+# define WM_DS_STENCIL_TEST_ENABLE (1 << 3)
+# define WM_DS_STENCIL_BUFFER_WRITE_ENABLE (1 << 2)
+# define WM_DS_DEPTH_TEST_ENABLE (1 << 1)
+# define WM_DS_DEPTH_BUFFER_WRITE_ENABLE (1 << 0)
+/* DW2 */
+# define WM_DS_STENCIL_TEST_MASK_MASK INTEL_MASK(31, 24)
+# define WM_DS_STENCIL_TEST_MASK_SHIFT 24
+# define WM_DS_STENCIL_WRITE_MASK_MASK INTEL_MASK(23, 16)
+# define WM_DS_STENCIL_WRITE_MASK_SHIFT 16
+# define WM_DS_BF_STENCIL_TEST_MASK_MASK INTEL_MASK(15, 8)
+# define WM_DS_BF_STENCIL_TEST_MASK_SHIFT 8
+# define WM_DS_BF_STENCIL_WRITE_MASK_MASK INTEL_MASK(7, 0)
+# define WM_DS_BF_STENCIL_WRITE_MASK_SHIFT 0
+
+#define GEN8_3DSTATE_PS_EXTRA GEN8_3D(3, 0, 0x4f)
+# define PSX_PIXEL_SHADER_VALID (1 << 31)
+# define PSX_PIXEL_SHADER_NO_RT_WRITE (1 << 30)
+# define PSX_OMASK_TO_RENDER_TARGET (1 << 29)
+# define PSX_KILL_ENABLE (1 << 28)
+# define PSX_PSCDEPTH_OFF (0 << 26)
+# define PSX_PSCDEPTH_ON (1 << 26)
+# define PSX_PSCDEPTH_ON_GE (2 << 26)
+# define PSX_PSCDEPTH_ON_LE (3 << 26)
+# define PSX_FORCE_COMPUTED_DEPTH (1 << 25)
+# define PSX_USES_SOURCE_DEPTH (1 << 24)
+# define PSX_USES_SOURCE_W (1 << 23)
+# define PSX_ATTRIBUTE_ENABLE (1 << 8)
+# define PSX_SHADER_DISABLES_ALPHA_TO_COVERAGE (1 << 7)
+# define PSX_SHADER_IS_PER_SAMPLE (1 << 6)
+# define PSX_SHADER_HAS_UAV (1 << 2)
+# define PSX_SHADER_USES_INPUT_COVERAGE_MASK (1 << 1)
+
+#define GEN8_3DSTATE_RASTER GEN8_3D(3, 0, 0x50)
+/* DW1 */
+# define RASTER_FRONT_WINDING_CCW (1 << 21)
+# define RASTER_CULL_BOTH (0 << 16)
+# define RASTER_CULL_NONE (1 << 16)
+# define RASTER_CULL_FRONT (2 << 16)
+# define RASTER_CULL_BACK (3 << 16)
+# define RASTER_SMOOTH_POINT_ENABLE (1 << 13)
+# define RASTER_LINE_AA_ENABLE (1 << 2)
+# define RASTER_VIEWPORT_Z_CLIP_TEST_ENABLE (1 << 0)
+
+#define GEN8_3DSTATE_SBE_SWIZ GEN8_3D(3, 0, 0x51)
+#define GEN8_3DSTATE_WM_HZ_OP GEN8_3D(3, 0, 0x52)
+
+
+#define GEN8_3DSTATE_DRAWING_RECTANGLE GEN8_3D(3, 1, 0x00)
+#define GEN8_3DSTATE_SAMPLER_PALETTE_LOAD GEN8_3D(3, 1, 0x02)
+#define GEN8_3DSTATE_CHROMA_KEY GEN8_3D(3, 1, 0x04)
+
+#define GEN8_3DSTATE_POLY_STIPPLE_OFFSET GEN8_3D(3, 1, 0x06)
+#define GEN8_3DSTATE_POLY_STIPPLE_PATTERN GEN8_3D(3, 1, 0x07)
+#define GEN8_3DSTATE_LINE_STIPPLE GEN8_3D(3, 1, 0x08)
+#define GEN8_3DSTATE_AA_LINE_PARAMS GEN8_3D(3, 1, 0x0a)
+#define GEN8_3DSTATE_SAMPLER_PALETTE_LOAD1 GEN8_3D(3, 1, 0x0c)
+#define GEN8_3DSTATE_MONOFILTER_SIZE GEN8_3D(3, 1, 0x11)
+#define GEN8_3DSTATE_PUSH_CONSTANT_ALLOC_VS GEN8_3D(3, 1, 0x12)
+#define GEN8_3DSTATE_PUSH_CONSTANT_ALLOC_HS GEN8_3D(3, 1, 0x13)
+#define GEN8_3DSTATE_PUSH_CONSTANT_ALLOC_DS GEN8_3D(3, 1, 0x14)
+#define GEN8_3DSTATE_PUSH_CONSTANT_ALLOC_GS GEN8_3D(3, 1, 0x15)
+#define GEN8_3DSTATE_PUSH_CONSTANT_ALLOC_PS GEN8_3D(3, 1, 0x16)
+/* DW1 */
+# define PUSH_CONSTANT_BUFFER_OFFSET_SHIFT 16
+# define PUSH_CONSTANT_BUFFER_SIZE_SHIFT 0
+
+#define GEN8_3DSTATE_SO_DECL_LIST GEN8_3D(3, 1, 0x17)
+#define GEN8_3DSTATE_SO_BUFFER GEN8_3D(3, 1, 0x18)
+#define GEN8_3DSTATE_BINDING_TABLE_POOL_ALLOC GEN8_3D(3, 1, 0x19)
+#define GEN8_3DSTATE_GATHER_BUFFER_POOL_ALLOC GEN8_3D(3, 1, 0x1a)
+#define GEN8_3DSTATE_DX9_CONSTANT_BUFFER_POOL_ALLOC GEN8_3D(3, 1, 0x1b)
+#define GEN8_3DSTATE_SAMPLE_PATTERN GEN8_3D(3, 1, 0x1c)
+
+
+/* for GEN8_PIPE_CONTROL */
+#define GEN8_PIPE_CONTROL GEN8_3D(3, 2, 0)
+#define PIPE_CONTROL_CS_STALL (1 << 20)
+#define PIPE_CONTROL_NOWRITE (0 << 14)
+#define PIPE_CONTROL_WRITE_QWORD (1 << 14)
+#define PIPE_CONTROL_WRITE_DEPTH (2 << 14)
+#define PIPE_CONTROL_WRITE_TIME (3 << 14)
+#define PIPE_CONTROL_DEPTH_STALL (1 << 13)
+#define PIPE_CONTROL_WC_FLUSH (1 << 12)
+#define PIPE_CONTROL_IS_FLUSH (1 << 11)
+#define PIPE_CONTROL_TC_FLUSH (1 << 10)
+#define PIPE_CONTROL_NOTIFY_ENABLE (1 << 8)
+#define PIPE_CONTROL_GLOBAL_GTT (1 << 2)
+#define PIPE_CONTROL_LOCAL_PGTT (0 << 2)
+#define PIPE_CONTROL_STALL_AT_SCOREBOARD (1 << 1)
+#define PIPE_CONTROL_DEPTH_CACHE_FLUSH (1 << 0)
+
+
+#define GEN8_3DPRIMITIVE GEN8_3D(3, 3, 0)
+
+/* 3DPRIMITIVE bits */
+#define VERTEX_SEQUENTIAL (0 << 15)
+#define VERTEX_RANDOM (1 << 15)
+
+#define ANISORATIO_2 0
+#define ANISORATIO_4 1
+#define ANISORATIO_6 2
+#define ANISORATIO_8 3
+#define ANISORATIO_10 4
+#define ANISORATIO_12 5
+#define ANISORATIO_14 6
+#define ANISORATIO_16 7
+
+#define BLENDFACTOR_ONE 0x1
+#define BLENDFACTOR_SRC_COLOR 0x2
+#define BLENDFACTOR_SRC_ALPHA 0x3
+#define BLENDFACTOR_DST_ALPHA 0x4
+#define BLENDFACTOR_DST_COLOR 0x5
+#define BLENDFACTOR_SRC_ALPHA_SATURATE 0x6
+#define BLENDFACTOR_CONST_COLOR 0x7
+#define BLENDFACTOR_CONST_ALPHA 0x8
+#define BLENDFACTOR_SRC1_COLOR 0x9
+#define BLENDFACTOR_SRC1_ALPHA 0x0A
+#define BLENDFACTOR_ZERO 0x11
+#define BLENDFACTOR_INV_SRC_COLOR 0x12
+#define BLENDFACTOR_INV_SRC_ALPHA 0x13
+#define BLENDFACTOR_INV_DST_ALPHA 0x14
+#define BLENDFACTOR_INV_DST_COLOR 0x15
+#define BLENDFACTOR_INV_CONST_COLOR 0x17
+#define BLENDFACTOR_INV_CONST_ALPHA 0x18
+#define BLENDFACTOR_INV_SRC1_COLOR 0x19
+#define BLENDFACTOR_INV_SRC1_ALPHA 0x1A
+
+#define BLENDFUNCTION_ADD 0
+#define BLENDFUNCTION_SUBTRACT 1
+#define BLENDFUNCTION_REVERSE_SUBTRACT 2
+#define GEN8_BLENDFUNCTION_MIN 3
+#define BLENDFUNCTION_MAX 4
+
+#define ALPHATEST_FORMAT_UNORM8 0
+#define ALPHATEST_FORMAT_FLOAT32 1
+
+#define CHROMAKEY_KILL_ON_ANY_MATCH 0
+#define CHROMAKEY_REPLACE_BLACK 1
+
+#define CLIP_API_OGL 0
+#define CLIP_API_DX 1
+
+#define CLIPMODE_NORMAL 0
+#define CLIPMODE_CLIP_ALL 1
+#define CLIPMODE_CLIP_NON_REJECTED 2
+#define CLIPMODE_REJECT_ALL 3
+#define CLIPMODE_ACCEPT_ALL 4
+
+#define CLIP_NDCSPACE 0
+#define CLIP_SCREENSPACE 1
+
+#define COMPAREFUNCTION_ALWAYS 0
+#define COMPAREFUNCTION_NEVER 1
+#define COMPAREFUNCTION_LESS 2
+#define COMPAREFUNCTION_EQUAL 3
+#define COMPAREFUNCTION_LEQUAL 4
+#define COMPAREFUNCTION_GREATER 5
+#define COMPAREFUNCTION_NOTEQUAL 6
+#define COMPAREFUNCTION_GEQUAL 7
+
+#define COVERAGE_PIXELS_HALF 0
+#define COVERAGE_PIXELS_1 1
+#define COVERAGE_PIXELS_2 2
+#define COVERAGE_PIXELS_4 3
+
+#define DEPTHFORMAT_D32_FLOAT_S8X24_UINT 0
+#define DEPTHFORMAT_D32_FLOAT 1
+#define DEPTHFORMAT_D24_UNORM_S8_UINT 2
+#define DEPTHFORMAT_D16_UNORM 5
+
+#define FLOATING_POINT_IEEE_754 0
+#define FLOATING_POINT_NON_IEEE_754 1
+
+#define INDEX_BYTE 0
+#define INDEX_WORD 1
+#define INDEX_DWORD 2
+
+#define LOGICOPFUNCTION_CLEAR 0
+#define LOGICOPFUNCTION_NOR 1
+#define LOGICOPFUNCTION_AND_INVERTED 2
+#define LOGICOPFUNCTION_COPY_INVERTED 3
+#define LOGICOPFUNCTION_AND_REVERSE 4
+#define LOGICOPFUNCTION_INVERT 5
+#define LOGICOPFUNCTION_XOR 6
+#define LOGICOPFUNCTION_NAND 7
+#define LOGICOPFUNCTION_AND 8
+#define LOGICOPFUNCTION_EQUIV 9
+#define LOGICOPFUNCTION_NOOP 10
+#define LOGICOPFUNCTION_OR_INVERTED 11
+#define LOGICOPFUNCTION_COPY 12
+#define LOGICOPFUNCTION_OR_REVERSE 13
+#define LOGICOPFUNCTION_OR 14
+#define LOGICOPFUNCTION_SET 15
+
+#define MAPFILTER_NEAREST 0x0
+#define MAPFILTER_LINEAR 0x1
+#define MAPFILTER_ANISOTROPIC 0x2
+#define MAPFILTER_FLEXIBLE 0x3
+#define MAPFILTER_MONO 0x6
+
+#define MIPFILTER_NONE 0
+#define MIPFILTER_NEAREST 1
+#define MIPFILTER_LINEAR 3
+
+#define POLYGON_FRONT_FACING 0
+#define POLYGON_BACK_FACING 1
+
+#define PREFILTER_ALWAYS 0x0
+#define PREFILTER_NEVER 0x1
+#define PREFILTER_LESS 0x2
+#define PREFILTER_EQUAL 0x3
+#define PREFILTER_LEQUAL 0x4
+#define PREFILTER_GREATER 0x5
+#define PREFILTER_NOTEQUAL 0x6
+#define PREFILTER_GEQUAL 0x7
+
+#define RASTRULE_UPPER_LEFT 0
+#define RASTRULE_UPPER_RIGHT 1
+
+#define STENCILOP_KEEP 0
+#define STENCILOP_ZERO 1
+#define STENCILOP_REPLACE 2
+#define STENCILOP_INCRSAT 3
+#define STENCILOP_DECRSAT 4
+#define STENCILOP_INCR 5
+#define STENCILOP_DECR 6
+#define STENCILOP_INVERT 7
+
+#define SURFACE_MIPMAPLAYOUT_BELOW 0
+#define SURFACE_MIPMAPLAYOUT_RIGHT 1
+
+#define SURFACEFORMAT_R32G32B32A32_FLOAT 0x000
+#define SURFACEFORMAT_R32G32B32A32_SINT 0x001
+#define SURFACEFORMAT_R32G32B32A32_UINT 0x002
+#define SURFACEFORMAT_R32G32B32A32_UNORM 0x003
+#define SURFACEFORMAT_R32G32B32A32_SNORM 0x004
+#define SURFACEFORMAT_R64G64_FLOAT 0x005
+#define SURFACEFORMAT_R32G32B32X32_FLOAT 0x006
+#define SURFACEFORMAT_R32G32B32A32_SSCALED 0x007
+#define SURFACEFORMAT_R32G32B32A32_USCALED 0x008
+#define SURFACEFORMAT_R32G32B32_FLOAT 0x040
+#define SURFACEFORMAT_R32G32B32_SINT 0x041
+#define SURFACEFORMAT_R32G32B32_UINT 0x042
+#define SURFACEFORMAT_R32G32B32_UNORM 0x043
+#define SURFACEFORMAT_R32G32B32_SNORM 0x044
+#define SURFACEFORMAT_R32G32B32_SSCALED 0x045
+#define SURFACEFORMAT_R32G32B32_USCALED 0x046
+#define SURFACEFORMAT_R16G16B16A16_UNORM 0x080
+#define SURFACEFORMAT_R16G16B16A16_SNORM 0x081
+#define SURFACEFORMAT_R16G16B16A16_SINT 0x082
+#define SURFACEFORMAT_R16G16B16A16_UINT 0x083
+#define SURFACEFORMAT_R16G16B16A16_FLOAT 0x084
+#define SURFACEFORMAT_R32G32_FLOAT 0x085
+#define SURFACEFORMAT_R32G32_SINT 0x086
+#define SURFACEFORMAT_R32G32_UINT 0x087
+#define SURFACEFORMAT_R32_FLOAT_X8X24_TYPELESS 0x088
+#define SURFACEFORMAT_X32_TYPELESS_G8X24_UINT 0x089
+#define SURFACEFORMAT_L32A32_FLOAT 0x08A
+#define SURFACEFORMAT_R32G32_UNORM 0x08B
+#define SURFACEFORMAT_R32G32_SNORM 0x08C
+#define SURFACEFORMAT_R64_FLOAT 0x08D
+#define SURFACEFORMAT_R16G16B16X16_UNORM 0x08E
+#define SURFACEFORMAT_R16G16B16X16_FLOAT 0x08F
+#define SURFACEFORMAT_A32X32_FLOAT 0x090
+#define SURFACEFORMAT_L32X32_FLOAT 0x091
+#define SURFACEFORMAT_I32X32_FLOAT 0x092
+#define SURFACEFORMAT_R16G16B16A16_SSCALED 0x093
+#define SURFACEFORMAT_R16G16B16A16_USCALED 0x094
+#define SURFACEFORMAT_R32G32_SSCALED 0x095
+#define SURFACEFORMAT_R32G32_USCALED 0x096
+#define SURFACEFORMAT_B8G8R8A8_UNORM 0x0C0
+#define SURFACEFORMAT_B8G8R8A8_UNORM_SRGB 0x0C1
+#define SURFACEFORMAT_R10G10B10A2_UNORM 0x0C2
+#define SURFACEFORMAT_R10G10B10A2_UNORM_SRGB 0x0C3
+#define SURFACEFORMAT_R10G10B10A2_UINT 0x0C4
+#define SURFACEFORMAT_R10G10B10_SNORM_A2_UNORM 0x0C5
+#define SURFACEFORMAT_R8G8B8A8_UNORM 0x0C7
+#define SURFACEFORMAT_R8G8B8A8_UNORM_SRGB 0x0C8
+#define SURFACEFORMAT_R8G8B8A8_SNORM 0x0C9
+#define SURFACEFORMAT_R8G8B8A8_SINT 0x0CA
+#define SURFACEFORMAT_R8G8B8A8_UINT 0x0CB
+#define SURFACEFORMAT_R16G16_UNORM 0x0CC
+#define SURFACEFORMAT_R16G16_SNORM 0x0CD
+#define SURFACEFORMAT_R16G16_SINT 0x0CE
+#define SURFACEFORMAT_R16G16_UINT 0x0CF
+#define SURFACEFORMAT_R16G16_FLOAT 0x0D0
+#define SURFACEFORMAT_B10G10R10A2_UNORM 0x0D1
+#define SURFACEFORMAT_B10G10R10A2_UNORM_SRGB 0x0D2
+#define SURFACEFORMAT_R11G11B10_FLOAT 0x0D3
+#define SURFACEFORMAT_R32_SINT 0x0D6
+#define SURFACEFORMAT_R32_UINT 0x0D7
+#define SURFACEFORMAT_R32_FLOAT 0x0D8
+#define SURFACEFORMAT_R24_UNORM_X8_TYPELESS 0x0D9
+#define SURFACEFORMAT_X24_TYPELESS_G8_UINT 0x0DA
+#define SURFACEFORMAT_L16A16_UNORM 0x0DF
+#define SURFACEFORMAT_I24X8_UNORM 0x0E0
+#define SURFACEFORMAT_L24X8_UNORM 0x0E1
+#define SURFACEFORMAT_A24X8_UNORM 0x0E2
+#define SURFACEFORMAT_I32_FLOAT 0x0E3
+#define SURFACEFORMAT_L32_FLOAT 0x0E4
+#define SURFACEFORMAT_A32_FLOAT 0x0E5
+#define SURFACEFORMAT_B8G8R8X8_UNORM 0x0E9
+#define SURFACEFORMAT_B8G8R8X8_UNORM_SRGB 0x0EA
+#define SURFACEFORMAT_R8G8B8X8_UNORM 0x0EB
+#define SURFACEFORMAT_R8G8B8X8_UNORM_SRGB 0x0EC
+#define SURFACEFORMAT_R9G9B9E5_SHAREDEXP 0x0ED
+#define SURFACEFORMAT_B10G10R10X2_UNORM 0x0EE
+#define SURFACEFORMAT_L16A16_FLOAT 0x0F0
+#define SURFACEFORMAT_R32_UNORM 0x0F1
+#define SURFACEFORMAT_R32_SNORM 0x0F2
+#define SURFACEFORMAT_R10G10B10X2_USCALED 0x0F3
+#define SURFACEFORMAT_R8G8B8A8_SSCALED 0x0F4
+#define SURFACEFORMAT_R8G8B8A8_USCALED 0x0F5
+#define SURFACEFORMAT_R16G16_SSCALED 0x0F6
+#define SURFACEFORMAT_R16G16_USCALED 0x0F7
+#define SURFACEFORMAT_R32_SSCALED 0x0F8
+#define SURFACEFORMAT_R32_USCALED 0x0F9
+#define SURFACEFORMAT_B5G6R5_UNORM 0x100
+#define SURFACEFORMAT_B5G6R5_UNORM_SRGB 0x101
+#define SURFACEFORMAT_B5G5R5A1_UNORM 0x102
+#define SURFACEFORMAT_B5G5R5A1_UNORM_SRGB 0x103
+#define SURFACEFORMAT_B4G4R4A4_UNORM 0x104
+#define SURFACEFORMAT_B4G4R4A4_UNORM_SRGB 0x105
+#define SURFACEFORMAT_R8G8_UNORM 0x106
+#define SURFACEFORMAT_R8G8_SNORM 0x107
+#define SURFACEFORMAT_R8G8_SINT 0x108
+#define SURFACEFORMAT_R8G8_UINT 0x109
+#define SURFACEFORMAT_R16_UNORM 0x10A
+#define SURFACEFORMAT_R16_SNORM 0x10B
+#define SURFACEFORMAT_R16_SINT 0x10C
+#define SURFACEFORMAT_R16_UINT 0x10D
+#define SURFACEFORMAT_R16_FLOAT 0x10E
+#define SURFACEFORMAT_I16_UNORM 0x111
+#define SURFACEFORMAT_L16_UNORM 0x112
+#define SURFACEFORMAT_A16_UNORM 0x113
+#define SURFACEFORMAT_L8A8_UNORM 0x114
+#define SURFACEFORMAT_I16_FLOAT 0x115
+#define SURFACEFORMAT_L16_FLOAT 0x116
+#define SURFACEFORMAT_A16_FLOAT 0x117
+#define SURFACEFORMAT_R5G5_SNORM_B6_UNORM 0x119
+#define SURFACEFORMAT_B5G5R5X1_UNORM 0x11A
+#define SURFACEFORMAT_B5G5R5X1_UNORM_SRGB 0x11B
+#define SURFACEFORMAT_R8G8_SSCALED 0x11C
+#define SURFACEFORMAT_R8G8_USCALED 0x11D
+#define SURFACEFORMAT_R16_SSCALED 0x11E
+#define SURFACEFORMAT_R16_USCALED 0x11F
+#define SURFACEFORMAT_R8_UNORM 0x140
+#define SURFACEFORMAT_R8_SNORM 0x141
+#define SURFACEFORMAT_R8_SINT 0x142
+#define SURFACEFORMAT_R8_UINT 0x143
+#define SURFACEFORMAT_A8_UNORM 0x144
+#define SURFACEFORMAT_I8_UNORM 0x145
+#define SURFACEFORMAT_L8_UNORM 0x146
+#define SURFACEFORMAT_P4A4_UNORM 0x147
+#define SURFACEFORMAT_A4P4_UNORM 0x148
+#define SURFACEFORMAT_R8_SSCALED 0x149
+#define SURFACEFORMAT_R8_USCALED 0x14A
+#define SURFACEFORMAT_R1_UINT 0x181
+#define SURFACEFORMAT_YCRCB_NORMAL 0x182
+#define SURFACEFORMAT_YCRCB_SWAPUVY 0x183
+#define SURFACEFORMAT_BC1_UNORM 0x186
+#define SURFACEFORMAT_BC2_UNORM 0x187
+#define SURFACEFORMAT_BC3_UNORM 0x188
+#define SURFACEFORMAT_BC4_UNORM 0x189
+#define SURFACEFORMAT_BC5_UNORM 0x18A
+#define SURFACEFORMAT_BC1_UNORM_SRGB 0x18B
+#define SURFACEFORMAT_BC2_UNORM_SRGB 0x18C
+#define SURFACEFORMAT_BC3_UNORM_SRGB 0x18D
+#define SURFACEFORMAT_MONO8 0x18E
+#define SURFACEFORMAT_YCRCB_SWAPUV 0x18F
+#define SURFACEFORMAT_YCRCB_SWAPY 0x190
+#define SURFACEFORMAT_DXT1_RGB 0x191
+#define SURFACEFORMAT_FXT1 0x192
+#define SURFACEFORMAT_R8G8B8_UNORM 0x193
+#define SURFACEFORMAT_R8G8B8_SNORM 0x194
+#define SURFACEFORMAT_R8G8B8_SSCALED 0x195
+#define SURFACEFORMAT_R8G8B8_USCALED 0x196
+#define SURFACEFORMAT_R64G64B64A64_FLOAT 0x197
+#define SURFACEFORMAT_R64G64B64_FLOAT 0x198
+#define SURFACEFORMAT_BC4_SNORM 0x199
+#define SURFACEFORMAT_BC5_SNORM 0x19A
+#define SURFACEFORMAT_R16G16B16_UNORM 0x19C
+#define SURFACEFORMAT_R16G16B16_SNORM 0x19D
+#define SURFACEFORMAT_R16G16B16_SSCALED 0x19E
+#define SURFACEFORMAT_R16G16B16_USCALED 0x19F
+
+#define SURFACE_1D 0
+#define SURFACE_2D 1
+#define SURFACE_3D 2
+#define SURFACE_CUBE 3
+#define SURFACE_BUFFER 4
+#define SURFACE_NULL 7
+
+#define TEXCOORDMODE_WRAP 0
+#define TEXCOORDMODE_MIRROR 1
+#define TEXCOORDMODE_CLAMP 2
+#define TEXCOORDMODE_CUBE 3
+#define TEXCOORDMODE_CLAMP_BORDER 4
+#define TEXCOORDMODE_MIRROR_ONCE 5
+
+#define THREAD_PRIORITY_NORMAL 0
+#define THREAD_PRIORITY_HIGH 1
+
+#define VERTEX_SUBPIXEL_PRECISION_8BITS 0
+#define VERTEX_SUBPIXEL_PRECISION_4BITS 1
+
+#define COMPONENT_NOSTORE 0
+#define COMPONENT_STORE_SRC 1
+#define COMPONENT_STORE_0 2
+#define COMPONENT_STORE_1_FLT 3
+#define COMPONENT_STORE_1_INT 4
+#define COMPONENT_STORE_VID 5
+#define COMPONENT_STORE_IID 6
+#define COMPONENT_STORE_PID 7
+
+/* Execution Unit (EU) defines
+ */
+
+#define GEN8_ALIGN_1 0
+#define GEN8_ALIGN_16 1
+
+#define GEN8_ADDRESS_DIRECT 0
+#define GEN8_ADDRESS_REGISTER_INDIRECT_REGISTER 1
+
+#define GEN8_CHANNEL_X 0
+#define GEN8_CHANNEL_Y 1
+#define GEN8_CHANNEL_Z 2
+#define GEN8_CHANNEL_W 3
+
+#define GEN8_COMPRESSION_NONE 0
+#define GEN8_COMPRESSION_2NDHALF 1
+#define GEN8_COMPRESSION_COMPRESSED 2
+
+#define GEN8_CONDITIONAL_NONE 0
+#define GEN8_CONDITIONAL_Z 1
+#define GEN8_CONDITIONAL_NZ 2
+#define GEN8_CONDITIONAL_EQ 1 /* Z */
+#define GEN8_CONDITIONAL_NEQ 2 /* NZ */
+#define GEN8_CONDITIONAL_G 3
+#define GEN8_CONDITIONAL_GE 4
+#define GEN8_CONDITIONAL_L 5
+#define GEN8_CONDITIONAL_LE 6
+#define GEN8_CONDITIONAL_C 7
+#define GEN8_CONDITIONAL_O 8
+
+#define GEN8_DEBUG_NONE 0
+#define GEN8_DEBUG_BREAKPOINT 1
+
+#define GEN8_DEPENDENCY_NORMAL 0
+#define GEN8_DEPENDENCY_NOTCLEARED 1
+#define GEN8_DEPENDENCY_NOTCHECKED 2
+#define GEN8_DEPENDENCY_DISABLE 3
+
+#define GEN8_EXECUTE_1 0
+#define GEN8_EXECUTE_2 1
+#define GEN8_EXECUTE_4 2
+#define GEN8_EXECUTE_8 3
+#define GEN8_EXECUTE_16 4
+#define GEN8_EXECUTE_32 5
+
+#define GEN8_HORIZONTAL_STRIDE_0 0
+#define GEN8_HORIZONTAL_STRIDE_1 1
+#define GEN8_HORIZONTAL_STRIDE_2 2
+#define GEN8_HORIZONTAL_STRIDE_4 3
+
+#define GEN8_INSTRUCTION_NORMAL 0
+#define GEN8_INSTRUCTION_SATURATE 1
+
+#define GEN8_OPCODE_MOV 1
+#define GEN8_OPCODE_SEL 2
+#define GEN8_OPCODE_NOT 4
+#define GEN8_OPCODE_AND 5
+#define GEN8_OPCODE_OR 6
+#define GEN8_OPCODE_XOR 7
+#define GEN8_OPCODE_SHR 8
+#define GEN8_OPCODE_SHL 9
+#define GEN8_OPCODE_RSR 10
+#define GEN8_OPCODE_RSL 11
+#define GEN8_OPCODE_ASR 12
+#define GEN8_OPCODE_CMP 16
+#define GEN8_OPCODE_JMPI 32
+#define GEN8_OPCODE_IF 34
+#define GEN8_OPCODE_IFF 35
+#define GEN8_OPCODE_ELSE 36
+#define GEN8_OPCODE_ENDIF 37
+#define GEN8_OPCODE_DO 38
+#define GEN8_OPCODE_WHILE 39
+#define GEN8_OPCODE_BREAK 40
+#define GEN8_OPCODE_CONTINUE 41
+#define GEN8_OPCODE_HALT 42
+#define GEN8_OPCODE_MSAVE 44
+#define GEN8_OPCODE_MRESTORE 45
+#define GEN8_OPCODE_PUSH 46
+#define GEN8_OPCODE_POP 47
+#define GEN8_OPCODE_WAIT 48
+#define GEN8_OPCODE_SEND 49
+#define GEN8_OPCODE_ADD 64
+#define GEN8_OPCODE_MUL 65
+#define GEN8_OPCODE_AVG 66
+#define GEN8_OPCODE_FRC 67
+#define GEN8_OPCODE_RNDU 68
+#define GEN8_OPCODE_RNDD 69
+#define GEN8_OPCODE_RNDE 70
+#define GEN8_OPCODE_RNDZ 71
+#define GEN8_OPCODE_MAC 72
+#define GEN8_OPCODE_MACH 73
+#define GEN8_OPCODE_LZD 74
+#define GEN8_OPCODE_SAD2 80
+#define GEN8_OPCODE_SADA2 81
+#define GEN8_OPCODE_DP4 84
+#define GEN8_OPCODE_DPH 85
+#define GEN8_OPCODE_DP3 86
+#define GEN8_OPCODE_DP2 87
+#define GEN8_OPCODE_DPA2 88
+#define GEN8_OPCODE_LINE 89
+#define GEN8_OPCODE_NOP 126
+
+#define GEN8_PREDICATE_NONE 0
+#define GEN8_PREDICATE_NORMAL 1
+#define GEN8_PREDICATE_ALIGN1_ANYV 2
+#define GEN8_PREDICATE_ALIGN1_ALLV 3
+#define GEN8_PREDICATE_ALIGN1_ANY2H 4
+#define GEN8_PREDICATE_ALIGN1_ALL2H 5
+#define GEN8_PREDICATE_ALIGN1_ANY4H 6
+#define GEN8_PREDICATE_ALIGN1_ALL4H 7
+#define GEN8_PREDICATE_ALIGN1_ANY8H 8
+#define GEN8_PREDICATE_ALIGN1_ALL8H 9
+#define GEN8_PREDICATE_ALIGN1_ANY16H 10
+#define GEN8_PREDICATE_ALIGN1_ALL16H 11
+#define GEN8_PREDICATE_ALIGN16_REPLICATE_X 2
+#define GEN8_PREDICATE_ALIGN16_REPLICATE_Y 3
+#define GEN8_PREDICATE_ALIGN16_REPLICATE_Z 4
+#define GEN8_PREDICATE_ALIGN16_REPLICATE_W 5
+#define GEN8_PREDICATE_ALIGN16_ANY4H 6
+#define GEN8_PREDICATE_ALIGN16_ALL4H 7
+
+#define GEN8_ARCHITECTURE_REGISTER_FILE 0
+#define GEN8_GENERAL_REGISTER_FILE 1
+#define GEN8_MESSAGE_REGISTER_FILE 2
+#define GEN8_IMMEDIATE_VALUE 3
+
+#define GEN8_REGISTER_TYPE_UD 0
+#define GEN8_REGISTER_TYPE_D 1
+#define GEN8_REGISTER_TYPE_UW 2
+#define GEN8_REGISTER_TYPE_W 3
+#define GEN8_REGISTER_TYPE_UB 4
+#define GEN8_REGISTER_TYPE_B 5
+#define GEN8_REGISTER_TYPE_VF 5 /* packed float vector, immediates only? */
+#define GEN8_REGISTER_TYPE_HF 6
+#define GEN8_REGISTER_TYPE_V 6 /* packed int vector, immediates only, uword dest only */
+#define GEN8_REGISTER_TYPE_F 7
+
+#define GEN8_ARF_NULL 0x00
+#define GEN8_ARF_ADDRESS 0x10
+#define GEN8_ARF_ACCUMULATOR 0x20
+#define GEN8_ARF_FLAG 0x30
+#define GEN8_ARF_MASK 0x40
+#define GEN8_ARF_MASK_STACK 0x50
+#define GEN8_ARF_MASK_STACK_DEPTH 0x60
+#define GEN8_ARF_STATE 0x70
+#define GEN8_ARF_CONTROL 0x80
+#define GEN8_ARF_NOTIFICATION_COUNT 0x90
+#define GEN8_ARF_IP 0xA0
+
+#define GEN8_AMASK 0
+#define GEN8_IMASK 1
+#define GEN8_LMASK 2
+#define GEN8_CMASK 3
+
+#define GEN8_THREAD_NORMAL 0
+#define GEN8_THREAD_ATOMIC 1
+#define GEN8_THREAD_SWITCH 2
+
+#define GEN8_VERTICAL_STRIDE_0 0
+#define GEN8_VERTICAL_STRIDE_1 1
+#define GEN8_VERTICAL_STRIDE_2 2
+#define GEN8_VERTICAL_STRIDE_4 3
+#define GEN8_VERTICAL_STRIDE_8 4
+#define GEN8_VERTICAL_STRIDE_16 5
+#define GEN8_VERTICAL_STRIDE_32 6
+#define GEN8_VERTICAL_STRIDE_64 7
+#define GEN8_VERTICAL_STRIDE_128 8
+#define GEN8_VERTICAL_STRIDE_256 9
+#define GEN8_VERTICAL_STRIDE_ONE_DIMENSIONAL 0xF
+
+#define GEN8_WIDTH_1 0
+#define GEN8_WIDTH_2 1
+#define GEN8_WIDTH_4 2
+#define GEN8_WIDTH_8 3
+#define GEN8_WIDTH_16 4
+
+#define GEN8_STATELESS_BUFFER_BOUNDARY_1K 0
+#define GEN8_STATELESS_BUFFER_BOUNDARY_2K 1
+#define GEN8_STATELESS_BUFFER_BOUNDARY_4K 2
+#define GEN8_STATELESS_BUFFER_BOUNDARY_8K 3
+#define GEN8_STATELESS_BUFFER_BOUNDARY_16K 4
+#define GEN8_STATELESS_BUFFER_BOUNDARY_32K 5
+#define GEN8_STATELESS_BUFFER_BOUNDARY_64K 6
+#define GEN8_STATELESS_BUFFER_BOUNDARY_128K 7
+#define GEN8_STATELESS_BUFFER_BOUNDARY_256K 8
+#define GEN8_STATELESS_BUFFER_BOUNDARY_512K 9
+#define GEN8_STATELESS_BUFFER_BOUNDARY_1M 10
+#define GEN8_STATELESS_BUFFER_BOUNDARY_2M 11
+
+#define GEN8_POLYGON_FACING_FRONT 0
+#define GEN8_POLYGON_FACING_BACK 1
+
+#define GEN8_MESSAGE_TARGET_NULL 0
+#define GEN8_MESSAGE_TARGET_MATH 1
+#define GEN8_MESSAGE_TARGET_SAMPLER 2
+#define GEN8_MESSAGE_TARGET_GATEWAY 3
+#define GEN8_MESSAGE_TARGET_DATAPORT_READ 4
+#define GEN8_MESSAGE_TARGET_DATAPORT_WRITE 5
+#define GEN8_MESSAGE_TARGET_URB 6
+#define GEN8_MESSAGE_TARGET_THREAD_SPAWNER 7
+
+#define GEN8_SAMPLER_RETURN_FORMAT_FLOAT32 0
+#define GEN8_SAMPLER_RETURN_FORMAT_UINT32 2
+#define GEN8_SAMPLER_RETURN_FORMAT_SINT32 3
+
+#define GEN8_SAMPLER_MESSAGE_SIMD8_SAMPLE 0
+#define GEN8_SAMPLER_MESSAGE_SIMD16_SAMPLE 0
+#define GEN8_SAMPLER_MESSAGE_SIMD16_SAMPLE_BIAS 0
+#define GEN8_SAMPLER_MESSAGE_SIMD8_KILLPIX 1
+#define GEN8_SAMPLER_MESSAGE_SIMD4X2_SAMPLE_LOD 1
+#define GEN8_SAMPLER_MESSAGE_SIMD16_SAMPLE_LOD 1
+#define GEN8_SAMPLER_MESSAGE_SIMD4X2_SAMPLE_GRADIENTS 2
+#define GEN8_SAMPLER_MESSAGE_SIMD8_SAMPLE_GRADIENTS 2
+#define GEN8_SAMPLER_MESSAGE_SIMD4X2_SAMPLE_COMPARE 0
+#define GEN8_SAMPLER_MESSAGE_SIMD16_SAMPLE_COMPARE 2
+#define GEN8_SAMPLER_MESSAGE_SIMD4X2_RESINFO 2
+#define GEN8_SAMPLER_MESSAGE_SIMD8_RESINFO 2
+#define GEN8_SAMPLER_MESSAGE_SIMD16_RESINFO 2
+#define GEN8_SAMPLER_MESSAGE_SIMD4X2_LD 3
+#define GEN8_SAMPLER_MESSAGE_SIMD8_LD 3
+#define GEN8_SAMPLER_MESSAGE_SIMD16_LD 3
+
+#define GEN8_DATAPORT_OWORD_BLOCK_1_OWORDLOW 0
+#define GEN8_DATAPORT_OWORD_BLOCK_1_OWORDHIGH 1
+#define GEN8_DATAPORT_OWORD_BLOCK_2_OWORDS 2
+#define GEN8_DATAPORT_OWORD_BLOCK_4_OWORDS 3
+#define GEN8_DATAPORT_OWORD_BLOCK_8_OWORDS 4
+
+#define GEN8_DATAPORT_OWORD_DUAL_BLOCK_1OWORD 0
+#define GEN8_DATAPORT_OWORD_DUAL_BLOCK_4OWORDS 2
+
+#define GEN8_DATAPORT_DWORD_SCATTERED_BLOCK_8DWORDS 2
+#define GEN8_DATAPORT_DWORD_SCATTERED_BLOCK_16DWORDS 3
+
+#define GEN8_DATAPORT_READ_MESSAGE_OWORD_BLOCK_READ 0
+#define GEN8_DATAPORT_READ_MESSAGE_OWORD_DUAL_BLOCK_READ 1
+#define GEN8_DATAPORT_READ_MESSAGE_DWORD_BLOCK_READ 2
+#define GEN8_DATAPORT_READ_MESSAGE_DWORD_SCATTERED_READ 3
+
+#define GEN8_DATAPORT_READ_TARGET_DATA_CACHE 0
+#define GEN8_DATAPORT_READ_TARGET_RENDER_CACHE 1
+#define GEN8_DATAPORT_READ_TARGET_SAMPLER_CACHE 2
+
+#define GEN8_DATAPORT_RENDER_TARGET_WRITE_SIMD16_SINGLE_SOURCE 0
+#define GEN8_DATAPORT_RENDER_TARGET_WRITE_SIMD16_SINGLE_SOURCE_REPLICATED 1
+#define GEN8_DATAPORT_RENDER_TARGET_WRITE_SIMD8_DUAL_SOURCE_SUBSPAN01 2
+#define GEN8_DATAPORT_RENDER_TARGET_WRITE_SIMD8_DUAL_SOURCE_SUBSPAN23 3
+#define GEN8_DATAPORT_RENDER_TARGET_WRITE_SIMD8_SINGLE_SOURCE_SUBSPAN01 4
+
+#define GEN8_DATAPORT_WRITE_MESSAGE_OWORD_BLOCK_WRITE 0
+#define GEN8_DATAPORT_WRITE_MESSAGE_OWORD_DUAL_BLOCK_WRITE 1
+#define GEN8_DATAPORT_WRITE_MESSAGE_DWORD_BLOCK_WRITE 2
+#define GEN8_DATAPORT_WRITE_MESSAGE_DWORD_SCATTERED_WRITE 3
+#define GEN8_DATAPORT_WRITE_MESSAGE_RENDER_TARGET_WRITE 4
+#define GEN8_DATAPORT_WRITE_MESSAGE_STREAMED_VERTEX_BUFFER_WRITE 5
+#define GEN8_DATAPORT_WRITE_MESSAGE_FLUSH_RENDER_CACHE 7
+
+#define GEN8_MATH_FUNCTION_INV 1
+#define GEN8_MATH_FUNCTION_LOG 2
+#define GEN8_MATH_FUNCTION_EXP 3
+#define GEN8_MATH_FUNCTION_SQRT 4
+#define GEN8_MATH_FUNCTION_RSQ 5
+#define GEN8_MATH_FUNCTION_SIN 6 /* was 7 */
+#define GEN8_MATH_FUNCTION_COS 7 /* was 8 */
+#define GEN8_MATH_FUNCTION_SINCOS 8 /* was 6 */
+#define GEN8_MATH_FUNCTION_TAN 9
+#define GEN8_MATH_FUNCTION_POW 10
+#define GEN8_MATH_FUNCTION_INT_DIV_QUOTIENT_AND_REMAINDER 11
+#define GEN8_MATH_FUNCTION_INT_DIV_QUOTIENT 12
+#define GEN8_MATH_FUNCTION_INT_DIV_REMAINDER 13
+
+#define GEN8_MATH_INTEGER_UNSIGNED 0
+#define GEN8_MATH_INTEGER_SIGNED 1
+
+#define GEN8_MATH_PRECISION_FULL 0
+#define GEN8_MATH_PRECISION_PARTIAL 1
+
+#define GEN8_MATH_SATURATE_NONE 0
+#define GEN8_MATH_SATURATE_SATURATE 1
+
+#define GEN8_MATH_DATA_VECTOR 0
+#define GEN8_MATH_DATA_SCALAR 1
+
+#define GEN8_URB_OPCODE_WRITE 0
+
+#define GEN8_URB_SWIZZLE_NONE 0
+#define GEN8_URB_SWIZZLE_INTERLEAVE 1
+#define GEN8_URB_SWIZZLE_TRANSPOSE 2
+
+#define GEN8_SCRATCH_SPACE_SIZE_1K 0
+#define GEN8_SCRATCH_SPACE_SIZE_2K 1
+#define GEN8_SCRATCH_SPACE_SIZE_4K 2
+#define GEN8_SCRATCH_SPACE_SIZE_8K 3
+#define GEN8_SCRATCH_SPACE_SIZE_16K 4
+#define GEN8_SCRATCH_SPACE_SIZE_32K 5
+#define GEN8_SCRATCH_SPACE_SIZE_64K 6
+#define GEN8_SCRATCH_SPACE_SIZE_128K 7
+#define GEN8_SCRATCH_SPACE_SIZE_256K 8
+#define GEN8_SCRATCH_SPACE_SIZE_512K 9
+#define GEN8_SCRATCH_SPACE_SIZE_1M 10
+#define GEN8_SCRATCH_SPACE_SIZE_2M 11
+
+struct gen8_blend_state {
+ struct {
+ /* 00 */ uint32_t pad:19;
+ /* 19 */ uint32_t y_dither_offset:2;
+ /* 21 */ uint32_t x_dither_offset:2;
+ /* 23 */ uint32_t color_dither_enable:1;
+ /* 24 */ uint32_t alpha_test_function:3;
+ /* 27 */ uint32_t alpha_test:1;
+ /* 28 */ uint32_t alpha_to_coverage_dither:1;
+ /* 29 */ uint32_t alpha_to_one:1;
+ /* 30 */ uint32_t ia_blend:1;
+ /* 31 */ uint32_t alpha_to_coverage:1;
+ } common;
+
+ struct {
+ /* 00 */ uint32_t write_disable_blue:1;
+ /* 01 */ uint32_t write_disable_green:1;
+ /* 02 */ uint32_t write_disable_red:1;
+ /* 03 */ uint32_t write_disable_alpha:1;
+ /* 04 */ uint32_t pad0:1;
+ /* 05 */ uint32_t alpha_blend_function:3;
+ /* 08 */ uint32_t dest_alpha_blend_factor:5;
+ /* 13 */ uint32_t source_alpha_blend_factor:5;
+ /* 18 */ uint32_t color_blend_function:3;
+ /* 21 */ uint32_t dest_blend_factor:5;
+ /* 26 */ uint32_t source_blend_factor:5;
+ /* 31 */ uint32_t color_blend:1;
+ /* 32 */ uint32_t post_blend_clamp:1;
+ /* 33 */ uint32_t pre_blend_clamp:1;
+ /* 34 */ uint32_t color_clamp_range:2;
+ /* 36 */ uint32_t pre_blend_source_only_clamp:1;
+ /* 37 */ uint32_t pad1:22;
+ /* 59 */ uint32_t logic_op_function:4;
+ /* 63 */ uint32_t logic_op:1;
+ } rt;
+};
+
+struct gen8_color_calc_state {
+ struct {
+ /* 00 */ uint32_t alpha_test_format:1;
+ /* 01 */ uint32_t pad0:14;
+ /* 15 */ uint32_t round_disable:1;
+ /* 16 */ uint32_t bf_stencil_ref:8;
+ /* 24 */ uint32_t stencil_ref:8;
+ } cc0;
+
+ union {
+ float alpha_ref_f;
+ struct {
+ uint32_t ui:8;
+ uint32_t pad0:24;
+ } alpha_ref_fi;
+ } cc1;
+
+ float constant_r;
+ float constant_g;
+ float constant_b;
+ float constant_a;
+};
+
+struct gen8_sampler_state {
+ struct {
+ /* 00 */ unsigned int aniso_algorithm:1;
+ /* 01 */ unsigned int lod_bias:13;
+ /* 14 */ unsigned int min_filter:3;
+ /* 17 */ unsigned int mag_filter:3;
+ /* 20 */ unsigned int mip_filter:2;
+ /* 22 */ unsigned int base_level:5;
+ /* 27 */ unsigned int lod_preclamp:2;
+ /* 29 */ unsigned int default_color_mode:1;
+ /* 30 */ unsigned int flexible_filter_clamp:1;
+ /* 31 */ unsigned int disable:1;
+ } ss0;
+
+ struct {
+ /* 00 */ unsigned int cube_control_mode:1;
+ /* 01 */ unsigned int shadow_function:3;
+ /* 04 */ unsigned int chroma_key_mode:1;
+ /* 05 */ unsigned int chroma_key_index:2;
+ /* 07 */ unsigned int chroma_key_enable:1;
+ /* 08 */ unsigned int max_lod:12;
+ /* 20 */ unsigned int min_lod:12;
+ } ss1;
+
+ struct {
+ unsigned int pad:6;
+ unsigned int default_color_pointer:26;
+ } ss2;
+
+ struct {
+ /* 00 */ unsigned int r_wrap_mode:3;
+ /* 03 */ unsigned int t_wrap_mode:3;
+ /* 06 */ unsigned int s_wrap_mode:3;
+ /* 09 */ unsigned int pad:1;
+ /* 10 */ unsigned int non_normalized_coord:1;
+ /* 11 */ unsigned int trilinear_quality:2;
+ /* 13 */ unsigned int address_round:6;
+ /* 19 */ unsigned int max_aniso:3;
+ /* 22 */ unsigned int pad0:2;
+ /* 24 */ unsigned int non_separable_filter:8;
+ } ss3;
+};
+
+/* Surface state DW0 */
+#define SURFACE_RC_READ_WRITE (1 << 8)
+#define SURFACE_TILED (1 << 13)
+#define SURFACE_TILED_Y (1 << 12)
+#define SURFACE_FORMAT_SHIFT 18
+#define SURFACE_VALIGN_1 (0 << 16) /* reserved! */
+#define SURFACE_VALIGN_4 (1 << 16)
+#define SURFACE_VALIGN_8 (2 << 16)
+#define SURFACE_VALIGN_16 (3 << 16)
+#define SURFACE_HALIGN_1 (0 << 14) /* reserved! */
+#define SURFACE_HALIGN_4 (1 << 14)
+#define SURFACE_HALIGN_8 (2 << 14)
+#define SURFACE_HALIGN_16 (3 << 14)
+#define SURFACE_TYPE_SHIFT 29
+
+/* Surface state DW2 */
+#define SURFACE_HEIGHT_SHIFT 16
+#define SURFACE_WIDTH_SHIFT 0
+
+/* Surface state DW3 */
+#define SURFACE_DEPTH_SHIFT 21
+#define SURFACE_PITCH_SHIFT 0
+
+#define SWIZZLE_ZERO 0
+#define SWIZZLE_ONE 1
+#define SWIZZLE_RED 4
+#define SWIZZLE_GREEN 5
+#define SWIZZLE_BLUE 6
+#define SWIZZLE_ALPHA 7
+#define __SURFACE_SWIZZLE(r,g,b,a) \
+ ((a) << 16 | (b) << 19 | (g) << 22 | (r) << 25)
+#define SURFACE_SWIZZLE(r,g,b,a) \
+ __SURFACE_SWIZZLE(SWIZZLE_##r, SWIZZLE_##g, SWIZZLE_##b, SWIZZLE_##a)
+
+typedef enum {
+ SAMPLER_FILTER_NEAREST = 0,
+ SAMPLER_FILTER_BILINEAR,
+ FILTER_COUNT
+} sampler_filter_t;
+
+typedef enum {
+ SAMPLER_EXTEND_NONE = 0,
+ SAMPLER_EXTEND_REPEAT,
+ SAMPLER_EXTEND_PAD,
+ SAMPLER_EXTEND_REFLECT,
+ EXTEND_COUNT
+} sampler_extend_t;
+
+#endif
diff --git a/src/sna/gen8_vertex.c b/src/sna/gen8_vertex.c
new file mode 100644
index 0000000..dcafcd1
--- /dev/null
+++ b/src/sna/gen8_vertex.c
@@ -0,0 +1,297 @@
+/*
+ * Copyright © 2012 Intel Corporation
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+ * SOFTWARE.
+ *
+ * Authors:
+ * Chris Wilson <chris at chris-wilson.co.uk>
+ *
+ */
+
+#ifdef HAVE_CONFIG_H
+#include "config.h"
+#endif
+
+#include "sna.h"
+#include "sna_render.h"
+#include "sna_render_inline.h"
+#include "gen8_vertex.h"
+
+void gen8_vertex_align(struct sna *sna, const struct sna_composite_op *op)
+{
+ int vertex_index;
+
+ assert(op->floats_per_rect == 3*op->floats_per_vertex);
+
+ vertex_index = (sna->render.vertex_used + op->floats_per_vertex - 1) / op->floats_per_vertex;
+ if ((int)sna->render.vertex_size - vertex_index * op->floats_per_vertex < 2*op->floats_per_rect) {
+ DBG(("%s: flushing vertex buffer: new index=%d, max=%d\n",
+ __FUNCTION__, vertex_index, sna->render.vertex_size / op->floats_per_vertex));
+ if (gen8_vertex_finish(sna) < op->floats_per_rect) {
+ kgem_submit(&sna->kgem);
+ _kgem_set_mode(&sna->kgem, KGEM_RENDER);
+ }
+
+ vertex_index = (sna->render.vertex_used + op->floats_per_vertex - 1) / op->floats_per_vertex;
+ assert(vertex_index * op->floats_per_vertex <= sna->render.vertex_size);
+ }
+
+ sna->render.vertex_index = vertex_index;
+ sna->render.vertex_used = vertex_index * op->floats_per_vertex;
+}
+
+void gen8_vertex_flush(struct sna *sna)
+{
+ DBG(("%s[%x] = %d\n", __FUNCTION__,
+ 4*sna->render.vertex_offset,
+ sna->render.vertex_index - sna->render.vertex_start));
+
+ assert(sna->render.vertex_offset);
+ assert(sna->render.vertex_offset <= sna->kgem.nbatch);
+ assert(sna->render.vertex_index > sna->render.vertex_start);
+ assert(sna->render.vertex_used <= sna->render.vertex_size);
+
+ sna->kgem.batch[sna->render.vertex_offset] =
+ sna->render.vertex_index - sna->render.vertex_start;
+ sna->render.vertex_offset = 0;
+}
+
+int gen8_vertex_finish(struct sna *sna)
+{
+ struct kgem_bo *bo;
+ unsigned int i;
+ unsigned hint, size;
+
+ DBG(("%s: used=%d / %d\n", __FUNCTION__,
+ sna->render.vertex_used, sna->render.vertex_size));
+ assert(sna->render.vertex_offset == 0);
+ assert(sna->render.vertex_used);
+ assert(sna->render.vertex_used <= sna->render.vertex_size);
+ assert(sna->render.nvertex_reloc);
+
+ sna_vertex_wait__locked(&sna->render);
+
+ /* Note: we only need dword alignment (currently) */
+
+ hint = CREATE_GTT_MAP;
+
+ bo = sna->render.vbo;
+ if (bo) {
+ for (i = 0; i < sna->render.nvertex_reloc; i++) {
+ DBG(("%s: reloc[%d] = %d\n", __FUNCTION__,
+ i, sna->render.vertex_reloc[i]));
+
+ *(uint64_t *)(sna->kgem.batch+sna->render.vertex_reloc[i]) =
+ kgem_add_reloc64(&sna->kgem,
+ sna->render.vertex_reloc[i], bo,
+ I915_GEM_DOMAIN_VERTEX << 16,
+ 0);
+ }
+
+ assert(!sna->render.active);
+ sna->render.nvertex_reloc = 0;
+ sna->render.vertex_used = 0;
+ sna->render.vertex_index = 0;
+ sna->render.vbo = NULL;
+ sna->render.vb_id = 0;
+
+ kgem_bo_destroy(&sna->kgem, bo);
+ hint |= CREATE_CACHED | CREATE_NO_THROTTLE;
+ } else {
+ if (kgem_is_idle(&sna->kgem)) {
+ sna->render.vertices = sna->render.vertex_data;
+ sna->render.vertex_size = ARRAY_SIZE(sna->render.vertex_data);
+ return 0;
+ }
+ }
+
+ size = 256*1024;
+ assert(!sna->render.active);
+ sna->render.vertices = NULL;
+ sna->render.vbo = kgem_create_linear(&sna->kgem, size, hint);
+ while (sna->render.vbo == NULL && size > 16*1024) {
+ size /= 2;
+ sna->render.vbo = kgem_create_linear(&sna->kgem, size, hint);
+ }
+ if (sna->render.vbo == NULL)
+ sna->render.vbo = kgem_create_linear(&sna->kgem,
+ 256*1024, CREATE_GTT_MAP);
+ if (sna->render.vbo)
+ sna->render.vertices = kgem_bo_map(&sna->kgem, sna->render.vbo);
+ if (sna->render.vertices == NULL) {
+ if (sna->render.vbo) {
+ kgem_bo_destroy(&sna->kgem, sna->render.vbo);
+ sna->render.vbo = NULL;
+ }
+ sna->render.vertices = sna->render.vertex_data;
+ sna->render.vertex_size = ARRAY_SIZE(sna->render.vertex_data);
+ return 0;
+ }
+
+ if (sna->render.vertex_used) {
+ DBG(("%s: copying initial buffer x %d to handle=%d\n",
+ __FUNCTION__,
+ sna->render.vertex_used,
+ sna->render.vbo->handle));
+ assert(sizeof(float)*sna->render.vertex_used <=
+ __kgem_bo_size(sna->render.vbo));
+ memcpy(sna->render.vertices,
+ sna->render.vertex_data,
+ sizeof(float)*sna->render.vertex_used);
+ }
+
+ size = __kgem_bo_size(sna->render.vbo)/4;
+ if (size >= UINT16_MAX)
+ size = UINT16_MAX - 1;
+
+ DBG(("%s: create vbo handle=%d, size=%d\n",
+ __FUNCTION__, sna->render.vbo->handle, size));
+
+ sna->render.vertex_size = size;
+ return sna->render.vertex_size - sna->render.vertex_used;
+}
+
+void gen8_vertex_close(struct sna *sna)
+{
+ struct kgem_bo *bo, *free_bo = NULL;
+ unsigned int i, delta = 0;
+
+ assert(sna->render.vertex_offset == 0);
+ if (!sna->render.vb_id)
+ return;
+
+ DBG(("%s: used=%d, vbo active? %d, vb=%x, nreloc=%d\n",
+ __FUNCTION__, sna->render.vertex_used, sna->render.vbo ? sna->render.vbo->handle : 0,
+ sna->render.vb_id, sna->render.nvertex_reloc));
+
+ assert(!sna->render.active);
+
+ bo = sna->render.vbo;
+ if (bo) {
+ if (sna->render.vertex_size - sna->render.vertex_used < 64) {
+ DBG(("%s: discarding vbo (full), handle=%d\n", __FUNCTION__, sna->render.vbo->handle));
+ sna->render.vbo = NULL;
+ sna->render.vertices = sna->render.vertex_data;
+ sna->render.vertex_size = ARRAY_SIZE(sna->render.vertex_data);
+ free_bo = bo;
+ } else if (!sna->kgem.has_llc && sna->render.vertices == MAP(bo->map__cpu)) {
+ DBG(("%s: converting CPU map to GTT\n", __FUNCTION__));
+ sna->render.vertices =
+ kgem_bo_map__gtt(&sna->kgem, sna->render.vbo);
+ if (sna->render.vertices == NULL) {
+ sna->render.vbo = NULL;
+ sna->render.vertices = sna->render.vertex_data;
+ sna->render.vertex_size = ARRAY_SIZE(sna->render.vertex_data);
+ free_bo = bo;
+ }
+
+ }
+ } else {
+ int size;
+
+ size = sna->kgem.nbatch;
+ size += sna->kgem.batch_size - sna->kgem.surface;
+ size += sna->render.vertex_used;
+
+ if (size <= 1024) {
+ DBG(("%s: copy to batch: %d @ %d\n", __FUNCTION__,
+ sna->render.vertex_used, sna->kgem.nbatch));
+ assert(sna->kgem.nbatch + sna->render.vertex_used <= sna->kgem.surface);
+ memcpy(sna->kgem.batch + sna->kgem.nbatch,
+ sna->render.vertex_data,
+ sna->render.vertex_used * 4);
+ delta = sna->kgem.nbatch * 4;
+ bo = NULL;
+ sna->kgem.nbatch += sna->render.vertex_used;
+ } else {
+ size = 256 * 1024;
+ do {
+ bo = kgem_create_linear(&sna->kgem, size,
+ CREATE_GTT_MAP | CREATE_NO_RETIRE | CREATE_NO_THROTTLE | CREATE_CACHED);
+ } while (bo == NULL && (size>>=1) > sizeof(float)*sna->render.vertex_used);
+
+ sna->render.vertices = NULL;
+ if (bo)
+ sna->render.vertices = kgem_bo_map(&sna->kgem, bo);
+ if (sna->render.vertices != NULL) {
+ DBG(("%s: new vbo: %d / %d\n", __FUNCTION__,
+ sna->render.vertex_used, __kgem_bo_size(bo)/4));
+
+ assert(sizeof(float)*sna->render.vertex_used <= __kgem_bo_size(bo));
+ memcpy(sna->render.vertices,
+ sna->render.vertex_data,
+ sizeof(float)*sna->render.vertex_used);
+
+ size = __kgem_bo_size(bo)/4;
+ if (size >= UINT16_MAX)
+ size = UINT16_MAX - 1;
+
+ sna->render.vbo = bo;
+ sna->render.vertex_size = size;
+ } else {
+ DBG(("%s: tmp vbo: %d\n", __FUNCTION__,
+ sna->render.vertex_used));
+
+ if (bo)
+ kgem_bo_destroy(&sna->kgem, bo);
+
+ bo = kgem_create_linear(&sna->kgem,
+ 4*sna->render.vertex_used,
+ CREATE_NO_THROTTLE);
+ if (bo && !kgem_bo_write(&sna->kgem, bo,
+ sna->render.vertex_data,
+ 4*sna->render.vertex_used)) {
+ kgem_bo_destroy(&sna->kgem, bo);
+ bo = NULL;
+ }
+
+ assert(sna->render.vbo == NULL);
+ sna->render.vertices = sna->render.vertex_data;
+ sna->render.vertex_size = ARRAY_SIZE(sna->render.vertex_data);
+ free_bo = bo;
+ }
+ }
+ }
+
+ assert(sna->render.nvertex_reloc);
+ for (i = 0; i < sna->render.nvertex_reloc; i++) {
+ DBG(("%s: reloc[%d] = %d\n", __FUNCTION__,
+ i, sna->render.vertex_reloc[i]));
+
+ *(uint64_t *)(sna->kgem.batch+sna->render.vertex_reloc[i]) =
+ kgem_add_reloc64(&sna->kgem,
+ sna->render.vertex_reloc[i], bo,
+ I915_GEM_DOMAIN_VERTEX << 16,
+ delta);
+ }
+ sna->render.nvertex_reloc = 0;
+ sna->render.vb_id = 0;
+
+ if (sna->render.vbo == NULL) {
+ assert(!sna->render.active);
+ sna->render.vertex_used = 0;
+ sna->render.vertex_index = 0;
+ assert(sna->render.vertices == sna->render.vertex_data);
+ assert(sna->render.vertex_size == ARRAY_SIZE(sna->render.vertex_data));
+ }
+
+ if (free_bo)
+ kgem_bo_destroy(&sna->kgem, free_bo);
+}
diff --git a/src/sna/gen8_vertex.h b/src/sna/gen8_vertex.h
new file mode 100644
index 0000000..2ff559d
--- /dev/null
+++ b/src/sna/gen8_vertex.h
@@ -0,0 +1,14 @@
+#ifndef GEN8_VERTEX_H
+#define GEN8_VERTEX_H
+
+#include "compiler.h"
+
+#include "sna.h"
+#include "sna_render.h"
+
+void gen8_vertex_align(struct sna *sna, const struct sna_composite_op *op);
+void gen8_vertex_flush(struct sna *sna);
+int gen8_vertex_finish(struct sna *sna);
+void gen8_vertex_close(struct sna *sna);
+
+#endif /* GEN8_VERTEX_H */
diff --git a/src/sna/kgem.c b/src/sna/kgem.c
index 777326e..187e4ff 100644
--- a/src/sna/kgem.c
+++ b/src/sna/kgem.c
@@ -1244,7 +1244,7 @@ void kgem_init(struct kgem *kgem, int fd, struct pci_device *dev, unsigned gen)
if (gen == 022)
/* 865g cannot handle a batch spanning multiple pages */
kgem->batch_size = PAGE_SIZE / sizeof(uint32_t);
- if ((gen >> 3) == 7)
+ if (gen >= 070)
kgem->batch_size = 16*1024;
if (!kgem->has_relaxed_delta && kgem->batch_size > 4*1024)
kgem->batch_size = 4*1024;
diff --git a/src/sna/sna.h b/src/sna/sna.h
index 7bd3aa4..0acc9a2 100644
--- a/src/sna/sna.h
+++ b/src/sna/sna.h
@@ -316,6 +316,7 @@ struct sna {
struct gen5_render_state gen5;
struct gen6_render_state gen6;
struct gen7_render_state gen7;
+ struct gen8_render_state gen8;
} render_state;
bool dri_available;
diff --git a/src/sna/sna_accel.c b/src/sna/sna_accel.c
index f7da098..5df49b3 100644
--- a/src/sna/sna_accel.c
+++ b/src/sna/sna_accel.c
@@ -16813,8 +16813,10 @@ bool sna_accel_init(ScreenPtr screen, struct sna *sna)
if (sna_option_accel_none(sna)) {
backend = "disabled";
sna->kgem.wedged = true;
- } else if (sna_option_accel_blt(sna) || sna->info->gen >= 0100)
+ } else if (sna_option_accel_blt(sna) || sna->info->gen >= 0110)
(void)backend;
+ else if (sna->info->gen >= 0100)
+ backend = gen8_render_init(sna, backend);
else if (sna->info->gen >= 070)
backend = gen7_render_init(sna, backend);
else if (sna->info->gen >= 060)
diff --git a/src/sna/sna_render.h b/src/sna/sna_render.h
index d64d652..0368556 100644
--- a/src/sna/sna_render.h
+++ b/src/sna/sna_render.h
@@ -144,6 +144,10 @@ struct sna_composite_op {
struct {
uint32_t flags;
} gen7;
+
+ struct {
+ uint32_t flags;
+ } gen8;
} u;
void *priv;
@@ -503,6 +507,57 @@ struct gen7_render_state {
bool emit_flush;
};
+
+enum {
+ GEN8_WM_KERNEL_NOMASK = 0,
+ GEN8_WM_KERNEL_NOMASK_P,
+
+ GEN8_WM_KERNEL_MASK,
+ GEN8_WM_KERNEL_MASK_P,
+
+ GEN8_WM_KERNEL_MASKCA,
+ GEN8_WM_KERNEL_MASKCA_P,
+
+ GEN8_WM_KERNEL_MASKSA,
+ GEN8_WM_KERNEL_MASKSA_P,
+
+ GEN8_WM_KERNEL_OPACITY,
+ GEN8_WM_KERNEL_OPACITY_P,
+
+ GEN8_WM_KERNEL_VIDEO_PLANAR,
+ GEN8_WM_KERNEL_VIDEO_PACKED,
+ GEN8_WM_KERNEL_COUNT
+};
+
+struct gen8_render_state {
+ unsigned gt;
+
+ struct kgem_bo *general_bo;
+
+ uint32_t vs_state;
+ uint32_t sf_state;
+ uint32_t sf_mask_state;
+ uint32_t wm_state;
+ uint32_t wm_kernel[GEN8_WM_KERNEL_COUNT][3];
+
+ uint32_t cc_blend;
+
+ uint32_t drawrect_offset;
+ uint32_t drawrect_limit;
+ uint32_t blend;
+ uint32_t samplers;
+ uint32_t kernel;
+
+ uint16_t num_sf_outputs;
+ uint16_t ve_id;
+ uint16_t last_primitive;
+ int16_t floats_per_vertex;
+ uint16_t surface_table;
+
+ bool needs_invariant;
+ bool emit_flush;
+};
+
struct sna_static_stream {
uint32_t size, used;
uint8_t *data;
@@ -557,6 +612,7 @@ const char *gen4_render_init(struct sna *sna, const char *backend);
const char *gen5_render_init(struct sna *sna, const char *backend);
const char *gen6_render_init(struct sna *sna, const char *backend);
const char *gen7_render_init(struct sna *sna, const char *backend);
+const char *gen8_render_init(struct sna *sna, const char *backend);
bool sna_tiling_composite(uint32_t op,
PicturePtr src,
diff --git a/src/sna/sna_render_inline.h b/src/sna/sna_render_inline.h
index a1b97be..3f74341 100644
--- a/src/sna/sna_render_inline.h
+++ b/src/sna/sna_render_inline.h
@@ -56,6 +56,14 @@ static force_inline void batch_emit(struct sna *sna, uint32_t dword)
sna->kgem.batch[sna->kgem.nbatch++] = dword;
}
+static force_inline void batch_emit64(struct sna *sna, uint64_t qword)
+{
+ assert(sna->kgem.mode != KGEM_NONE);
+ assert(sna->kgem.nbatch + 2 + KGEM_BATCH_RESERVED < sna->kgem.surface);
+ *(uint64_t *)(sna->kgem.batch+sna->kgem.nbatch) = qword;
+ sna->kgem.nbatch += 2;
+}
+
static force_inline void batch_emit_float(struct sna *sna, float f)
{
union {
commit 610af0c70e755062b36ba9756fbc4288518b7c35
Author: Chris Wilson <chris at chris-wilson.co.uk>
Date: Wed Nov 13 11:50:52 2013 +0000
Update i915_pciids.h
Pulling in changes from:
kernel commit 4d4dead67a4ab1d5de393f15ed5e4e2aa63d3bcf
Author: Ben Widawsky <benjamin.widawsky at intel.com>
Date: Sun Nov 3 16:47:33 2013 -0800
drm/i915/bdw: Add device IDs
Signed-off-by: Chris Wilson <chris at chris-wilson.co.uk>
diff --git a/src/i915_pciids.h b/src/i915_pciids.h
index 8a10f5c..940ece4 100644
--- a/src/i915_pciids.h
+++ b/src/i915_pciids.h
@@ -208,4 +208,29 @@
#define INTEL_VLV_D_IDS(info) \
INTEL_VGA_DEVICE(0x0155, info)
+#define _INTEL_BDW_M(gt, id, info) \
+ INTEL_VGA_DEVICE((((gt) - 1) << 4) | (id), info)
+#define _INTEL_BDW_D(gt, id, info) \
+ INTEL_VGA_DEVICE((((gt) - 1) << 4) | (id), info)
+
+#define _INTEL_BDW_M_IDS(gt, info) \
+ _INTEL_BDW_M(gt, 0x1602, info), /* ULT */ \
+ _INTEL_BDW_M(gt, 0x1606, info), /* ULT */ \
+ _INTEL_BDW_M(gt, 0x160B, info), /* Iris */ \
+ _INTEL_BDW_M(gt, 0x160E, info) /* ULX */
+
+#define _INTEL_BDW_D_IDS(gt, info) \
+ _INTEL_BDW_D(gt, 0x160A, info), /* Server */ \
+ _INTEL_BDW_D(gt, 0x160D, info) /* Workstation */
+
+#define INTEL_BDW_M_IDS(info) \
+ _INTEL_BDW_M_IDS(1, info), \
+ _INTEL_BDW_M_IDS(2, info), \
+ _INTEL_BDW_M_IDS(3, info)
+
+#define INTEL_BDW_D_IDS(info) \
+ _INTEL_BDW_D_IDS(1, info), \
+ _INTEL_BDW_D_IDS(2, info), \
+ _INTEL_BDW_D_IDS(3, info)
+
#endif /* _I915_PCIIDS_H */
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