xf86-video-intel: src/sna/sna_display.c

[Chris Wilson]

 src/sna/sna_display.c |   61 +++++++++++++++++++++++++++++++++++++++++---------
 1 file changed, 51 insertions(+), 10 deletions(-)

New commits:
commit bd22abee8f33b20ff6bc7297b0a9ae8708d18727
Author: Chris Wilson <chris at chris-wilson.co.uk>
Date:   Thu Nov 7 22:27:50 2013 +0000

    sna: Update Baytrail VSync logic
    
    My current best guess at the glaring hole in the spec that is
    synchronisation to vertical refresh.
    
    Note that this leaves VSync disabled for BYT for now as it is
    ineffective - but at least it now doesn't hang!
    
    Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=69869
    Signed-off-by: Chris Wilson <chris at chris-wilson.co.uk>

diff --git a/src/sna/sna_display.c b/src/sna/sna_display.c
index 53324c6..ec1367d 100644
--- a/src/sna/sna_display.c
+++ b/src/sna/sna_display.c
@@ -3710,14 +3710,58 @@ static bool sna_emit_wait_for_scanline_hsw(struct sna *sna,
 	return true;
 }
 
-static bool sna_emit_wait_for_scanline_ivb(struct sna *sna,
+static bool sna_emit_wait_for_scanline_vlv(struct sna *sna,
 					   xf86CrtcPtr crtc,
 					   int pipe, int y1, int y2,
 					   bool full_height)
 {
-	uint32_t *b;
+	uint32_t display_base = 0x180000;
 	uint32_t event;
-	uint32_t forcewake;
+	uint32_t *b;
+
+	return false; /* synchronisation? I've heard of that */
+
+	if (!sna->kgem.has_secure_batches)
+		return false;
+
+	assert(y1 >= 0);
+	assert(y2 > y1);
+	assert(sna->kgem.mode);
+
+	/* Always program one less than the desired value */
+	if (--y1 < 0)
+		y1 = crtc->bounds.y2;
+	y2--;
+
+	b = kgem_get_batch(&sna->kgem);
+	sna->kgem.nbatch += 4;
+
+	if (pipe == 0) {
+		if (full_height)
+			event = MI_WAIT_FOR_PIPEA_SVBLANK;
+		else
+			event = MI_WAIT_FOR_PIPEA_SCAN_LINE_WINDOW;
+	} else {
+		if (full_height)
+			event = MI_WAIT_FOR_PIPEB_SVBLANK;
+		else
+			event = MI_WAIT_FOR_PIPEB_SCAN_LINE_WINDOW;
+	}
+	b[0] = MI_LOAD_REGISTER_IMM | 1;
+	b[1] = display_base + 0x70004 + 0x1000 * pipe;
+	b[2] = (1 << 31) | (y1 << 16) | y2;
+	b[3] = MI_WAIT_FOR_EVENT | event;
+
+	sna->kgem.batch_flags |= I915_EXEC_SECURE;
+	return true;
+}
+
+static bool sna_emit_wait_for_scanline_ivb(struct sna *sna,
+					   xf86CrtcPtr crtc,
+					   int pipe, int y1, int y2,
+					   bool full_height)
+{
+	uint32_t event, *b;
 
 	if (!sna->kgem.has_secure_batches)
 		return false;
@@ -3745,11 +3789,6 @@ static bool sna_emit_wait_for_scanline_ivb(struct sna *sna,
 		break;
 	}
 
-	if (sna->kgem.gen == 071)
-		forcewake = 0x1300b0; /* FORCEWAKE_VLV */
-	else
-		forcewake = 0xa188; /* FORCEWAKE_MT */
-
 	b = kgem_get_batch(&sna->kgem);
 
 	/* Both the LRI and WAIT_FOR_EVENT must be in the same cacheline */
@@ -3764,14 +3803,14 @@ static bool sna_emit_wait_for_scanline_ivb(struct sna *sna,
 	b[1] = 0x44050; /* DERRMR */
 	b[2] = ~event;
 	b[3] = MI_LOAD_REGISTER_IMM | 1;
-	b[4] = forcewake;
+	b[4] = 0xa188; /* FORCEWAKE_MT */
 	b[5] = 2 << 16 | 2;
 	b[6] = MI_LOAD_REGISTER_IMM | 1;
 	b[7] = 0x70068 + 0x1000 * pipe;
 	b[8] = (1 << 31) | (1 << 30) | (y1 << 16) | y2;
 	b[9] = MI_WAIT_FOR_EVENT | event;
 	b[10] = MI_LOAD_REGISTER_IMM | 1;
-	b[11] = forcewake;
+	b[11] = 0xa188; /* FORCEWAKE_MT */
 	b[12] = 2 << 16;
 	b[13] = MI_LOAD_REGISTER_IMM | 1;
 	b[14] = 0x44050; /* DERRMR */
@@ -3936,6 +3975,8 @@ sna_wait_for_scanline(struct sna *sna,
 		ret = false;
 	else if (sna->kgem.gen >= 075)
 		ret = sna_emit_wait_for_scanline_hsw(sna, crtc, pipe, y1, y2, full_height);
+	else if (sna->kgem.gen == 071)
+		ret = sna_emit_wait_for_scanline_vlv(sna, crtc, pipe, y1, y2, full_height);
 	else if (sna->kgem.gen >= 070)
 		ret = sna_emit_wait_for_scanline_ivb(sna, crtc, pipe, y1, y2, full_height);
 	else if (sna->kgem.gen >= 060)