xf86-video-intel: src/intel_driver.h src/intel_module.c

[Chris Wilson]

 src/intel_driver.h |   15 +++++++++++++++
 src/intel_module.c |   14 ++++++++++++++
 2 files changed, 29 insertions(+)

New commits:
commit ab576a42650d8a743dd91108f774c220d866de95
Author: Chris Wilson <chris at chris-wilson.co.uk>
Date:   Sat Apr 27 12:06:30 2013 +0100

    Add all reserved PCI-IDs for Haswell
    
    There is a tendency for a product to ship based on a 'reserved' PCI-ID
    prior to us being notified about it. In other words, the first we find
    out about such a product is when customers start complaining about their
    shiny new hardware not being supported...
    
    References: https://bugs.freedesktop.org/show_bug.cgi?id=63701
    Signed-off-by: Chris Wilson <chris at chris-wilson.co.uk>

diff --git a/src/intel_driver.h b/src/intel_driver.h
index 0dda5b1..d109c7e 100644
--- a/src/intel_driver.h
+++ b/src/intel_driver.h
@@ -201,6 +201,10 @@
 #define PCI_CHIP_HASWELL_S_GT1		0x040A
 #define PCI_CHIP_HASWELL_S_GT2		0x041A
 #define PCI_CHIP_HASWELL_S_GT2_PLUS	0x042A
+#define PCI_CHIP_HASWELL_GT1_RSVD		0x040E
+#define PCI_CHIP_HASWELL_GT2_RSVD		0x041E
+#define PCI_CHIP_HASWELL_GT2_PLUS_RSVD		0x042E
+
 #define PCI_CHIP_HASWELL_SDV_D_GT1	0x0C02
 #define PCI_CHIP_HASWELL_SDV_D_GT2	0x0C12
 #define PCI_CHIP_HASWELL_SDV_D_GT2_PLUS	0x0C22
@@ -210,6 +214,10 @@
 #define PCI_CHIP_HASWELL_SDV_S_GT1	0x0C0A
 #define PCI_CHIP_HASWELL_SDV_S_GT2	0x0C1A
 #define PCI_CHIP_HASWELL_SDV_S_GT2_PLUS	0x0C2A
+#define PCI_CHIP_HASWELL_SDV_GT1_RSVD		0x0C0E
+#define PCI_CHIP_HASWELL_SDV_GT2_RSVD		0x0C1E
+#define PCI_CHIP_HASWELL_SDV_GT2_PLUS_RSVD	0x0C2E
+
 #define PCI_CHIP_HASWELL_ULT_D_GT1	0x0A02
 #define PCI_CHIP_HASWELL_ULT_D_GT2	0x0A12
 #define PCI_CHIP_HASWELL_ULT_D_GT2_PLUS	0x0A22
@@ -219,6 +227,10 @@
 #define PCI_CHIP_HASWELL_ULT_S_GT1	0x0A0A
 #define PCI_CHIP_HASWELL_ULT_S_GT2	0x0A1A
 #define PCI_CHIP_HASWELL_ULT_S_GT2_PLUS	0x0A2A
+#define PCI_CHIP_HASWELL_ULT_GT1_RSVD		0x0A0E
+#define PCI_CHIP_HASWELL_ULT_GT2_RSVD		0x0A1E
+#define PCI_CHIP_HASWELL_ULT_GT2_PLUS_RSVD	0x0A2E
+
 #define PCI_CHIP_HASWELL_CRW_D_GT1	0x0D02
 #define PCI_CHIP_HASWELL_CRW_D_GT2	0x0D12
 #define PCI_CHIP_HASWELL_CRW_D_GT2_PLUS	0x0D22
@@ -228,6 +240,9 @@
 #define PCI_CHIP_HASWELL_CRW_S_GT1	0x0D0A
 #define PCI_CHIP_HASWELL_CRW_S_GT2	0x0D1A
 #define PCI_CHIP_HASWELL_CRW_S_GT2_PLUS	0x0D2A
+#define PCI_CHIP_HASWELL_CRW_GT1_RSVD		0x0D0E
+#define PCI_CHIP_HASWELL_CRW_GT2_RSVD		0x0D1E
+#define PCI_CHIP_HASWELL_CRW_GT2_PLUS_RSVD	0x0D2E
 
 #define PCI_CHIP_VALLEYVIEW_PO		0x0f30
 #define PCI_CHIP_VALLEYVIEW_1		0x0f31
diff --git a/src/intel_module.c b/src/intel_module.c
index 4434ed0..73cfa97 100644
--- a/src/intel_module.c
+++ b/src/intel_module.c
@@ -277,6 +277,10 @@ static const struct pci_id_match intel_device_match[] = {
 	INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_S_GT1, &intel_haswell_info ),
 	INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_S_GT2, &intel_haswell_info ),
 	INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_S_GT2_PLUS, &intel_haswell_info ),
+	INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_GT1_RSVD, &intel_haswell_info ),
+	INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_GT2_RSVD, &intel_haswell_info ),
+	INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_GT2_PLUS_RSVD, &intel_haswell_info ),
+
 	INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_SDV_D_GT1, &intel_haswell_info ),
 	INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_SDV_D_GT2, &intel_haswell_info ),
 	INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_SDV_D_GT2_PLUS, &intel_haswell_info ),
@@ -286,6 +290,10 @@ static const struct pci_id_match intel_device_match[] = {
 	INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_SDV_S_GT1, &intel_haswell_info ),
 	INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_SDV_S_GT2, &intel_haswell_info ),
 	INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_SDV_S_GT2_PLUS, &intel_haswell_info ),
+	INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_SDV_GT1_RSVD, &intel_haswell_info ),
+	INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_SDV_GT2_RSVD, &intel_haswell_info ),
+	INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_SDV_GT2_PLUS_RSVD, &intel_haswell_info ),
+
 	INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_ULT_D_GT1, &intel_haswell_info ),
 	INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_ULT_D_GT2, &intel_haswell_info ),
 	INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_ULT_D_GT2_PLUS, &intel_haswell_info ),
@@ -295,6 +303,9 @@ static const struct pci_id_match intel_device_match[] = {
 	INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_ULT_S_GT1, &intel_haswell_info ),
 	INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_ULT_S_GT2, &intel_haswell_info ),
 	INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_ULT_S_GT2_PLUS, &intel_haswell_info ),
+	INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_ULT_GT1_RSVD, &intel_haswell_info ),
+	INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_ULT_GT2_RSVD, &intel_haswell_info ),
+	INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_ULT_GT2_PLUS_RSVD, &intel_haswell_info ),
 	INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_CRW_D_GT1, &intel_haswell_info ),
 	INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_CRW_D_GT2, &intel_haswell_info ),
 	INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_CRW_D_GT2_PLUS, &intel_haswell_info ),
@@ -304,6 +315,9 @@ static const struct pci_id_match intel_device_match[] = {
 	INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_CRW_S_GT1, &intel_haswell_info ),
 	INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_CRW_S_GT2, &intel_haswell_info ),
 	INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_CRW_S_GT2_PLUS, &intel_haswell_info ),
+	INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_CRW_GT1_RSVD, &intel_haswell_info ),
+	INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_CRW_GT2_RSVD, &intel_haswell_info ),
+	INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_CRW_GT2_PLUS_RSVD, &intel_haswell_info ),
 
 	INTEL_DEVICE_MATCH (PCI_CHIP_VALLEYVIEW_PO, &intel_valleyview_info ),
 	INTEL_DEVICE_MATCH (PCI_CHIP_VALLEYVIEW_1, &intel_valleyview_info ),